coreboot-gerrit November 2018

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1699 discussions

Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by chris wang (Code Review) 06 Nov '18

06 Nov '18

chris wang has posted comments on this change. ( https://review.coreboot.org/29469 ) Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... Patch Set 6: (2 comments) Thank you Richard. https://review.coreboot.org/#/c/29469/4//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29469/4//COMMIT_MSG@12 PS4, Line 12: M is controlled by APU_EDP_BK > This makes no sense with the actual code change. […] correct the description and put more explanation here. https://review.coreboot.org/#/c/29469/4/src/soc/amd/stoneyridge/chip.h File src/soc/amd/stoneyridge/chip.h: https://review.coreboot.org/#/c/29469/4/src/soc/amd/stoneyridge/chip.h@66 PS4, Line 66: /* : * This specifies the LVDS/eDP power up sequence time for the delay from : > I see in subsequent patch that it's unit of 4 milliseconds. Add that information here. put more description here. -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 6 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Tue, 06 Nov 2018 09:09:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/lenovo/x201/romstage: Remove duplicated lines
by Peter Lemenkov (Code Review) 06 Nov '18

06 Nov '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29500 Change subject: mb/lenovo/x201/romstage: Remove duplicated lines ...................................................................... mb/lenovo/x201/romstage: Remove duplicated lines These lines looks redundant. We've set some values before and now we're resetting them. Change-Id: Ib30940e671be8c13a28128bd1e7e6d690283c8cb Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/romstage.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/29500/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 02b9e24..bc2a15b 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -121,8 +121,6 @@ /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, - /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, - /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -- To view, visit https://review.coreboot.org/29500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib30940e671be8c13a28128bd1e7e6d690283c8cb Gerrit-Change-Number: 29500 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: mb/lenovo/x201: Remove unnecessary include - delay.h
by Peter Lemenkov (Code Review) 06 Nov '18

06 Nov '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29499 Change subject: mb/lenovo/x201: Remove unnecessary include - delay.h ...................................................................... mb/lenovo/x201: Remove unnecessary include - delay.h Change-Id: Ia997c5188aef0c18d871658209c2d5f718ee2a19 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/dock.c M src/mainboard/lenovo/x201/romstage.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/29499/1 diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index a11c720..b0e467a 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> -#include <delay.h> #include "dock.h" #include <southbridge/intel/ibexpeak/pch.h> #include "ec/lenovo/h8/h8.h" diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index b6efbd7..02b9e24 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -30,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <ec/acpi/ec.h> -#include <delay.h> #include <timestamp.h> #include <arch/acpi.h> -- To view, visit https://review.coreboot.org/29499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia997c5188aef0c18d871658209c2d5f718ee2a19 Gerrit-Change-Number: 29499 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: mb/lenovo/*/*: Fix non-local header treated as local
by Peter Lemenkov (Code Review) 06 Nov '18

06 Nov '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29501 Change subject: mb/lenovo/*/*: Fix non-local header treated as local ...................................................................... mb/lenovo/*/*: Fix non-local header treated as local See also commit 4ad1446b with Change-Id I036208a111d009620d8354fa9c97688eb4e872ad ("Fix non-local header treated as local"). Change-Id: Idea19b52198e6f46b0da6022558a46246a52f2e7 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t400/dock.c M src/mainboard/lenovo/x200/dock.c M src/mainboard/lenovo/x201/dock.c M src/mainboard/lenovo/x201/romstage.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/29501/1 diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 0c6db0b..3d92a79 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -26,7 +26,7 @@ #include <superio/nsc/pc87382/pc87382.h> #include <southbridge/intel/i82801ix/i82801ix.h> -#include "ec/lenovo/h8/h8.h" +#include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> struct pin_config { diff --git a/src/mainboard/lenovo/x200/dock.c b/src/mainboard/lenovo/x200/dock.c index 5bf2cd3..dc5eabf 100644 --- a/src/mainboard/lenovo/x200/dock.c +++ b/src/mainboard/lenovo/x200/dock.c @@ -23,7 +23,7 @@ #include <delay.h> #include "dock.h" #include <southbridge/intel/i82801ix/i82801ix.h> -#include "ec/lenovo/h8/h8.h" +#include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> #define LPC_DEV PCI_DEV(0, 0x1f, 0) diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index b0e467a..a25fc70 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -22,7 +22,7 @@ #include <device/pci.h> #include "dock.h" #include <southbridge/intel/ibexpeak/pch.h> -#include "ec/lenovo/h8/h8.h" +#include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> void h8_mainboard_init_dock (void) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index bc2a15b..d2100fa 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -34,7 +34,7 @@ #include <arch/acpi.h> #include "dock.h" -#include "arch/early_variables.h" +#include <arch/early_variables.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> #include <northbridge/intel/nehalem/nehalem.h> -- To view, visit https://review.coreboot.org/29501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idea19b52198e6f46b0da6022558a46246a52f2e7 Gerrit-Change-Number: 29501 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: mb/lenovo/x201/gpio: Use reset structure
by Peter Lemenkov (Code Review) 06 Nov '18

06 Nov '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29498 Change subject: mb/lenovo/x201/gpio: Use reset structure ...................................................................... mb/lenovo/x201/gpio: Use reset structure This structure was defined but never used. Let's use it. Change-Id: I73baf428a7300e64fa486699e82ef62c6a53ea60 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/x201/gpio.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29498/1 diff --git a/src/mainboard/lenovo/x201/gpio.c b/src/mainboard/lenovo/x201/gpio.c index 0a40ce6..76872ec 100644 --- a/src/mainboard/lenovo/x201/gpio.c +++ b/src/mainboard/lenovo/x201/gpio.c @@ -380,6 +380,7 @@ .mode = &pch_gpio_set1_mode, .direction = &pch_gpio_set1_direction, .level = &pch_gpio_set1_level, + .reset = &pch_gpio_set1_reset, .blink = &pch_gpio_set1_blink, .invert = &pch_gpio_set1_invert, }, -- To view, visit https://review.coreboot.org/29498 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I73baf428a7300e64fa486699e82ef62c6a53ea60 Gerrit-Change-Number: 29498 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by chris wang (Code Review) 06 Nov '18

06 Nov '18

Hello Chris Wang, Richard Spiegel, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29469 to look at the new patch set (#6). Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... mb/google/kahlee: edp panel initialization time tuning 1.adding two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2.the BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEM_L,so to change APU_EDP_BKLTEN_L to low as default, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/soc/amd/stoneyridge/chip.h 3 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29469/6 -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 6 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com>

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Change in coreboot[master]: security/vboot: Add VB2_LIB to postcar stage if available
by Werner Zeh (Code Review) 06 Nov '18

06 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29465 ) Change subject: security/vboot: Add VB2_LIB to postcar stage if available ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29465/1/src/security/vboot/Makefile.inc File src/security/vboot/Makefile.inc: https://review.coreboot.org/#/c/29465/1/src/security/vboot/Makefile.inc@115 PS1, Line 115: ifeq ($(CONFIG_POSTCAR_STAGE), y) > I don't think you need to guard this, actually. […] Well, I was adviced to do so by Patrick. But at the second glance you seem to be right. This just adds the VB2_LIB to the sources of the postcar. Should be OK to do it unconditionally. @Patrick: Have we overseen something? -- To view, visit https://review.coreboot.org/29465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I933d33b0188d1b123bb4735722b6086e7786624f Gerrit-Change-Number: 29465 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 08:36:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by chris wang (Code Review) 06 Nov '18

06 Nov '18

Hello Chris Wang, Richard Spiegel, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29469 to look at the new patch set (#5). Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... mb/google/kahlee: edp panel initialization time tuning 1.adding two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2.the BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/ EDP_BKLTEM_L,so to change APU_EDP_BKLTEN_L to low as default, thus we can control the delay time by config APU_DP_VARY_BL. BUG=b:118011567 TEST=emerge-grunt coreboot Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/soc/amd/stoneyridge/chip.h 3 files changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29469/5 -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 5 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com>

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Change in coreboot[master]: src/mainboard/portwell/m107: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 06 Nov '18

06 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29470 ) Change subject: src/mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/29470/3/src/mainboard/portwell/m107/irqrout… File src/mainboard/portwell/m107/irqroute.h: https://review.coreboot.org/#/c/29470/3/src/mainboard/portwell/m107/irqrout… PS3, Line 39: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/29470/3/src/mainboard/portwell/m107/irqrout… PS3, Line 60: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 08:23:16 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/mainboard/portwell/m107: Do initial mainboard commit
by Frans Hendriks (Code Review) 06 Nov '18

06 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29470 to look at the new patch set (#3). Change subject: src/mainboard/portwell/m107: Do initial mainboard commit ...................................................................... src/mainboard/portwell/m107: Do initial mainboard commit No support for Portwell PQ7-M107. Create (braswell) board based on Intel Strago. BUG=N/A TEST=Portwell PQ7-M107 Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A src/mainboard/portwell/Kconfig A src/mainboard/portwell/Kconfig.name A src/mainboard/portwell/m107/Kconfig A src/mainboard/portwell/m107/Kconfig.name A src/mainboard/portwell/m107/Makefile.inc A src/mainboard/portwell/m107/acpi/dptf.asl A src/mainboard/portwell/m107/acpi/ec.asl A src/mainboard/portwell/m107/acpi/mainboard.asl A src/mainboard/portwell/m107/acpi/sleepstates.asl A src/mainboard/portwell/m107/acpi/superio.asl A src/mainboard/portwell/m107/acpi_tables.c A src/mainboard/portwell/m107/board_info.txt A src/mainboard/portwell/m107/cmos.layout A src/mainboard/portwell/m107/com_init.c A src/mainboard/portwell/m107/devicetree.cb A src/mainboard/portwell/m107/dsdt.asl A src/mainboard/portwell/m107/fadt.c A src/mainboard/portwell/m107/gpio.c A src/mainboard/portwell/m107/hda_verb.c A src/mainboard/portwell/m107/irqroute.c A src/mainboard/portwell/m107/irqroute.h A src/mainboard/portwell/m107/mainboard.c A src/mainboard/portwell/m107/onboard.h A src/mainboard/portwell/m107/romstage.c A src/mainboard/portwell/m107/smihandler.c A src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/portwell/m107/w25q64.c 27 files changed, 1,609 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29470/3 -- To view, visit https://review.coreboot.org/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018