coreboot-gerrit November 2018

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Change in coreboot[master]: riscv: add support to select the privilege level of the payload running
by Xiang Wang (Code Review) 05 Nov '18

05 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29494 to look at the new patch set (#2). Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... riscv: add support to select the privilege level of the payload running Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/arch/riscv/include/arch/boot.h D src/arch/riscv/payload.S A src/arch/riscv/payload.c 6 files changed, 78 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29494/2 -- To view, visit https://review.coreboot.org/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 2 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add support to select the privilege level of the payload running
by Xiang Wang (Code Review) 05 Nov '18

05 Nov '18

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/29494 Change subject: riscv: add support to select the privilege level of the payload running ...................................................................... riscv: add support to select the privilege level of the payload running Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/arch/riscv/include/arch/boot.h D src/arch/riscv/payload.S A src/arch/riscv/payload.c 6 files changed, 79 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29494/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index ae83be8..aeaed32 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -38,3 +38,25 @@ config RISCV_WORKING_HARTID int + +config RISCV_PAYLOAD_MODE + int + default 0 if RISCV_PAYLOAD_U_MODE + default 1 if RISCV_PAYLOAD_S_MODE + default 3 if RISCV_PAYLOAD_M_MODE + +choice + prompt "***Privilege level for payload***" + default RISCV_PAYLOAD_S_MODE + +config RISCV_PAYLOAD_U_MODE + bool "payload running in u-mode" + + +config RISCV_PAYLOAD_S_MODE + bool "payload running in s-mode" + +config RISCV_PAYLOAD_M_MODE + bool "payload running in m-mode" + +endchoice diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index eacf32a..37570f7 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -124,7 +124,7 @@ ramstage-y += smp.c ramstage-y += boot.c ramstage-y += tables.c -ramstage-y += payload.S +ramstage-y += payload.c ramstage-y += pmp.c ramstage-y += \ $(top)/src/lib/memchr.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 8b8f365..67fbb17 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -34,7 +34,6 @@ { const void *fdt = HLS()->fdt; void (*doit)(void *) = prog_entry(prog); - void riscvpayload(const void *fdt, void *payload); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { /* @@ -45,7 +44,10 @@ printk(BIOS_SPEW, "FDT is at %p\n", fdt); printk(BIOS_SPEW, "OK, let's go\n"); - riscvpayload(fdt, doit); + void (*fn)(uintptr_t arg0, uintptr_t arg1) = prog_entry(prog); + uintptr_t arg0 = read_csr(mhartid); + uintptr_t arg1 = (uintptr_t)fdt; + run_payload(fn, arg0, arg1); } write_csr(mscratch, fdt); diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h index 24c1bed..4c9158a 100644 --- a/src/arch/riscv/include/arch/boot.h +++ b/src/arch/riscv/include/arch/boot.h @@ -16,6 +16,12 @@ #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H +#include <stdint.h> + extern const void *rom_fdt; +void run_payload( + void (*fn)(uintptr_t arg0, uintptr_t arg1), + uintptr_t arg0, + uintptr_t arg1); #endif diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S deleted file mode 100644 index 1b8cb96..0000000 --- a/src/arch/riscv/payload.S +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc - * Copyright (C) 2018 Jonathan Neuschäfer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// "return" to a payload. a0: FDT, a1: entry point - .global riscvpayload -riscvpayload: - /* Load the entry point */ - mv t0, a1 - csrw mepc, t0 - csrr t0, mstatus - - /* Set mstatus.MPP (the previous privilege mode) to supervisor mode */ - li t1, ~(3<<11) - and t0, t0, t1 - li t2, (1<<11) - or t0, t0, t2 - csrw mstatus, t0 - - /* Pass the right arguments and jump! */ - mv a1, a0 - csrr a0, mhartid - mret diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c new file mode 100644 index 0000000..de87ac7 --- /dev/null +++ b/src/arch/riscv/payload.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/boot.h> +#include <arch/encoding.h> +#include <console/console.h> + +void run_payload( + void (*fn)(uintptr_t arg0, uintptr_t arg1), + uintptr_t arg0, + uintptr_t arg1) +{ + uintptr_t status = read_csr(mstatus) & ~MSTATUS_MPP; + switch (CONFIG_RISCV_PAYLOAD_MODE) { + case 0: + break; + case 1: + status |= MSTATUS_SPP; + break; + case 3: + status |= MSTATUS_MPP; + break; + default: + die("wrong privilege level for payload"); + break; + } + write_csr(mstatus, status); + write_csr(mepc, fn); + asm volatile("mv a0, %0"::"r"(arg0):"a0"); + asm volatile("mv a1, %0"::"r"(arg1):"a1"); + asm volatile("mret"); +} + -- To view, visit https://review.coreboot.org/29494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951 Gerrit-Change-Number: 29494 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>

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Change in coreboot[master]: [wip]mb/google/sarien: Add HD Audio verb table
by Lijian Zhao (Code Review) 05 Nov '18

05 Nov '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/29484 ) Change subject: [wip]mb/google/sarien: Add HD Audio verb table ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29484/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29484/3//COMMIT_MSG@12 PS3, Line 12: BUG=N/A > Please use these BUG ID's: 119058355,119054586 Done -- To view, visit https://review.coreboot.org/29484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Gerrit-Change-Number: 29484 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 01:45:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [wip]mb/google/sarien: Add HD Audio verb table
by Lijian Zhao (Code Review) 05 Nov '18

05 Nov '18

Hello Jairaj Arava, Bora Guvendik, Sathyanarayana Nujella, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29484 to look at the new patch set (#5). Change subject: [wip]mb/google/sarien: Add HD Audio verb table ...................................................................... [wip]mb/google/sarien: Add HD Audio verb table Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google sarien and arcada board. BUG=b:119058355,119054586 Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/hda_verb.c A src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h A src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h 5 files changed, 377 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29484/5 -- To view, visit https://review.coreboot.org/29484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Gerrit-Change-Number: 29484 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [wip]mb/google/sarien: Add HD Audio verb table
by Lijian Zhao (Code Review) 05 Nov '18

05 Nov '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/29484 ) Change subject: [wip]mb/google/sarien: Add HD Audio verb table ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29484/3/src/mainboard/google/sarien/Kconfig File src/mainboard/google/sarien/Kconfig: https://review.coreboot.org/#/c/29484/3/src/mainboard/google/sarien/Kconfig… PS3, Line 21: select SOC_INTEL_COMMON_BLOCK_HDA_VERB > I think the other flags are in alphabetical order, can you move this one up. Done -- To view, visit https://review.coreboot.org/29484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Gerrit-Change-Number: 29484 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 01:42:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [wip]mb/google/sarien: Add HD Audio verb table
by Lijian Zhao (Code Review) 05 Nov '18

05 Nov '18

Hello Jairaj Arava, Bora Guvendik, Sathyanarayana Nujella, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29484 to look at the new patch set (#4). Change subject: [wip]mb/google/sarien: Add HD Audio verb table ...................................................................... [wip]mb/google/sarien: Add HD Audio verb table Implement HD Audio verb table for RealTek ALC 3204 codec on google sarien and arcada board. BUG=N/A Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/Makefile.inc A src/mainboard/google/sarien/hda_verb.c A src/mainboard/google/sarien/variants/arcada/include/variant/hda_verb.h A src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h 5 files changed, 377 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29484/4 -- To view, visit https://review.coreboot.org/29484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Gerrit-Change-Number: 29484 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: ish: enable for Sarien
by Li1 Feng (Code Review) 05 Nov '18

05 Nov '18

Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/29493 Change subject: ish: enable for Sarien ...................................................................... ish: enable for Sarien WIP: not merge C12/C13 is configured for ISH UART1 Signed-off-by: li feng <li1.feng(a)intel.com> Change-Id: Ibdb9eae3bb5e8beef3b6727ef8aae88d16893666 --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29493/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 1360b3f..55c2d11 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -106,6 +106,7 @@ device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on end # SA Thermal device device pci 12.0 on end # Thermal Subsystem + device pci 13.0 on end # ISH device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on end # USB xHCI diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 690af1f..95e395f 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -82,9 +82,8 @@ /* UART0_TXD */ PAD_NC(GPP_C9, NONE), /* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ /* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ -/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ /* UART1_CTS# */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ -- To view, visit https://review.coreboot.org/29493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibdb9eae3bb5e8beef3b6727ef8aae88d16893666 Gerrit-Change-Number: 29493 Gerrit-PatchSet: 1 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com>

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Change in coreboot[master]: mb/google/sarien: Program HD Audio SVID/SSID
by Lijian Zhao (Code Review) 05 Nov '18

05 Nov '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/29492 Change subject: mb/google/sarien: Program HD Audio SVID/SSID ...................................................................... mb/google/sarien: Program HD Audio SVID/SSID Realtek Codec kernel driver requires PCH HD Audio controller to have subvendor id and subsystem id matched with verb table. Program same values to make it working. BUG=N/A TEST=Boot up on Sarien board and check with kernel driver dmesg to see ALC3204 or ALC3254. Change-Id: I3c08da2daf8539864ea3f9aa04ccf488e2844da5 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/google/sarien/ramstage.c A src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h A src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h 3 files changed, 64 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/29492/1 diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index c65104b..cb04fbd 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <soc/ramstage.h> #include <variant/gpio.h> +#include <variant/ssid.h> #include <vendorcode/google/chromeos/chromeos.h> void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -25,6 +26,11 @@ gpio_table = variant_gpio_table(&num_gpios); gpio_configure_pads(gpio_table, num_gpios); + + /* Update PCH HDA SVID/SSID */ + params->SiSsidTablePtr = (uint32_t)ssidtblptr; + params->SiNumberOfSsidTableEntry = + (sizeof(ssidtblptr) / sizeof(svid_ssid_init_entry)); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h b/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h new file mode 100644 index 0000000..66df0cc --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/ssid.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef VARIANT_SSID_H +#define VARIANT_SSID_H + +#include <device/pci_ids.h> +#include <soc/intel/common/ssid.h> + +#define HDA_FUNC 3 +#define ALC_SSID 0x08b6 + +svid_ssid_init_entry ssidtblptr[] = { + {{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }}, + {PCI_VENDOR_ID_DELL, ALC_SSID}, 0 }, +}; + +#endif diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h b/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h new file mode 100644 index 0000000..79bf1c3 --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/ssid.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef VARIANT_SSID_H +#define VARIANT_SSID_H + +#include <device/pci_ids.h> +#include <soc/intel/common/ssid.h> + +#define HDA_FUNC 3 +#define ALC_SSID 0x08b8 + +svid_ssid_init_entry ssidtblptr[] = { + {{{PCI_SUBSYSTEM_VENDOR_ID, HDA_FUNC, PCH_DEV_SLOT_LPC, 0, 0, 0, 0 }}, + {PCI_VENDOR_ID_DELL, ALC_SSID}, 0 }, +}; + +#endif -- To view, visit https://review.coreboot.org/29492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3c08da2daf8539864ea3f9aa04ccf488e2844da5 Gerrit-Change-Number: 29492 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: ish: enable ISH in Fircrest
by Li1 Feng (Code Review) 05 Nov '18

05 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29491 to look at the new patch set (#2). Change subject: ish: enable ISH in Fircrest ...................................................................... ish: enable ISH in Fircrest WIP: not merge. In Fircrest enabled C12, C13 NF1 for ISH UART1 Change-Id: If171036218b15e16c288127ba925857221cabf60 Signed-off-by: li feng <li1.feng(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/sarien/variants/sarien/gpio.c 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/29491/2 -- To view, visit https://review.coreboot.org/29491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If171036218b15e16c288127ba925857221cabf60 Gerrit-Change-Number: 29491 Gerrit-PatchSet: 2 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [wip]mb/google/sarien: Add HD Audio verb table
by Bora Guvendik (Code Review) 05 Nov '18

05 Nov '18

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/29484 ) Change subject: [wip]mb/google/sarien: Add HD Audio verb table ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29484/3/src/mainboard/google/sarien/Kconfig File src/mainboard/google/sarien/Kconfig: https://review.coreboot.org/#/c/29484/3/src/mainboard/google/sarien/Kconfig… PS3, Line 21: select SOC_INTEL_COMMON_BLOCK_HDA_VERB I think the other flags are in alphabetical order, can you move this one up. -- To view, visit https://review.coreboot.org/29484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Gerrit-Change-Number: 29484 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 00:58:38 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018