coreboot-gerrit September 2017

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Change in coreboot[master]: debug reboot
by Marc Jones (Code Review) 29 Sep '17

29 Sep '17

Marc Jones has abandoned this change. ( https://review.coreboot.org/21761 ) Change subject: debug reboot ...................................................................... Abandoned debug code... -- To view, visit https://review.coreboot.org/21761 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I08a4bc7ea7023383d7d05118d42340857bfc439c Gerrit-Change-Number: 21761 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: arch/riscv: Return from trap_handler instead of jumping out
by Jonathan Neuschäfer (Code Review) 29 Sep '17

29 Sep '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21764 Change subject: arch/riscv: Return from trap_handler instead of jumping out ...................................................................... arch/riscv: Return from trap_handler instead of jumping out Change-Id: I8dbed5dbe377d3a02e58a3bc16a1ee112b28bea9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S 2 files changed, 3 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21764/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 78b98e4..1f13bed 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -69,7 +69,6 @@ } tf->gpr[10] = returnValue; write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } static const char *const exception_names[] = { @@ -210,16 +209,16 @@ case CAUSE_MISALIGNED_LOAD: print_trap_information(tf); handle_misaligned_load(tf); - break; + return; case CAUSE_MISALIGNED_STORE: print_trap_information(tf); handle_misaligned_store(tf); - break; + return; case CAUSE_SUPERVISOR_ECALL: /* Don't print so we make console putchar calls look the way they should */ handle_supervisor_call(tf); - break; + return; default: printk(BIOS_EMERG, "================================\n"); printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); @@ -262,7 +261,6 @@ // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } void handle_misaligned_store(trapframe *tf) { @@ -290,5 +288,4 @@ // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j trap_return"); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 5add7ba..601862d 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -137,7 +137,6 @@ move a0,sp jal trap_handler - .global trap_return trap_return: csrr a0, mscratch restore_regs -- To view, visit https://review.coreboot.org/21764 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8dbed5dbe377d3a02e58a3bc16a1ee112b28bea9 Gerrit-Change-Number: 21764 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: arch/riscv: Unify trap return
by Jonathan Neuschäfer (Code Review) 29 Sep '17

29 Sep '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21763 Change subject: arch/riscv: Unify trap return ...................................................................... arch/riscv: Unify trap return Change-Id: I9de0c92b3f925e8f4db00d7281222a07db68b2ae Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S 2 files changed, 10 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/21763/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 4359ed9..78b98e4 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -69,7 +69,7 @@ } tf->gpr[10] = returnValue; write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j supervisor_call_return"); + asm volatile("j trap_return"); } static const char *const exception_names[] = { @@ -262,7 +262,7 @@ // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j machine_call_return"); + asm volatile("j trap_return"); } void handle_misaligned_store(trapframe *tf) { @@ -290,5 +290,5 @@ // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j machine_call_return"); + asm volatile("j trap_return"); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 44cfab7..5add7ba 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -136,15 +136,10 @@ save_tf move a0,sp jal trap_handler - .global supervisor_call_return -supervisor_call_return: - csrr a0, mscratch - restore_regs - # go back into supervisor call - mret - .global machine_call_return -machine_call_return: - csrr a0, mscratch - restore_regs - # go back into machine call - mret + + .global trap_return +trap_return: + csrr a0, mscratch + restore_regs + # go back to the previous mode + mret -- To view, visit https://review.coreboot.org/21763 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9de0c92b3f925e8f4db00d7281222a07db68b2ae Gerrit-Change-Number: 21763 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: arch/riscv: Drop mret workaround
by Jonathan Neuschäfer (Code Review) 29 Sep '17

29 Sep '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21762 Change subject: arch/riscv: Drop mret workaround ...................................................................... arch/riscv: Drop mret workaround Our toolchain can compile mret now, and once the encoding changes, we'll have to adjust the code anyway. Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/riscv/payload.S M src/arch/riscv/trap_util.S 2 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/21762/1 diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S index ce88bc3..a189adf 100644 --- a/src/arch/riscv/payload.S +++ b/src/arch/riscv/payload.S @@ -24,7 +24,4 @@ li t2, (1<<11) or t0, t0, t2 csrw mstatus, t0 - - // We're still in toolchain no mans land. - .word 0x30200073 - //mret + mret diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index ae32379..44cfab7 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -141,10 +141,10 @@ csrr a0, mscratch restore_regs # go back into supervisor call - .word 0x30200073 # mret + mret .global machine_call_return machine_call_return: csrr a0, mscratch restore_regs # go back into machine call - .word 0x30200073 # mret + mret -- To view, visit https://review.coreboot.org/21762 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c Gerrit-Change-Number: 21762 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: debug reboot
by Marc Jones (Code Review) 29 Sep '17

29 Sep '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/21761 Change subject: debug reboot ...................................................................... debug reboot Change-Id: I08a4bc7ea7023383d7d05118d42340857bfc439c Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/lib/bootblock.c M src/lib/prog_loaders.c M src/soc/amd/common/agesawrapper.c M src/soc/amd/common/def_callouts.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/reset.c 7 files changed, 23 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/21761/1 diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 2e228c6..52c5cca 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -48,7 +48,9 @@ } bootblock_soc_init(); + post_code(0x66); bootblock_mainboard_init(); + post_code(0x67); run_romstage(); } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 128869b..f9f4492 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -52,19 +52,19 @@ { struct prog romstage = PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); - +post_code(0x50); if (prog_locate(&romstage)) goto fail; - +post_code(0x51); timestamp_add_now(TS_START_COPYROM); if (cbfs_prog_stage_load(&romstage)) goto fail; - +post_code(0x52); timestamp_add_now(TS_END_COPYROM); prog_run(&romstage); - +post_code(0x53); fail: if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) die("Couldn't load romstage.\n"); diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index b95d61a..876fe31 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -71,10 +71,12 @@ AmdResetParams.FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3)); AmdResetParams.FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); - + post_code(0x60); status = AmdInitReset(&AmdResetParams); + post_code(0x61); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); + post_code(0x62); return status; } @@ -101,11 +103,12 @@ OemCustomizeInitEarly (AmdEarlyParamsPtr); AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled; + post_code(0x63); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - +post_code(0x64); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); - +post_code(0x65); return status; } diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/def_callouts.c index fda0013..8bce75e 100644 --- a/src/soc/amd/common/def_callouts.c +++ b/src/soc/amd/common/def_callouts.c @@ -16,6 +16,7 @@ #include <cbfs.h> #include <spd_bin.h> +#include <reset.h> #include <AGESA.h> #include <amdlib.h> @@ -60,7 +61,7 @@ AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINT8 Value; + //UINT8 Value; UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader; @@ -80,8 +81,10 @@ case WARM_RESET_IMMEDIATELY: case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite(AccessWidth8, SYS_RESET, &Value, StdHeader); + post_code(0x6E); + hard_reset(); + //Value = 0x06; + //LibAmdIoWrite(AccessWidth8, SYS_RESET, &Value, StdHeader); break; default: diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 06d9f58..4f2d13a 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -52,6 +52,7 @@ romstage-y += gpio.c romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c romstage-y += pmutil.c +romstage-y += reset.c romstage-y += smbus.c romstage-y += smbus_spd.c romstage-y += ramtop.c @@ -74,7 +75,6 @@ ramstage-y += lpc.c ramstage-y += model_15_init.c ramstage-y += northbridge.c -ramstage-y += pmutil.c ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sm.c diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 3f01603..3a1fdc4 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -60,4 +60,5 @@ post_code(0x38); AGESAWRAPPER(amdinitearly); /* APs will not exit amdinitearly */ + post_code(0x39); } diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 73f944d..9f1f060 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <reset.h> #include <soc/southbridge.h> +#include <console/console.h> #define HT_INIT_CONTROL 0x6c #define HTIC_BIOSR_Detect (1 << 5) @@ -34,6 +35,8 @@ void do_hard_reset(void) { + + post_code(0x6F); set_bios_reset(); /* Try rebooting through port 0xcf9 */ /* -- To view, visit https://review.coreboot.org/21761 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I08a4bc7ea7023383d7d05118d42340857bfc439c Gerrit-Change-Number: 21761 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: RISC-V boards: Stop using the config string
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21690 ) Change subject: RISC-V boards: Stop using the config string ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61334/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16478/ : SUCCESS -- To view, visit https://review.coreboot.org/21690 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe Gerrit-Change-Number: 21690 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 04:40:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: AGESA: f15: Fix function name in message
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21760 ) Change subject: AGESA: f15: Fix function name in message ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61333/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16477/ : SUCCESS -- To view, visit https://review.coreboot.org/21760 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b Gerrit-Change-Number: 21760 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 01:24:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: AGESA: f15: Fix function name in message
by Jonathan Neuschäfer (Code Review) 29 Sep '17

29 Sep '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21760 Change subject: AGESA: f15: Fix function name in message ...................................................................... AGESA: f15: Fix function name in message Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/cpu/amd/agesa/family15/romstage.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/21760/1 diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c index e2b58c8..7e65f81 100644 --- a/src/cpu/amd/agesa/family15/romstage.c +++ b/src/cpu/amd/agesa/family15/romstage.c @@ -60,7 +60,7 @@ printk(BIOS_INFO, "...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); - die("After soft_reset_x - shouldn't see this message!!!\n"); + die("After soft_reset - shouldn't see this message!!!\n"); } post_code(0x40); -- To view, visit https://review.coreboot.org/21760 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b Gerrit-Change-Number: 21760 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: amd/stoneyridge: Move pm/smi_read/write functions to util file
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21759 ) Change subject: amd/stoneyridge: Move pm/smi_read/write functions to util file ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61330/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16474/ : SUCCESS -- To view, visit https://review.coreboot.org/21759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 Gerrit-Change-Number: 21759 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 00:43:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21685 ) Change subject: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61332/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16476/ : SUCCESS -- To view, visit https://review.coreboot.org/21685 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Gerrit-Change-Number: 21685 Gerrit-PatchSet: 8 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 00:43:13 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017