Change in coreboot[master]: debug reboot
Marc Jones has uploaded this change for review. ( https://review.coreboot.org/21761 Change subject: debug reboot ...................................................................... debug reboot Change-Id: I08a4bc7ea7023383d7d05118d42340857bfc439c Signed-off-by: Marc Jones <marcj303@gmail.com> --- M src/lib/bootblock.c M src/lib/prog_loaders.c M src/soc/amd/common/agesawrapper.c M src/soc/amd/common/def_callouts.c M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/bootblock/bootblock.c M src/soc/amd/stoneyridge/reset.c 7 files changed, 23 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/21761/1 diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 2e228c6..52c5cca 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -48,7 +48,9 @@ } bootblock_soc_init(); + post_code(0x66); bootblock_mainboard_init(); + post_code(0x67); run_romstage(); } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 128869b..f9f4492 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -52,19 +52,19 @@ { struct prog romstage = PROG_INIT(PROG_ROMSTAGE, CONFIG_CBFS_PREFIX "/romstage"); - +post_code(0x50); if (prog_locate(&romstage)) goto fail; - +post_code(0x51); timestamp_add_now(TS_START_COPYROM); if (cbfs_prog_stage_load(&romstage)) goto fail; - +post_code(0x52); timestamp_add_now(TS_END_COPYROM); prog_run(&romstage); - +post_code(0x53); fail: if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) die("Couldn't load romstage.\n"); diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index b95d61a..876fe31 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -71,10 +71,12 @@ AmdResetParams.FchInterface.SataEnable = !((CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3)); AmdResetParams.FchInterface.IdeEnable = (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3); - + post_code(0x60); status = AmdInitReset(&AmdResetParams); + post_code(0x61); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); + post_code(0x62); return status; } @@ -101,11 +103,12 @@ OemCustomizeInitEarly (AmdEarlyParamsPtr); AmdEarlyParamsPtr->GnbConfig.PsppPolicy = PsppDisabled; + post_code(0x63); status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - +post_code(0x64); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); AmdReleaseStruct (&AmdParamStruct); - +post_code(0x65); return status; } diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/def_callouts.c index fda0013..8bce75e 100644 --- a/src/soc/amd/common/def_callouts.c +++ b/src/soc/amd/common/def_callouts.c @@ -16,6 +16,7 @@ #include <cbfs.h> #include <spd_bin.h> +#include <reset.h> #include <AGESA.h> #include <amdlib.h> @@ -60,7 +61,7 @@ AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINT8 Value; + //UINT8 Value; UINTN ResetType; AMD_CONFIG_PARAMS *StdHeader; @@ -80,8 +81,10 @@ case WARM_RESET_IMMEDIATELY: case COLD_RESET_IMMEDIATELY: - Value = 0x06; - LibAmdIoWrite(AccessWidth8, SYS_RESET, &Value, StdHeader); + post_code(0x6E); + hard_reset(); + //Value = 0x06; + //LibAmdIoWrite(AccessWidth8, SYS_RESET, &Value, StdHeader); break; default: diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 06d9f58..4f2d13a 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -52,6 +52,7 @@ romstage-y += gpio.c romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c romstage-y += pmutil.c +romstage-y += reset.c romstage-y += smbus.c romstage-y += smbus_spd.c romstage-y += ramtop.c @@ -74,7 +75,6 @@ ramstage-y += lpc.c ramstage-y += model_15_init.c ramstage-y += northbridge.c -ramstage-y += pmutil.c ramstage-y += reset.c ramstage-y += sata.c ramstage-y += sm.c diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 3f01603..3a1fdc4 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -60,4 +60,5 @@ post_code(0x38); AGESAWRAPPER(amdinitearly); /* APs will not exit amdinitearly */ + post_code(0x39); } diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c index 73f944d..9f1f060 100644 --- a/src/soc/amd/stoneyridge/reset.c +++ b/src/soc/amd/stoneyridge/reset.c @@ -19,6 +19,7 @@ #include <arch/io.h> #include <reset.h> #include <soc/southbridge.h> +#include <console/console.h> #define HT_INIT_CONTROL 0x6c #define HTIC_BIOSR_Detect (1 << 5) @@ -34,6 +35,8 @@ void do_hard_reset(void) { + + post_code(0x6F); set_bios_reset(); /* Try rebooting through port 0xcf9 */ /* -- To view, visit https://review.coreboot.org/21761 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I08a4bc7ea7023383d7d05118d42340857bfc439c Gerrit-Change-Number: 21761 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc@marcjonesconsulting.com>
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