coreboot-gerrit September 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21685 ) Change subject: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61313/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16458/ : SUCCESS -- To view, visit https://review.coreboot.org/21685 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Gerrit-Change-Number: 21685 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 00:14:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Move pm/smi_read/write functions to util file
by Marshall Dawson (Code Review) 29 Sep '17

29 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21759 Change subject: amd/stoneyridge: Move pm/smi_read/write functions to util file ...................................................................... amd/stoneyridge: Move pm/smi_read/write functions to util file Pull all pm_read and write, smi_read and write variants into a single file. Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/southbridge.h A src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/smi.c M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/southbridge.c 7 files changed, 77 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/21759/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 28b3244..daab687 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -74,6 +74,7 @@ ramstage-y += gpio.c ramstage-y += hda.c ramstage-y += southbridge.c +ramstage-y += sb_util.c ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c ramstage-y += lpc.c ramstage-y += model_15_init.c @@ -92,6 +93,7 @@ smm-y += smihandler.c smm-y += smi_util.c +smm-y += sb_util.c smm-y += tsc_freq.c smm-y += uart.c diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 2a0748c..daf7a0c 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -19,9 +19,6 @@ #include <arch/io.h> -/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. */ -#define SMI_BASE 0xfed80200 - #define SMI_SCI_STATUS 0x10 /* SMI source and status */ @@ -195,26 +192,6 @@ SMI_LVL_LOW = 0, SMI_LVL_HIGH = 1, }; - -static inline uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(SMI_BASE + offset)); -} - -static inline void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(SMI_BASE + offset), value); -} - -static inline uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(SMI_BASE + offset)); -} - -static inline void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(SMI_BASE + offset), value); -} void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void disable_gevent_smi(uint8_t gevent); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 7393abc..80fcf87 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -25,10 +25,9 @@ #define IO_APIC2_ADDR 0xfec20000 -/* Offsets from ACPI_MMIO_BASE - * This is defined by AGESA, but we don't include AGESA headers to avoid - * polluting the namespace. - */ +/* Offsets from ACPI_MMIO_BASE */ +#define APU_SMI_BASE 0xfed80200 + #define PM_MMIO_BASE 0xfed80300 #define APU_UART0_BASE 0xfedc6000 @@ -194,6 +193,10 @@ void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); void pm_write32(u8 reg, u32 value); +u16 smi_read16(u8 reg); +u32 smi_read32(u8 reg); +void smi_write16(u8 reg, u16 value); +void smi_write32(u8 reg, u32 value); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c new file mode 100644 index 0000000..87bff70 --- /dev/null +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/southbridge.h> + +void pm_write8(u8 reg, u8 value) +{ + write8((void *)(PM_MMIO_BASE + reg), value); +} + +u8 pm_read8(u8 reg) +{ + return read8((void *)(PM_MMIO_BASE + reg)); +} + +void pm_write16(u8 reg, u16 value) +{ + write16((void *)(PM_MMIO_BASE + reg), value); +} + +u16 pm_read16(u8 reg) +{ + return read16((void *)(PM_MMIO_BASE + reg)); +} + +void pm_write32(u8 reg, u32 value) +{ + write32((void *)(PM_MMIO_BASE + reg), value); +} + +u32 pm_read32(u8 reg) +{ + return read32((void *)(PM_MMIO_BASE + reg)); +} + +void smi_write32(uint8_t offset, uint32_t value) +{ + write32((void *)(APU_SMI_BASE + offset), value); +} + +uint32_t smi_read32(uint8_t offset) +{ + return read32((void *)(APU_SMI_BASE + offset)); +} + +uint16_t smi_read16(uint8_t offset) +{ + return read16((void *)(APU_SMI_BASE + offset)); +} + +void smi_write16(uint8_t offset, uint16_t value) +{ + write16((void *)(APU_SMI_BASE + offset), value); +} diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c index 31ca5d1..1cfbc03 100644 --- a/src/soc/amd/stoneyridge/smi.c +++ b/src/soc/amd/stoneyridge/smi.c @@ -9,6 +9,7 @@ #include <console/console.h> #include <cpu/cpu.h> +#include <soc/southbridge.h> #include <soc/smi.h> void smm_setup_structures(void *gnvs, void *tcg, void *smi1) diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 68e792c..42d651a 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -6,6 +6,7 @@ */ #include <console/console.h> +#include <soc/southbridge.h> #include <soc/smi.h> static void configure_smi(uint8_t smi_num, uint8_t mode) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a829575..fca8041 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -40,36 +40,6 @@ return (int)tmp; } -void pm_write8(u8 reg, u8 value) -{ - write8((void *)(PM_MMIO_BASE + reg), value); -} - -u8 pm_read8(u8 reg) -{ - return read8((void *)(PM_MMIO_BASE + reg)); -} - -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(PM_MMIO_BASE + reg), value); -} - -u16 pm_read16(u8 reg) -{ - return read16((void *)(PM_MMIO_BASE + reg)); -} - -void pm_write32(u8 reg, u32 value) -{ - write32((void *)(PM_MMIO_BASE + reg), value); -} - -u32 pm_read32(u8 reg) -{ - return read32((void *)(PM_MMIO_BASE + reg)); -} - void sb_enable(device_t dev) { printk(BIOS_DEBUG, "%s\n", __func__); -- To view, visit https://review.coreboot.org/21759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 Gerrit-Change-Number: 21759 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/intel/common/block: Update LPC lib
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21605 ) Change subject: soc/intel/common/block: Update LPC lib ...................................................................... Patch Set 18: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61311/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16456/ : SUCCESS -- To view, visit https://review.coreboot.org/21605 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9359765f7293210044b411db49163df0418070a Gerrit-Change-Number: 21605 Gerrit-PatchSet: 18 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 00:10:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: change gpio device name
by Lijian Zhao (Code Review) 29 Sep '17

29 Sep '17

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/21758 ) Change subject: soc/intel/cannonlake: change gpio device name ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/21758 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iace5dc748435b48b50faae6f60a10f1f7ae058ff Gerrit-Change-Number: 21758 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 00:09:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: change gpio device name
by Bora Guvendik (Code Review) 29 Sep '17

29 Sep '17

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/21758 Change subject: soc/intel/cannonlake: change gpio device name ...................................................................... soc/intel/cannonlake: change gpio device name Change-Id: Iace5dc748435b48b50faae6f60a10f1f7ae058ff Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/include/soc/gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/21758/1 diff --git a/src/soc/intel/cannonlake/include/soc/gpio.h b/src/soc/intel/cannonlake/include/soc/gpio.h index 0d97f04..2d9f3d7 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio.h +++ b/src/soc/intel/cannonlake/include/soc/gpio.h @@ -19,6 +19,6 @@ #include <soc/gpio_defs.h> #include <intelblocks/gpio.h> -#define CROS_GPIO_DEVICE_NAME "INT344B:00" +#define CROS_GPIO_DEVICE_NAME "INT34BB:00" #endif -- To view, visit https://review.coreboot.org/21758 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iace5dc748435b48b50faae6f60a10f1f7ae058ff Gerrit-Change-Number: 21758 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
by Bora Guvendik (Code Review) 29 Sep '17

29 Sep '17

Hello Barnali Sarkar, Andrex Andraos, Subrata Banik, AndreX Andraos, Lijian Zhao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21685 to look at the new patch set (#6). Change subject: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO ...................................................................... soc/intel/cannonlake: add initial ASL methods for SCS, GPIO Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/dsdt.asl A src/soc/intel/cannonlake/acpi/gpio.asl A src/soc/intel/cannonlake/acpi/pcr.asl A src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/cannonlake/acpi/southbridge.asl M src/soc/intel/cannonlake/include/soc/gpio_defs.h 6 files changed, 161 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/21685/6 -- To view, visit https://review.coreboot.org/21685 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Gerrit-Change-Number: 21685 Gerrit-PatchSet: 6 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Add smi support in board
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21542 ) Change subject: mainboard/intel/cannonlake_rvp: Add smi support in board ...................................................................... Patch Set 12: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61307/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16452/ : SUCCESS -- To view, visit https://review.coreboot.org/21542 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f363e20a6eb92b3c05e16715aa052a8da18b509 Gerrit-Change-Number: 21542 Gerrit-PatchSet: 12 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 00:04:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add northbridge dsdt table
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21756 ) Change subject: soc/intel/cannonlake: Add northbridge dsdt table ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61310/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16455/ : SUCCESS -- To view, visit https://review.coreboot.org/21756 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc Gerrit-Change-Number: 21756 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 00:02:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Fill the SMI usage
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21543 ) Change subject: soc/intel/cannonlake: Fill the SMI usage ...................................................................... Patch Set 20: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61306/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16450/ : SUCCESS -- To view, visit https://review.coreboot.org/21543 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9aab141c528709b30804d327804c4031c59fcfff Gerrit-Change-Number: 21543 Gerrit-PatchSet: 20 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 23:55:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add lpc pci driver
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21277 ) Change subject: soc/intel/cannonlake: Add lpc pci driver ...................................................................... Patch Set 18: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61305/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16451/ : SUCCESS -- To view, visit https://review.coreboot.org/21277 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Gerrit-Change-Number: 21277 Gerrit-PatchSet: 18 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Wei-nan Liu <wei-nan.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 23:54:17 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017