coreboot-gerrit September 2017

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Change in coreboot[master]: soc/intel/common/block: Move power button SMI functions to common PMC...
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21755 ) Change subject: soc/intel/common/block: Move power button SMI functions to common PMC block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61299/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16444/ : SUCCESS -- To view, visit https://review.coreboot.org/21755 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525 Gerrit-Change-Number: 21755 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 22:40:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Move power button SMI functions to common PMC...
by Shaunak Saha (Code Review) 29 Sep '17

29 Sep '17

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/21755 Change subject: soc/intel/common/block: Move power button SMI functions to common PMC block ...................................................................... soc/intel/common/block: Move power button SMI functions to common PMC block This patch moves the functions update_pm1_enable and read_pm1_enable to common block PMC. We rename the functions to pmc_update_pm1_enable and pmc_read_pm1_enable to keep semantics consistent. Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/21755/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 4093599..fe0a765 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -42,6 +42,11 @@ */ int soc_prev_sleep_state(const struct chipset_power_state *ps, int prev_sleep_state); + +/* PM1 */ +void pmc_update_pm1_enable(uint16_t events); +uint16_t pmc_read_pm1_enable(void); + /* * Function to print, clear, and return SMI status bits in SMI_STS * register. This function internally calls pmc_reset_smi_status with diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index e741332..78b43e4 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -72,6 +72,23 @@ return smi_sts; } +/* + * Update supplied events in PM1_EN register. This does not disable any already + * set events. + */ +void pmc_update_pm1_enable(u16 events) +{ + u16 pm1_en = pmc_read_pm1_enable(); + pm1_en |= events; + pmc_enable_pm1(pm1_en); +} + +/* Read events set in PM1_EN register. */ +uint16_t pmc_read_pm1_enable(void) +{ + return inw(ACPI_BASE_ADDRESS + PM1_EN); +} + uint32_t pmc_clear_smi_status(void) { uint32_t sts = pmc_reset_smi_status(); -- To view, visit https://review.coreboot.org/21755 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525 Gerrit-Change-Number: 21755 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com>

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Change in coreboot[master]: nb/intel: Add Ivy Bridge Server (Xeon-E3v2) PCI IDs
by build bot (Jenkins) (Code Review) 28 Sep '17

28 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21753 ) Change subject: nb/intel: Add Ivy Bridge Server (Xeon-E3v2) PCI IDs ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61298/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16443/ : SUCCESS -- To view, visit https://review.coreboot.org/21753 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05 Gerrit-Change-Number: 21753 Gerrit-PatchSet: 2 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 21:50:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sandybridge/acpi: remove unnessary check of PCI IDs
by build bot (Jenkins) (Code Review) 28 Sep '17

28 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21754 ) Change subject: sandybridge/acpi: remove unnessary check of PCI IDs ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61297/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16442/ : SUCCESS -- To view, visit https://review.coreboot.org/21754 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7 Gerrit-Change-Number: 21754 Gerrit-PatchSet: 2 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 21:45:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sandybridge/acpi: remove unnessary check of PCI IDs
by build bot (Jenkins) (Code Review) 28 Sep '17

28 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21754 ) Change subject: sandybridge/acpi: remove unnessary check of PCI IDs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61295/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16441/ : SUCCESS -- To view, visit https://review.coreboot.org/21754 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7 Gerrit-Change-Number: 21754 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 19:59:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Add Ivy Bridge Server (Xeon-E3v2) PCI IDs
by build bot (Jenkins) (Code Review) 28 Sep '17

28 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21753 ) Change subject: Add Ivy Bridge Server (Xeon-E3v2) PCI IDs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61294/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16440/ : SUCCESS -- To view, visit https://review.coreboot.org/21753 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05 Gerrit-Change-Number: 21753 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 19:51:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sandybridge/acpi: remove unnessary check of PCI IDs
by Vagiz Tarkhanov (Code Review) 28 Sep '17

28 Sep '17

Vagiz Tarkhanov has uploaded this change for review. ( https://review.coreboot.org/21754 Change subject: sandybridge/acpi: remove unnessary check of PCI IDs ...................................................................... sandybridge/acpi: remove unnessary check of PCI IDs DRAM Controller is always 00.0 No need to check its PCI ID. Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7 Signed-off-by: Vagiz Tarkhanov <rakkin(a)autistici.org> --- M src/northbridge/intel/sandybridge/acpi.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/21754/1 diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 658000aa..78225d0 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -26,14 +26,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0); - if (!dev) - dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0); + struct device *const dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return current; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 9d88c70..dd1a58c 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -201,9 +201,6 @@ #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); } -#define PCI_DEVICE_ID_SB 0x0104 -#define PCI_DEVICE_ID_IB 0x0154 - #ifdef __SMM__ void intel_sandybridge_finalize_smm(void); #else /* !__SMM__ */ -- To view, visit https://review.coreboot.org/21754 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7 Gerrit-Change-Number: 21754 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org>

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Change in coreboot[master]: Add Ivy Bridge Server (Xeon-E3v2) PCI IDs
by Vagiz Tarkhanov (Code Review) 28 Sep '17

28 Sep '17

Vagiz Tarkhanov has uploaded this change for review. ( https://review.coreboot.org/21753 Change subject: Add Ivy Bridge Server (Xeon-E3v2) PCI IDs ...................................................................... Add Ivy Bridge Server (Xeon-E3v2) PCI IDs Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05 Signed-off-by: Vagiz Tarkhanov <rakkin(a)autistici.org> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/northbridge.c 3 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/21753/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 3580f35..2f1b790 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -98,6 +98,7 @@ case 0x0156: /* IvyBridge */ case 0x0162: /* IvyBridge */ case 0x0166: /* IvyBridge */ + case 0x016a: /* IvyBridge */ break; default: printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n"); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 029bb05..25c9ea9 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -271,6 +271,7 @@ case 0x80860156: /* IVB GT1 Mobile */ case 0x80860162: /* IVB GT2 Desktop */ case 0x80860166: /* IVB GT2 Mobile */ + case 0x8086016a: /* IVB GT2 Server */ new_vendev = 0x80860106;/* SNB GT1 Mobile */ break; } @@ -756,7 +757,7 @@ static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, - 0x0166, 0x0162, 0x0152, + 0x0166, 0x0162, 0x016a, 0x0152, 0 }; static const struct pci_driver gma __pci_driver = { diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 821da87..9bd50a8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -517,6 +517,13 @@ .device = 0x0154, /* Ivy bridge */ }; +static const struct pci_driver mc_driver_158 __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x0158, /* Ivy bridge */ +}; + + static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); -- To view, visit https://review.coreboot.org/21753 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05 Gerrit-Change-Number: 21753 Gerrit-PatchSet: 1 Gerrit-Owner: Vagiz Tarkhanov <rakkin(a)autistici.org>

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Change in coreboot[master]: soc/intel/skylake: Add support in SKL for PMC common code
by build bot (Jenkins) (Code Review) 28 Sep '17

28 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20499 ) Change subject: soc/intel/skylake: Add support in SKL for PMC common code ...................................................................... Patch Set 18: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61293/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16439/ : SUCCESS -- To view, visit https://review.coreboot.org/20499 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Gerrit-Change-Number: 20499 Gerrit-PatchSet: 18 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 18:37:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add lpc pci driver
by build bot (Jenkins) (Code Review) 28 Sep '17

28 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21277 ) Change subject: soc/intel/cannonlake: Add lpc pci driver ...................................................................... Patch Set 17: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61292/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16438/ : SUCCESS -- To view, visit https://review.coreboot.org/21277 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Gerrit-Change-Number: 21277 Gerrit-PatchSet: 17 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: Wei-nan Liu <wei-nan.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Sep 2017 18:31:31 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017