coreboot-gerrit September 2017

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Change in coreboot[master]: WIP amd/stoneyridge: Add placeholder for SlpTyp handler in SMI
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21751 Change subject: WIP amd/stoneyridge: Add placeholder for SlpTyp handler in SMI ...................................................................... WIP amd/stoneyridge: Add placeholder for SlpTyp handler in SMI The S3 suspend flow involves trapping on a SlpTyp request, writing resume data to flash, then notifying the PSP of the S3 request. Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/21751/1 diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 8551631..2c2bac9 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -41,6 +41,11 @@ mainboard_smi_apmc(cmd); } +static void sb_slp_typ_handler(void) +{ + /* TODO: Insert S3 pre here */ +} + int southbridge_io_trap_handler(int smif) { return 0; @@ -52,6 +57,7 @@ */ struct smi_sources_t smi_sources[] = { {SMITYPE_SMI_CMD_PORT, sb_apmc_smi_handler}, + {SMITYPE_SLP_TYP, sb_slp_typ_handler}, }; static void process_smi_sci(void) -- To view, visit https://review.coreboot.org/21751 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead Gerrit-Change-Number: 21751 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Change SMM setup functions
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21750 Change subject: amd/stoneyridge: Change SMM setup functions ...................................................................... amd/stoneyridge: Change SMM setup functions Remove the APMC-specific initialization call. Make the function which programs the event type not static and call it from the southbridge.c file. Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21750/1 diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index ed4a6c0..d31b8bc 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -222,9 +222,9 @@ } uint16_t pm_acpi_smi_cmd_port(void); +void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void disable_gevent_smi(uint8_t gevent); -void enable_acpi_cmd_smi(void); #ifndef __SMM__ void enable_smi_generation(void); diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 833e6e3..96e9d61 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -9,7 +9,7 @@ #include <soc/southbridge.h> #include <soc/smi.h> -static void configure_smi(uint8_t smi_num, uint8_t mode) +void configure_smi(uint8_t smi_num, uint8_t mode) { uint8_t reg32_offset, bit_offset; uint32_t reg32; @@ -67,12 +67,6 @@ /* SMI0 source is GEVENT0 and so on */ configure_smi(gevent, SMI_MODE_DISABLE); -} - -/** Enable SMIs on writes to ACPI SMI command port */ -void enable_acpi_cmd_smi(void) -{ - configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); } uint16_t pm_acpi_smi_cmd_port(void) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index a829575..b5357a9 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -90,7 +90,7 @@ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { pm_write16(PM_ACPI_SMI_CMD, APM_CNT); - enable_acpi_cmd_smi(); + configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); } else { pm_write16(PM_ACPI_SMI_CMD, 0); } -- To view, visit https://review.coreboot.org/21750 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2 Gerrit-Change-Number: 21750 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21749 Change subject: amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge ...................................................................... amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge Duplicate existing pm_read and pm_write and create 32-bit register access functions. Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/21749/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 054b36a..09dfb54 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -195,8 +195,10 @@ void lpc_wideio_16_window(uint16_t base); u8 pm_read8(u8 reg); u16 pm_read16(u8 reg); +u32 pm_read32(u8 reg); void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); +void pm_write32(u8 reg, u32 value); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 655a15a..a829575 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -60,6 +60,16 @@ return read16((void *)(PM_MMIO_BASE + reg)); } +void pm_write32(u8 reg, u32 value) +{ + write32((void *)(PM_MMIO_BASE + reg), value); +} + +u32 pm_read32(u8 reg) +{ + return read32((void *)(PM_MMIO_BASE + reg)); +} + void sb_enable(device_t dev) { printk(BIOS_DEBUG, "%s\n", __func__); -- To view, visit https://review.coreboot.org/21749 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979 Gerrit-Change-Number: 21749 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Fix pm_read16 argument size
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21748 Change subject: amd/stoneyridge: Fix pm_read16 argument size ...................................................................... amd/stoneyridge: Fix pm_read16 argument size Make pm_read16() consistent with the other PM register access functions. Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/21748/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index fdb0995..054b36a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -194,7 +194,7 @@ void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); u8 pm_read8(u8 reg); -u16 pm_read16(u16 reg); +u16 pm_read16(u8 reg); void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 1ca742f..655a15a 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -55,7 +55,7 @@ write16((void *)(PM_MMIO_BASE + reg), value); } -u16 pm_read16(u16 reg) +u16 pm_read16(u8 reg) { return read16((void *)(PM_MMIO_BASE + reg)); } -- To view, visit https://review.coreboot.org/21748 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95 Gerrit-Change-Number: 21748 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add PM defintions to southbridge.h
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21747 Change subject: amd/stoneyridge: Add PM defintions to southbridge.h ...................................................................... amd/stoneyridge: Add PM defintions to southbridge.h Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21747/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9f353fb..fdb0995 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -42,6 +42,9 @@ #define PM2_INDEX 0xcd0 #define PM2_DATA 0xcd1 +#define PM_PCI_CTRL 0x08 +#define FORCE_SLPSTATE_RETRY BIT(25) +#define FORCE_STPCLK_RETRY BIT(24) #define PM_ACPI_MMIO_EN 0x24 #define PM_SERIRQ_CONF 0x54 #define PM_EVT_BLK 0x60 @@ -51,6 +54,8 @@ #define PM_GPE0_BLK 0x68 #define PM_ACPI_SMI_CMD 0x6a #define PM_ACPI_CONF 0x74 +#define PM_RST_CTRL1 0xbe +#define SLPTYPE_CONTROL_EN BIT(5) #define PM_PMIO_DEBUG 0xd2 #define PM_MANUAL_RESET 0xd3 #define PM_HUD_SD_FLASH_CTRL 0xe7 -- To view, visit https://review.coreboot.org/21747 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0 Gerrit-Change-Number: 21747 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Refactor SMI handler
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21746 Change subject: amd/stoneyridge: Refactor SMI handler ...................................................................... amd/stoneyridge: Refactor SMI handler Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/smihandler.c 2 files changed, 56 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/21746/1 diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index c024c08..ed4a6c0 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -196,6 +196,11 @@ SMI_LVL_HIGH = 1, }; +struct smi_sources_t { + int type; + void (*handler)(void); +}; + static inline uint32_t smi_read32(uint8_t offset) { return read32((void *)(SMI_BASE + offset)); diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index cabfd3d..8551631 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -1,8 +1,17 @@ /* - * SMI handler for Hudson southbridges + * This file is part of the coreboot project. * + * Copyright (C) 2017 Advanced Micro Devices, Inc. * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> - * Subject to the GNU GPL v2, or (at your option) any later version. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include <console/console.h> @@ -37,6 +46,14 @@ return 0; } +/* + * Table of functions supported in the SMI handler. Note that SMI source setup + * in southbridge.c is unrelated to this list. + */ +struct smi_sources_t smi_sources[] = { + {SMITYPE_SMI_CMD_PORT, sb_apmc_smi_handler}, +}; + static void process_smi_sci(void) { const uint32_t status = smi_read32(SMI_SCI_STATUS); @@ -45,54 +62,38 @@ smi_write32(SMI_SCI_STATUS, status); } -static void process_gpe_smi(void) +static void *get_source_handler(int source) { - const uint32_t status = smi_read32(SMI_REG_SMISTS0); + int i; - /* Only Bits [23:0] indicate GEVENT SMIs. */ - if (status & GEVENT_MASK) { - /* A GEVENT SMI occurred */ - mainboard_smi_gpi(status & GEVENT_MASK); + for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) + if (smi_sources[i].type == source) + return smi_sources[i].handler; + + return NULL; +} + +static void process_smi_sources(uint32_t reg) +{ + const uint32_t status = smi_read32(reg); + int offset = 32 * (reg - SMI_REG_SMISTS0) / 4; + void (*source_handler)(void); + int i; + + for (i = 0 ; i < 32 ; i++) { + if (status & (1 << i)) { + source_handler = get_source_handler(i + offset); + if (source_handler) + source_handler(); + } } - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(SMI_REG_SMISTS0, status); -} + if (reg == SMI_REG_SMISTS0) + if (status & GEVENT_MASK) + mainboard_smi_gpi(status & GEVENT_MASK); -static void process_smi_0x84(void) -{ - const uint32_t status = smi_read32(SMI_REG_SMISTS1); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(SMI_REG_SMISTS1, status); -} - -static void process_smi_0x88(void) -{ - const uint32_t status = smi_read32(SMI_REG_SMISTS2); - - if (status & TYPE_TO_MASK(SMITYPE_SMI_CMD_PORT)) { - /* Command received via ACPI SMI command port */ - sb_apmc_smi_handler(); - } - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(SMI_REG_SMISTS2, status); -} - -static void process_smi_0x8c(void) -{ - const uint32_t status = smi_read32(SMI_REG_SMISTS3); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(SMI_REG_SMISTS4, status); -} - -static void process_smi_0x90(void) -{ - const uint32_t status = smi_read32(SMI_REG_SMISTS4); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(SMI_REG_SMISTS4, status); + /* Clear all events in this register */ + smi_write32(reg, status); } void southbridge_smi_handler(void) @@ -102,15 +103,15 @@ if (smi_src & SMI_STATUS_SRC_SCI) process_smi_sci(); if (smi_src & SMI_STATUS_SRC_0) - process_gpe_smi(); + process_smi_sources(SMI_REG_SMISTS0); if (smi_src & SMI_STATUS_SRC_1) - process_smi_0x84(); + process_smi_sources(SMI_REG_SMISTS1); if (smi_src & SMI_STATUS_SRC_2) - process_smi_0x88(); + process_smi_sources(SMI_REG_SMISTS2); if (smi_src & SMI_STATUS_SRC_3) - process_smi_0x8c(); + process_smi_sources(SMI_REG_SMISTS3); if (smi_src & SMI_STATUS_SRC_4) - process_smi_0x90(); + process_smi_sources(SMI_REG_SMISTS4); } void southbridge_smi_set_eos(void) -- To view, visit https://review.coreboot.org/21746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Gerrit-Change-Number: 21746 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Clean up smihandler.c
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21745 Change subject: amd/stoneyridge: Clean up smihandler.c ...................................................................... amd/stoneyridge: Clean up smihandler.c Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 22 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/21745/1 diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index c3c85e3..cabfd3d 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -11,18 +11,6 @@ #include <soc/smi.h> #include <soc/southbridge.h> - -#define SMI_0x88_ACPI_COMMAND (1 << 11) - -enum smi_source { - SMI_SOURCE_SCI = (1 << 0), - SMI_SOURCE_GPE = (1 << 1), - SMI_SOURCE_0x84 = (1 << 2), - SMI_SOURCE_0x88 = (1 << 3), - SMI_SOURCE_IRQ_TRAP = (1 << 4), - SMI_SOURCE_0x90 = (1 << 5) -}; - static void sb_apmc_smi_handler(void) { u32 reg32; @@ -51,78 +39,77 @@ static void process_smi_sci(void) { - const uint32_t status = smi_read32(0x10); + const uint32_t status = smi_read32(SMI_SCI_STATUS); /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x10, status); + smi_write32(SMI_SCI_STATUS, status); } static void process_gpe_smi(void) { - const uint32_t status = smi_read32(0x80); - const uint32_t gevent_mask = (1 << 24) - 1; + const uint32_t status = smi_read32(SMI_REG_SMISTS0); /* Only Bits [23:0] indicate GEVENT SMIs. */ - if (status & gevent_mask) { + if (status & GEVENT_MASK) { /* A GEVENT SMI occurred */ - mainboard_smi_gpi(status & gevent_mask); + mainboard_smi_gpi(status & GEVENT_MASK); } /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x80, status); + smi_write32(SMI_REG_SMISTS0, status); } static void process_smi_0x84(void) { - const uint32_t status = smi_read32(0x84); + const uint32_t status = smi_read32(SMI_REG_SMISTS1); /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x84, status); + smi_write32(SMI_REG_SMISTS1, status); } static void process_smi_0x88(void) { - const uint32_t status = smi_read32(0x88); + const uint32_t status = smi_read32(SMI_REG_SMISTS2); - if (status & SMI_0x88_ACPI_COMMAND) { + if (status & TYPE_TO_MASK(SMITYPE_SMI_CMD_PORT)) { /* Command received via ACPI SMI command port */ sb_apmc_smi_handler(); } /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x88, status); + smi_write32(SMI_REG_SMISTS2, status); } static void process_smi_0x8c(void) { - const uint32_t status = smi_read32(0x8c); + const uint32_t status = smi_read32(SMI_REG_SMISTS3); /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x8c, status); + smi_write32(SMI_REG_SMISTS4, status); } static void process_smi_0x90(void) { - const uint32_t status = smi_read32(0x90); + const uint32_t status = smi_read32(SMI_REG_SMISTS4); /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x90, status); + smi_write32(SMI_REG_SMISTS4, status); } void southbridge_smi_handler(void) { - const uint16_t smi_src = smi_read16(0x94); + const uint16_t smi_src = smi_read16(SMI_REG_POINTER); - if (smi_src & SMI_SOURCE_SCI) + if (smi_src & SMI_STATUS_SRC_SCI) process_smi_sci(); - if (smi_src & SMI_SOURCE_GPE) + if (smi_src & SMI_STATUS_SRC_0) process_gpe_smi(); - if (smi_src & SMI_SOURCE_0x84) + if (smi_src & SMI_STATUS_SRC_1) process_smi_0x84(); - if (smi_src & SMI_SOURCE_0x88) + if (smi_src & SMI_STATUS_SRC_2) process_smi_0x88(); - if (smi_src & SMI_SOURCE_IRQ_TRAP) + if (smi_src & SMI_STATUS_SRC_3) process_smi_0x8c(); - if (smi_src & SMI_SOURCE_0x90) + if (smi_src & SMI_STATUS_SRC_4) process_smi_0x90(); } -- To view, visit https://review.coreboot.org/21745 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Gerrit-Change-Number: 21745 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Check SMI command address before reading
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21744 Change subject: amd/stoneyridge: Check SMI command address before reading ...................................................................... amd/stoneyridge: Check SMI command address before reading Use the currently programmed address of the SMI pommand port before checking the passed command. This ensures we're reading the right port in case the port was relocated without our knowledge. Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/smi_util.c M src/soc/amd/stoneyridge/smihandler.c 3 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/21744/1 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 28b3244..9041c46 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -94,6 +94,7 @@ smm-y += smi_util.c smm-y += tsc_freq.c smm-y += uart.c +smm-y += southbridge.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 68e792c..833e6e3 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -6,6 +6,7 @@ */ #include <console/console.h> +#include <soc/southbridge.h> #include <soc/smi.h> static void configure_smi(uint8_t smi_num, uint8_t mode) @@ -73,3 +74,8 @@ { configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); } + +uint16_t pm_acpi_smi_cmd_port(void) +{ + return pm_read16(PM_ACPI_SMI_CMD); +} diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 45dada5..c3c85e3 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -5,7 +5,6 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ - #include <console/console.h> #include <cpu/x86/smm.h> #include <delay.h> @@ -27,7 +26,7 @@ static void sb_apmc_smi_handler(void) { u32 reg32; - const uint8_t cmd = inb(APM_CNT); + const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); switch (cmd) { case APM_CNT_ACPI_ENABLE: -- To view, visit https://review.coreboot.org/21744 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac Gerrit-Change-Number: 21744 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Clean up smi_util.c
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21743 Change subject: amd/stoneyridge: Clean up smi_util.c ...................................................................... amd/stoneyridge: Clean up smi_util.c Replace hardcoded values with defined ones. Change-Id: If963a817a4bea9b6dbb0d41a2bc0789a44a01391 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/smi_util.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/21743/1 diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 822738c..68e792c 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -8,15 +8,12 @@ #include <console/console.h> #include <soc/smi.h> -#define STONEYRIDGE_SMI_ACPI_COMMAND 75 - static void configure_smi(uint8_t smi_num, uint8_t mode) { uint8_t reg32_offset, bit_offset; uint32_t reg32; - /* SMI sources range from [0:149] */ - if (smi_num > 149) { + if (smi_num >= NUMBER_SMITYPES) { printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); return; } @@ -74,5 +71,5 @@ /** Enable SMIs on writes to ACPI SMI command port */ void enable_acpi_cmd_smi(void) { - configure_smi(STONEYRIDGE_SMI_ACPI_COMMAND, SMI_MODE_SMI); + configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); } -- To view, visit https://review.coreboot.org/21743 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If963a817a4bea9b6dbb0d41a2bc0789a44a01391 Gerrit-Change-Number: 21743 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add more SMM definitions
by Marshall Dawson (Code Review) 28 Sep '17

28 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21742 Change subject: amd/stoneyridge: Add more SMM definitions ...................................................................... amd/stoneyridge: Add more SMM definitions Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/smi.h 1 file changed, 174 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/21742/1 diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 46004c9..c024c08 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -1,8 +1,17 @@ /* - * Utilities for SMI handlers and SMM setup + * This file is part of the coreboot project. * + * Copyright (C) 2017 Advanced Micro Devices, Inc. * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> - * Subject to the GNU GPL v2, or (at your option) any later version. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ @@ -10,17 +19,170 @@ #include <arch/io.h> -/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. - * This is defined by AGESA, but we dpn't include AGESA headers to avoid - * polluting the namesace. - */ -#define SMI_BASE 0xfed80200 +/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. */ +#define SMI_BASE 0xfed80200 -#define SMI_REG_SMITRIG0 0x98 -#define SMITRG0_EOS (1 << 28) -#define SMITRG0_SMIENB (1 << 31) +#define SMI_SCI_STATUS 0x10 -#define SMI_REG_CONTROL0 0xa0 +/* SMI source and status */ +#define SMITYPE_AGPIO65 0 +#define SMITYPE_AGPIO66 1 +#define SMITYPE_AGPIO3 2 +#define SMITYPE_LPCPME_AGPIO22 3 +#define SMITYPE_GPIO4 4 +#define SMITYPE_LPCPD_AGPIOG21 5 +#define SMITYPE_IRTX1_G15 6 +#define SMITYPE_AGPIO5_DEVSLP0 7 +#define SMITYPE_WAKE_AGPIO2 8 +#define SMITYPE_APIO68_SGPIOCLK 9 +#define SMITYPE_AGPIO6 10 +#define SMITYPE_GPIO7 11 +#define SMITYPE_USBOC0_TRST_AGPIO16 12 +#define SMITYPE_USB0C1_TDI_AGPIO17 13 +#define SMITYPE_USBOC2_TCK_AGPIO18 14 +#define SMITYPE_TDO_USB0C3_AGPIO24 15 +#define SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23 16 +/* 17 Reserved */ +#define SMITYPE_BLINK_AGPIO11_USBOC7 18 +#define SMITYPE_SYSRESET_AGPIO1 19 +#define SMITYPE_IRRX1_AGPIO15 20 +#define SMITYPE_IRTX0_USBOC5_AGPIO13 21 +#define SMITYPE_GPIO9_SERPORTRX 22 +#define SMITYPE_GPIO8_SEPORTTX 23 +#define GEVENT_MASK ((1 << SMITYPE_AGPIO65) \ + | (1 << SMITYPE_AGPIO66) \ + | (1 << SMITYPE_AGPIO3) \ + | (1 << SMITYPE_LPCPME_AGPIO22) \ + | (1 << SMITYPE_GPIO4) \ + | (1 << SMITYPE_LPCPD_AGPIOG21) \ + | (1 << SMITYPE_IRTX1_G15) \ + | (1 << SMITYPE_AGPIO5_DEVSLP0) \ + | (1 << SMITYPE_WAKE_AGPIO2) \ + | (1 << SMITYPE_APIO68_SGPIOCLK) \ + | (1 << SMITYPE_AGPIO6) \ + | (1 << SMITYPE_GPIO7) \ + | (1 << SMITYPE_USBOC0_TRST_AGPIO16) \ + | (1 << SMITYPE_USB0C1_TDI_AGPIO17) \ + | (1 << SMITYPE_USBOC2_TCK_AGPIO18) \ + | (1 << SMITYPE_TDO_USB0C3_AGPIO24) \ + | (1 << SMITYPE_ACPRES_USBOC4_IRRX0_AGPIO23) \ + | (1 << SMITYPE_BLINK_AGPIO11_USBOC7) \ + | (1 << SMITYPE_SYSRESET_AGPIO1) \ + | (1 << SMITYPE_IRRX1_AGPIO15) \ + | (1 << SMITYPE_IRTX0_USBOC5_AGPIO13) \ + | (1 << SMITYPE_GPIO9_SERPORTRX)) +#define SMITYPE_EHCI0_WAKE 24 +#define SMITYPE_EHCI1_WAKE 25 +#define SMITYPE_ESPI_SYS 26 +#define SMITYPE_ESPI_WAKE_PME 27 +/* 28-32 Reserved */ +#define SMITYPE_FCH_FAKE0 33 +#define SMITYPE_FCH_FAKE1 34 +#define SMITYPE_FCH_FAKE2 35 +/* 36 Reserved */ +#define SMITYPE_SATA_GEVENT0 37 +#define SMITYPE_SATA_GEVENT1 38 +#define SMITYPE_ACP_WAKE 39 +#define SMITYPE_ECG 40 +#define SMITYPE_GPIO_CTL 41 +#define SMITYPE_CIR_PME 42 +#define SMITYPE_ALT_HPET_ALARM 43 +#define SMITYPE_FAN_THERMAL 44 +#define SMITYPE_ASF_MASTER_SLAVE 45 +#define SMITYPE_I2S_WAKE 46 +#define SMITYPE_SMBUS0_MASTER 47 +#define SMITYPE_TWARN 48 +#define SMITYPE_TRAFFIC_MON 49 +#define SMITYPE_ILLB 50 +#define SMITYPE_PWRBUTTON_UP 51 +#define SMITYPE_PROCHOT 52 +#define SMITYPE_APU_HW 53 +#define SMITYPE_NB_SCI 54 +#define SMITYPE_RAS_SERR 55 +#define SMITYPE_XHC0_PME 56 +/* 57 Reserved */ +#define SMITYPE_ACDC_TIMER 58 +/* 59-62 Reserved */ +#define SMITYPE_TEMP_TSI 63 +#define SMITYPE_KB_RESET 64 +#define SMITYPE_SLP_TYP 65 +#define SMITYPE_AL2H_ACPI 66 +#define SMITYPE_AHCI 67 +/* 68-71 Reserved */ +#define SMITYPE_GBL_RLS 72 +#define SMITYPE_BIOS_RLS 73 +#define SMITYPE_PWRBUTTON_DOWN 74 +#define SMITYPE_SMI_CMD_PORT 75 +#define SMITYPE_USB_SMI 76 +#define SMITYPE_SERIRQ 77 +#define SMITYPE_SMBUS0_INTR 78 +#define SMITYPE_IMC 79 +#define SMITYPE_XHC_ERROR 80 +#define SMITYPE_INTRUDER 81 +#define SMITYPE_VBAT_LOW 82 +#define SMITYPE_PROTHOT 83 +#define SMITYPE_PCI_SERR 84 +#define SMITYPE_GPP_SERR 85 +/* 85-88 Reserved */ +#define SMITYPE_TMERTRIP 89 +#define SMITYPE_EMUL60_64 90 +#define SMITYPE_USB_FLR 91 +#define SMITYPE_SATA_FLR 92 +#define SMITYPE_AZ_FLR 93 +/* 94-132 Reserved */ +#define SMITYPE_FANIN0 133 +/* 134-137 Reserved */ +#define SMITYPE_FAKE0 138 +#define SMITYPE_FAKE1 139 +#define SMITYPE_FAKE2 140 +/* 141 Reserved */ +#define SMITYPE_SHORT_TIMER 142 +#define SMITYPE_LONG_TIMER 143 +#define SMITYPE_AB_SMI 144 +#define SMITYPE_SOFT_RESET 145 +/* 146-147 Reserved */ +#define SMITYPE_IOTRAP0 148 +/* 149-151 Reserved */ +#define SMITYPE_MEMTRAP0 152 +/* 153-155 Reserved */ +#define SMITYPE_CFGTRAP0 156 +/* 157-159 Reserved */ +#define NUMBER_SMITYPES 160 +#define TYPE_TO_MASK(X) (1 << (X) % 32) + +#define SMI_REG_SMISTS0 0x80 +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +# define SMI_STATUS_SRC_SCI (1 << 0) +# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */ +# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */ +# define SMI_STATUS_SRC_2 (1 << 3) +# define SMI_STATUS_SRC_3 (1 << 4) +# define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_TIMER 0x96 +#define SMI_TIMER_MASK 0x7fff +#define SMI_TIMER_EN (1 << 15) + +#define SMI_REG_SMITRIG0 0x98 +# define SMITRG0_EOS (1 << 28) +# define SMI_TIMER_SEL (1 << 29) +# define SMITRG0_SMIENB (1 << 31) + +#define SMI_REG_CONTROL0 0xa0 +#define SMI_REG_CONTROL1 0xa4 +#define SMI_REG_CONTROL2 0xa8 +#define SMI_REG_CONTROL3 0xac +#define SMI_REG_CONTROL4 0xb0 +#define SMI_REG_CONTROL5 0xb4 +#define SMI_REG_CONTROL6 0xb8 +#define SMI_REG_CONTROL7 0xbc +#define SMI_REG_CONTROL8 0xc0 +#define SMI_REG_CONTROL9 0xc4 enum smi_mode { SMI_MODE_DISABLE = 0, @@ -54,6 +216,7 @@ write16((void *)(SMI_BASE + offset), value); } +uint16_t pm_acpi_smi_cmd_port(void); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void disable_gevent_smi(uint8_t gevent); void enable_acpi_cmd_smi(void); -- To view, visit https://review.coreboot.org/21742 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340 Gerrit-Change-Number: 21742 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit September 2017