coreboot-gerrit

coreboot-gerrit@coreboot.org
  • 1 participants
  • 1960 discussions
Change in coreboot[master]: mainboard/google/fizz: Enable Devslp for SATA port 1
by Kane Chen (Code Review)
2 years, 2 months
Change in coreboot[master]: arch/x86: Enable CQOS on Geminilake
by build bot (Jenkins) (Code Review)
2 years, 2 months
Change in coreboot[master]: soc/intel/skylake: Add support in SKL for PMC common code
by build bot (Jenkins) (Code Review)
2 years, 2 months
Change in coreboot[master]: mainboard/google/fizz: Enable Devslp for SATA port 1
by build bot (Jenkins) (Code Review)
2 years, 2 months
Change in coreboot[master]: mainboard/google/fizz: Enable Devslp for SATA port 1
by Gaggery Tsai (Code Review)
2 years, 2 months
Change in coreboot[master]: soc/amd/stoneyridge: Wait for UART to be ready
by build bot (Jenkins) (Code Review)
2 years, 2 months
Change in coreboot[master]: arch/riscv: Return from trap_handler instead of jumping out
by build bot (Jenkins) (Code Review)
2 years, 2 months
Change in coreboot[master]: arch/riscv: Drop mret workaround
by build bot (Jenkins) (Code Review)
2 years, 2 months
Change in coreboot[master]: arch/riscv: Unify trap return
by build bot (Jenkins) (Code Review)
2 years, 2 months
Change in coreboot[master]: soc/amd/stoneyridge: Wait for UART to be ready
by build bot (Jenkins) (Code Review)
2 years, 2 months
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