Change in coreboot[master]: mainboard/google/fizz: Enable Devslp for SATA port 1
Kane Chen has posted comments on this change. ( https://review.coreboot.org/21765 ) Change subject: mainboard/google/fizz: Enable Devslp for SATA port 1 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/21765/1/src/mainboard/google/fizz/gpio.h File src/mainboard/google/fizz/gpio.h: https://review.coreboot.org/#/c/21765/1/src/mainboard/google/fizz/gpio.h@170 PS1, Line 170: * SATA_DEVSLP0 */ PAD_CFG_GPI(GPP is this pin floating ? If so, it's better to set NC pin. thank you -- To view, visit https://review.coreboot.org/21765 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3 Gerrit-Change-Number: 21765 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai@intel.com> Gerrit-Reviewer: Kane Chen <kane.chen@intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki@intel.com> Gerrit-Reviewer: Shelley Chen <shchen@google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 08:50:57 +0000 Gerrit-HasComments: Yes
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Kane Chen (Code Review)