coreboot-gerrit September 2017

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Change in coreboot[master]: mainboard/google/fizz: Tune i2c parameters
by Shelley Chen (Code Review) 29 Sep '17

29 Sep '17

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/21773 Change subject: mainboard/google/fizz: Tune i2c parameters ...................................................................... mainboard/google/fizz: Tune i2c parameters Tune I2C params for I2C buses 1 and 5 to ensure that the frequency does not exceed 400KHz. BUG=b:65058277 BRANCH=None TEST=Measured bus frequency for audio and cr50 <= 400MHz Change-Id: Ia82d47916958e4c199b80a845977b79c4057ac81 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 19 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21773/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 3989ec4..3590d6e 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -220,7 +220,25 @@ # Configure I2C1 for cr50 TPM. Early init is required to set up a BAR # for TPM communication before memory is up. register "i2c[1]" = "{ - .early_init = 1, + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 156, + .scl_hcnt = 139, + .sda_hold = 36, + }, + .early_init = 1, + }" + + # audio + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 156, + .scl_hcnt = 139, + .sda_hold = 36, + }, }" # Must leave UART0 enabled or SD/eMMC will not work as PCI -- To view, visit https://review.coreboot.org/21773 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia82d47916958e4c199b80a845977b79c4057ac81 Gerrit-Change-Number: 21773 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: google/fizz: Set PL2 value based on sku id/charge max power
by Shelley Chen (Code Review) 29 Sep '17

29 Sep '17

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/21772 Change subject: google/fizz: Set PL2 value based on sku id/charge max power ...................................................................... google/fizz: Set PL2 value based on sku id/charge max power Set PL2 based on either 90% of usb c charger's max power or sku id if using a barrel jack. BUG=b:37473486 BRANCH=None TEST=output debug info for different skus and make sure PL2 set correctly. Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/mainboard.c 1 file changed, 20 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21772/1 diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 76fb2b8..1ced07e 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -18,7 +18,9 @@ #include <chip.h> #include <device/device.h> #include <ec/ec.h> -#include <intelblocks/mp_init.h> +#include <ec/google/chromeec/ec.h> +#include <gpio.h> +#include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -29,23 +31,29 @@ /* * mainboard_get_pl2 * - * @return value Pl2 should be set to based on cpu id + * @return value Pl2 should be set to * - * TODO: This is purely based on cpu id, which only works for the - * current build because we have a different cpu id per sku. However, - * on the next build, we'll have distinct board ids per sku. We'll - * need to modify that at this point. + * Check if charger is USB C. If so, set to 90% of the max value. + * Otherwise, set PL2 based on sku id. */ static u32 mainboard_get_pl2(void) { - struct cpuid_result cpuidr; + u32 watts = 0.9 * google_chromeec_get_usb_pd_power_info(); + int sku_id; - cpuidr = cpuid(1); - if (cpuidr.eax == CPUID_KABYLAKE_Y0) { - /* i7 needs higher pl2 */ - return 44; + if (watts == 0) { + /* using the barrel jack, get PL2 based on sku id */ + watts = 29; + sku_id = gpio_get(GPP_C15) << 3 | + gpio_get(GPP_C14) << 2 | + gpio_get(GPP_C13) << 1 | + gpio_get(GPP_C12); + if (sku_id == 0x4) { + /* u42 i7 needs higher pl2. Everything else is 29 */ + watts = 44; + } } - return 29; + return watts; } static void mainboard_init(device_t dev) -- To view, visit https://review.coreboot.org/21772 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3 Gerrit-Change-Number: 21772 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: chromeec: Add function to retrieve usb c charger info
by Shelley Chen (Code Review) 29 Sep '17

29 Sep '17

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/21771 Change subject: chromeec: Add function to retrieve usb c charger info ...................................................................... chromeec: Add function to retrieve usb c charger info Add google_chromeec_get_usb_pd_power_info(), which will call the EC_CMD_USB_PD_CONTROL host command to retrieve the current and voltage info of the usb c charger. Returns power info in watts. BUG=b:37473486 BRANCH=None TEST=output debug info to make sure that correct power is returned. Change-Id: Ie14a0a6163e1c2699cb20b4422c8062164d92076 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21771/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 03d4c3b..47bd5a3 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -622,6 +622,36 @@ return google_chromeec_command(&cmd); } +/* Get charger power info in Watts */ +int google_chromeec_get_usb_pd_power_info(void) +{ + struct ec_params_usb_pd_power_info req = { + .port = PD_POWER_CHARGING_PORT, + }; + struct ec_response_usb_pd_power_info rsp; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_USB_PD_POWER_INFO, + .cmd_version = 0, + .cmd_data_in = &req, + .cmd_size_in = sizeof(req), + .cmd_data_out = &rsp, + .cmd_size_out = sizeof(rsp), + .cmd_dev_index = 0, + }; + struct usb_chg_measures m; + + google_chromeec_command(&cmd); + + m = rsp.meas; + + if (rsp.type == USB_CHG_TYPE_PD) { + /* values are given in milliAmps and milliVolts */ + return (m.current_max * m.voltage_max)/1000000; + } + /* If barrel jack, then just return 0 */ + return 0; +} + int google_chromeec_set_usb_pd_role(u8 port, enum usb_pd_control_role role) { struct ec_params_usb_pd_control req = { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 3a7cadd..47760fb 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -89,6 +89,7 @@ }; int google_chromeec_set_usb_charge_mode(u8 port_id, enum usb_charge_mode mode); int google_chromeec_set_usb_pd_role(u8 port, enum usb_pd_control_role role); +int google_chromeec_get_usb_pd_power_info(void); /* internal structure to send a command to the EC and wait for response. */ struct chromeec_command { -- To view, visit https://review.coreboot.org/21771 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie14a0a6163e1c2699cb20b4422c8062164d92076 Gerrit-Change-Number: 21771 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: drivers/elog: Fix debug build errors
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21769 ) Change subject: drivers/elog: Fix debug build errors ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61366/ : SUCCESS -- To view, visit https://review.coreboot.org/21769 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda Gerrit-Change-Number: 21769 Gerrit-PatchSet: 2 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 19:35:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Remove preprocessor #IF
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21770 ) Change subject: soc/amd/stoneyridge/southbridge.c: Remove preprocessor #IF ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61365/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16507/ : SUCCESS -- To view, visit https://review.coreboot.org/21770 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4 Gerrit-Change-Number: 21770 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 18:58:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Remove preprocessor #IF
by Richard Spiegel (Code Review) 29 Sep '17

29 Sep '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/21770 Change subject: soc/amd/stoneyridge/southbridge.c: Remove preprocessor #IF ...................................................................... soc/amd/stoneyridge/southbridge.c: Remove preprocessor #IF Replace #if and #endif with runtime <if (condition) {> and <}> Code Files: southbridge.c BUG=b:62200891 Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 5 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21770/1 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 5e36100..676f971 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -28,9 +28,7 @@ #include <soc/southbridge.h> #include <soc/smbus.h> #include <soc/smi.h> -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) #include <fchec.h> -#endif int acpi_get_sleep_type(void) @@ -98,12 +96,11 @@ void southbridge_final(void *chip_info) { -#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) - agesawrapper_fchecfancontrolservice(); -#if !IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE) - enable_imc_thermal_zone(); -#endif -#endif + if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM)) { + agesawrapper_fchecfancontrolservice(); + if (!IS_ENABLED(CONFIG_ACPI_ENABLE_THERMAL_ZONE)) + enable_imc_thermal_zone(); + } } /* -- To view, visit https://review.coreboot.org/21770 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4 Gerrit-Change-Number: 21770 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: nb/intel/*/gma: Port ACPI opregion to older platforms
by Arthur Heymans (Code Review) 29 Sep '17

29 Sep '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21766 ) Change subject: nb/intel/*/gma: Port ACPI opregion to older platforms ...................................................................... Patch Set 1: Code-Review+2 Tested successfully on DG43GT (x4x) with vbt.bin, with X200 (gm45) with vendor option rom and D45GCLF (i945) with fake vbt. -- To view, visit https://review.coreboot.org/21766 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa Gerrit-Change-Number: 21766 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 18:35:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/elog: Fix to allow debug to work
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21769 ) Change subject: drivers/elog: Fix to allow debug to work ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61364/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16506/ : SUCCESS -- To view, visit https://review.coreboot.org/21769 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda Gerrit-Change-Number: 21769 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 17:43:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/*/gma: Port ACPI opregion to older platforms
by Arthur Heymans (Code Review) 29 Sep '17

29 Sep '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21766 ) Change subject: nb/intel/*/gma: Port ACPI opregion to older platforms ...................................................................... Patch Set 1: I can test those platforms. Maybe add pineview to the mix? (I can't test that one, so better have a separate patch for that) -- To view, visit https://review.coreboot.org/21766 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa Gerrit-Change-Number: 21766 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 17:31:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: WIP soc/amd/stoneyridge: Add ELOG to SMM
by build bot (Jenkins) (Code Review) 29 Sep '17

29 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21728 ) Change subject: WIP soc/amd/stoneyridge: Add ELOG to SMM ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61361/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16503/ : SUCCESS -- To view, visit https://review.coreboot.org/21728 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I458babe1694f042215dd0e1c3277856e340de86f Gerrit-Change-Number: 21728 Gerrit-PatchSet: 3 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 29 Sep 2017 17:31:04 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017