coreboot-gerrit September 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: amd/stoneyridge: Enable SMM in TSEG
by build bot (Jenkins) (Code Review) 21 Sep '17

21 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21501 ) Change subject: amd/stoneyridge: Enable SMM in TSEG ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60829/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16015/ : SUCCESS -- To view, visit https://review.coreboot.org/21501 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Gerrit-Change-Number: 21501 Gerrit-PatchSet: 7 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Sep 2017 00:52:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Put AGESA heap into cbmem
by build bot (Jenkins) (Code Review) 21 Sep '17

21 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21594 ) Change subject: amd/stoneyridge: Put AGESA heap into cbmem ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60831/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16017/ : SUCCESS -- To view, visit https://review.coreboot.org/21594 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848 Gerrit-Change-Number: 21594 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Sep 2017 00:49:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Clean up include files in northbridge.h
by Marshall Dawson (Code Review) 21 Sep '17

21 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21615 Change subject: amd/stoneyridge: Clean up include files in northbridge.h ...................................................................... amd/stoneyridge: Clean up include files in northbridge.h Add an extra include file to northbridge.c for completeness. cpu/msr.h is already included in cpu/amd/mtrr.h which allows the file to build properly. Remove include files that are no longer required for the file. Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 1 insertion(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/21615/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index ae2cdbb..07ea10f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -23,11 +23,10 @@ #include <cpu/amd/amdfam15.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> -#include <lib.h> #include <agesawrapper.h> #include <agesawrapper_call.h> #include <soc/northbridge.h> @@ -35,17 +34,6 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> - -/* - * AMD vendorcode files. Place at the end so coreboot defaults and maintained - * and not set by vendorcode - */ -#include <AGESA.h> -#include <cpuRegisters.h> -#include <FieldAccessors.h> -#include <Options.h> -#include <Porting.h> -#include <Topology.h> typedef struct dram_base_mask { u32 base; /* [47:27] at [28:8] */ -- To view, visit https://review.coreboot.org/21615 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d Gerrit-Change-Number: 21615 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: enable SATA
by build bot (Jenkins) (Code Review) 21 Sep '17

21 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21407 ) Change subject: mainboard/intel/cannonlake_rvp: enable SATA ...................................................................... Patch Set 4: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/60828/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16014/ : SUCCESS -- To view, visit https://review.coreboot.org/21407 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie4723b37f0a2028d22f0a344e45a1ded51deecd0 Gerrit-Change-Number: 21407 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 21 Sep 2017 00:17:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: enable SATA
by Bora Guvendik (Code Review) 21 Sep '17

21 Sep '17

Hello Pratikkumar V Prajapati, Abhay Kumar, Subrata Banik, John Zhao, Hannah Williams, Lijian Zhao, Shaunak Saha, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21407 to look at the new patch set (#4). Change subject: mainboard/intel/cannonlake_rvp: enable SATA ...................................................................... mainboard/intel/cannonlake_rvp: enable SATA Set sata enable FSP parameters. Change-Id: Ie4723b37f0a2028d22f0a344e45a1ded51deecd0 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/21407/4 -- To view, visit https://review.coreboot.org/21407 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie4723b37f0a2028d22f0a344e45a1ded51deecd0 Gerrit-Change-Number: 21407 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: google/kahlee: Fix GPIO ASL
by build bot (Jenkins) (Code Review) 20 Sep '17

20 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21614 ) Change subject: google/kahlee: Fix GPIO ASL ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60827/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16013/ : SUCCESS -- To view, visit https://review.coreboot.org/21614 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Gerrit-Change-Number: 21614 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Sep 2017 23:36:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Fix GPIO ASL
by Marc Jones (Code Review) 20 Sep '17

20 Sep '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/21614 Change subject: google/kahlee: Fix GPIO ASL ...................................................................... google/kahlee: Fix GPIO ASL Use a single define and set the CROS GPIO ASL device to match the StoneyRidge GPIO HID. Pass the GPIO number and not the memory mapped address of the GPIO. Also, add a DDN field in the GPIO ASL. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/mainboard/google/kahlee/acpi/carrizo_fch.asl M src/mainboard/google/kahlee/chromeos.c M src/soc/amd/stoneyridge/include/soc/gpio.h 3 files changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21614/1 diff --git a/src/mainboard/google/kahlee/acpi/carrizo_fch.asl b/src/mainboard/google/kahlee/acpi/carrizo_fch.asl index 04f563e..9bf7dec 100644 --- a/src/mainboard/google/kahlee/acpi/carrizo_fch.asl +++ b/src/mainboard/google/kahlee/acpi/carrizo_fch.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <soc/gpio.h> + Device (AAHB) { Name (_HID, "AAHB0000") @@ -30,9 +32,10 @@ Device (GPIO) { - Name (_HID, "AMD0030") - Name (_CID, "AMD0030") - Name(_UID, 0) + Name (_HID, GPIO_DEVICE_NAME) + Name (_CID, GPIO_DEVICE_NAME) + Name (_UID, 0) + Name (_DDN, GPIO_DEVICE_DESC) Name (_CRS, ResourceTemplate() { diff --git a/src/mainboard/google/kahlee/chromeos.c b/src/mainboard/google/kahlee/chromeos.c index 156614b..ef471be 100644 --- a/src/mainboard/google/kahlee/chromeos.c +++ b/src/mainboard/google/kahlee/chromeos.c @@ -21,7 +21,8 @@ #include <gpio.h> /* SPI Write protect */ -#define CROS_WP_GPIO GPIO_122 +#define CROS_WP_GPIO GPIO_122 +#define CROS_WP_GPIO_NUMBER 122 void fill_lb_gpios(struct lb_gpios *gpios) { @@ -40,8 +41,8 @@ } static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_WP_GPIO_NUMBER, GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index c5b7c8a..5aa6248 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -16,10 +16,12 @@ #ifndef __STONEYRIDGE_GPIO_H__ #define __STONEYRIDGE_GPIO_H__ +#define GPIO_DEVICE_NAME "AMD0030" +#define GPIO_DEVICE_DESC "GPIO Controller" + +#ifndef __ACPI__ #include <soc/amd/common/amd_defs.h> #include <types.h> - -#define CROS_GPIO_DEVICE_NAME "AmdKern" #define GPIO_PIN_STS (1 << 16) #define GPIO_PULLUP_ENABLE (1 << 20) @@ -128,5 +130,5 @@ #define GPIO_148 (GPIO_BANK2_CONTROL + 0x50) typedef uint32_t gpio_t; - +#endif /* __ACPI__ */ #endif /* __STONEYRIDGE_GPIO_H__ */ -- To view, visit https://review.coreboot.org/21614 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Gerrit-Change-Number: 21614 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: vboot: use cbfstool truncate
by Julius Werner (Code Review) 20 Sep '17

20 Sep '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/21609 ) Change subject: vboot: use cbfstool truncate ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/21609 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I33b7e1c483a69e66e82541c09582be2a71356a10 Gerrit-Change-Number: 21609 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Sep 2017 23:06:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/cbfstool: Add "truncate" command
by Julius Werner (Code Review) 20 Sep '17

20 Sep '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/21608 ) Change subject: util/cbfstool: Add "truncate" command ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/21608/1/util/cbfstool/cbfs_image.c File util/cbfstool/cbfs_image.c: https://review.coreboot.org/#/c/21608/1/util/cbfstool/cbfs_image.c@507 PS1, Line 507: * empty, we still want to keep it or we remove the entire filesystem. I'd say this (removing the entire filesystem) would be the more natural thing to do here. It might make sense in edge cases, e.g. imagine a situation where you have an extra CBFS FMAP section somewhere that may optionally contain something (we actually have that with RW_LEGACY already, although it's not verified). If the build system decides (from config options or whatever) not to add any files, you would still want it truncated so that it doesn't waste bytes on verification. https://review.coreboot.org/#/c/21608/1/util/cbfstool/cbfs_image.c@509 PS1, Line 509: * If that file is empty, remove it and report its header's offset as nit: Put this comment in front of the next if() so it's clear which comment belongs to what code section. https://review.coreboot.org/#/c/21608/1/util/cbfstool/cbfs_image.c@519 PS1, Line 519: /* nothing to truncate */ In both of the return 1 cases, should size be adjusted to the actual end of the CBFS? It might be different from buffer_size if the CBFS had already been truncated previously. -- To view, visit https://review.coreboot.org/21608 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0c747090813898539f3428936afa9d8459adee9c Gerrit-Change-Number: 21608 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Sep 2017 22:40:55 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Enable common LPC IP
by build bot (Jenkins) (Code Review) 20 Sep '17

20 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20120 ) Change subject: soc/intel/skylake: Enable common LPC IP ...................................................................... Patch Set 14: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60826/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16012/ : SUCCESS -- To view, visit https://review.coreboot.org/20120 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042e459fb7c07f024a7f6a5fe7da13eb5f0dd688 Gerrit-Change-Number: 20120 Gerrit-PatchSet: 14 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Sep 2017 21:12:58 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017