Tim Chen has uploaded this change for review. ( https://review.coreboot.org/21625
Change subject: google/coral: Set SKU ID to EC
......................................................................
google/coral: Set SKU ID to EC
Set AP SKU ID by ec command EC_CMD_SET_SKU_ID to update EC keyboard backlight
flag.
BUG=b:64705535
BRANCH=master
TEST=build and test on coral/bruce dut
Change-Id: Id427c9d714969d23f96e6be992f3344ade82b43e
Signed-off-by: Tim Chen <Tim-Chen(a)quantatw.com>
---
M src/mainboard/google/reef/variants/coral/mainboard.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/21625/1
diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c
index c60c083..fd8f33b 100644
--- a/src/mainboard/google/reef/variants/coral/mainboard.c
+++ b/src/mainboard/google/reef/variants/coral/mainboard.c
@@ -39,6 +39,11 @@
*oem_revision = variant_board_sku();
}
+void variant_board_ec_set_skuid(void)
+{
+ google_chromeec_set_sku_id(variant_board_sku());
+}
+
void mainboard_devtree_update(struct device *dev)
{
/* Override dev tree settings per board */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id427c9d714969d23f96e6be992f3344ade82b43e
Gerrit-Change-Number: 21625
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com>
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21621
Change subject: nb/i945/raminit: Don't fall back to smbus read on failed SPD decode
......................................................................
nb/i945/raminit: Don't fall back to smbus read on failed SPD decode
SPD decoding problems are no longer a good method for detecting if i2c
byte read failed, since the return value of i2c_block_read is checked.
Change-Id: I230aa22964c452cf28a9370c927b82c57e39cc62
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 8 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/21621/1
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index a9d183c..b7d2108 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -387,8 +387,7 @@
printk(BIOS_DEBUG, "Reading SPD using i2c block operation.\n");
if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) && bytes_read > 0)
hexdump(raw_spd, bytes_read);
- if (bytes_read != 64 || spd_decode_ddr2(&dimm_info, raw_spd)
- != SPD_STATUS_OK) {
+ if (bytes_read != 64) {
/* Try again with SMBUS byte read */
printk(BIOS_DEBUG, "i2c block operation failed,"
"trying smbus byte operation.\n");
@@ -396,10 +395,14 @@
raw_spd[j] = spd_read_byte(device, j);
if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
hexdump(raw_spd, 64);
- if (spd_decode_ddr2(&dimm_info, raw_spd)
- != SPD_STATUS_OK)
- continue;
}
+
+ if (spd_decode_ddr2(&dimm_info, raw_spd) != SPD_STATUS_OK) {
+ printk(BIOS_WARNING, "Encountered problems with SPD, "
+ "skipping this dimm.\n");
+ continue;
+ }
+
if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP))
dram_print_spd_ddr2(&dimm_info);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I230aa22964c452cf28a9370c927b82c57e39cc62
Gerrit-Change-Number: 21621
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21620
Change subject: device/dram/ddr2.c: Be more lax about bit7 for tRR byte in SPD
......................................................................
device/dram/ddr2.c: Be more lax about bit7 for tRR byte in SPD
At least one dimm was found to have an SPD with valid checksum (so
otherwise sane) but without bit7 set.
Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/device/dram/ddr2.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/21620/1
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index 6f43563..0a6574f 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -188,6 +188,12 @@
*/
static int spd_decode_tRR_time(u32 *tRR, u8 c)
{
+ if (!(c & (1 << 7))) {
+ printk(BIOS_DEBUG, "SPD byte12 (tRR) bit7 not set,"
+ " ignoring...");
+ c |= (1 << 7);
+ }
+
switch (c) {
default:
printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I091121a5d08159cea4befdedb5f3a92ce132c6e5
Gerrit-Change-Number: 21620
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>