coreboot-gerrit September 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Use common/block/gpio
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19201 ) Change subject: soc/intel/skylake: Use common/block/gpio ...................................................................... Patch Set 44: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61019/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16195/ : SUCCESS -- To view, visit https://review.coreboot.org/19201 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099 Gerrit-Change-Number: 19201 Gerrit-PatchSet: 44 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sowmya v <sowmyav235(a)gmail.com> Gerrit-Comment-Date: Mon, 25 Sep 2017 05:44:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add support in SKL for PMC common code
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20499 ) Change subject: soc/intel/skylake: Add support in SKL for PMC common code ...................................................................... Patch Set 12: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61018/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16194/ : SUCCESS -- To view, visit https://review.coreboot.org/20499 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Gerrit-Change-Number: 20499 Gerrit-PatchSet: 12 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 05:42:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection
by Arthur Heymans (Code Review) 25 Sep '17

25 Sep '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21587 ) Change subject: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/21587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c Gerrit-Change-Number: 21587 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 05:25:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] asus/p2b-ls: Add ACPI tables
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21672 ) Change subject: [WIP] asus/p2b-ls: Add ACPI tables ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61017/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16193/ : SUCCESS -- To view, visit https://review.coreboot.org/21672 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87 Gerrit-Change-Number: 21672 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 04:02:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] sb/intel/i82371eb: Rework ACPI DSDT table
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21671 ) Change subject: [WIP] sb/intel/i82371eb: Rework ACPI DSDT table ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61016/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16192/ : SUCCESS -- To view, visit https://review.coreboot.org/21671 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Gerrit-Change-Number: 21671 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 04:01:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] winbond/w83977tf: Add ACPI DSDT table
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21670 ) Change subject: [WIP] winbond/w83977tf: Add ACPI DSDT table ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61015/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16191/ : SUCCESS -- To view, visit https://review.coreboot.org/21670 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If113807901619bc0f4250607546be415f9e5e45b Gerrit-Change-Number: 21670 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 03:59:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82371eb: Consolidate bootblock.c logic
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21468 ) Change subject: sb/intel/i82371eb: Consolidate bootblock.c logic ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61014/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16190/ : SUCCESS -- To view, visit https://review.coreboot.org/21468 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01 Gerrit-Change-Number: 21468 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 03:58:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soraka: Update I2C5 bus tuning parameters
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21669 ) Change subject: soraka: Update I2C5 bus tuning parameters ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61013/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16189/ : SUCCESS -- To view, visit https://review.coreboot.org/21669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517 Gerrit-Change-Number: 21669 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 03:56:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] asus/p2b-ls: Add ACPI tables
by Keith Hui (Code Review) 25 Sep '17

25 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21672 Change subject: [WIP] asus/p2b-ls: Add ACPI tables ...................................................................... [WIP] asus/p2b-ls: Add ACPI tables Add ACPI tables support that will be needed for soft-off and S3 resume. Right now only have DSDT and what was done for asus/p2b. This has not yet been boot tested and so is not for merging yet. All feedbacks appreciated. Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b-ls/Kconfig A src/mainboard/asus/p2b-ls/acpi_tables.c A src/mainboard/asus/p2b-ls/dsdt.asl 3 files changed, 208 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21672/1 diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig index 967ebd9..2bb9369 100644 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ b/src/mainboard/asus/p2b-ls/Kconfig @@ -23,6 +23,7 @@ select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 select SDRAMPWR_4DIMM + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c new file mode 100644 index 0000000..d740ee1 --- /dev/null +++ b/src/mainboard/asus/p2b-ls/acpi_tables.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* mainboard has no ioapic */ + return current; +} diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl new file mode 100644 index 0000000..7f0d40b --- /dev/null +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/* + * Mapping of factory BIOS and coreboot ACPI names + * Factory coreboot + * DBG1 P80 + * + * PX40 LPCB + * PIRx PRTx (x=A|B|C|D) + * PIRQ PCIC + * SYSR MBRS (Hardcoded in acpi_tables.c) + * + * PS2K KBD + * PS2M MOU + * ENFG ENCM (ENTER_CONFIG_MODE) + * EXFG EXCM (EXIT_CONFIG_MODE) + * NIDX ADDR + * NDAT DATA + * LDNM LDN (PNP_LOGICAL_DEVICE) + * + */ +#define SUPERIO_PNP_BASE 0x3F0 +#define SUPERIO_DEV W977 +#define WINBOND_SHOW_UARTA +#define WINBOND_SHOW_UARTB +#define WINBOND_SHOW_FDC +#define WINBOND_SHOW_LPT + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) +{ + OperationRegion(X80, SystemIO, 0x80, 1) + Field(X80, ByteAcc, NoLock, Preserve) + { + P80, 8 + } + /* Define the main processor. */ + Scope (\_PR) + { + /* Looks like the P_CNT field can't be a method or name + * and has to be hardcoded to 0xe410 or generated in SSDT */ + Processor (CPU0, 0x01, 0xe410, 0x06) {} + } + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + */ + + /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */ + /* + 000b / 0x0: soft off/suspend to disk (soff/std) s5 + 001b / 0x1: suspend to ram (str) s3 + 010b / 0x2: powered on suspend, context lost (poscl) s1 + 011b / 0x3: powered on suspend, cpu context lost (posccl) s2 + 100b / 0x4: powered on suspend, context maintained (pos) s4 + 101b / 0x5: working (clock control) s0 + 110b / 0x6: reserved + 111b / 0x7: reserved + */ + Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) + /*Name (\_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/ + Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00) + Name (_UID, 0x00) + Name (_BBN, 0x00) + + /* PCI Routing Table */ + Name (_PRT, Package () { + Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, + Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, + Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, + Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, + + Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, + Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, + Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, + Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, + + Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, + Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, + Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, + Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, + + Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, + Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, + Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, + Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, + + Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, + Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, + Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, + Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, + + Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, + Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, + Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, + Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, + + }) + /* Begin PX40 southbridge block */ +#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" +#include "southbridge/intel/i82371eb/acpi/i82371eb.asl" +#include "southbridge/intel/i82371eb/acpi/pirq.asl" + } + } + OperationRegion (GPOB, SystemIO, 0xE42C, 0x10) + Field (GPOB, ByteAcc, NoLock, Preserve) + { + Offset (0x03), + TO12, 1, /* Device trap 12 */ + Offset (0x08), + FANM, 1, /* GPO0, meant for fan */ + Offset (0x09), + PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet this goes low when power is cut from its core. */ + , 3, + , 2, + , 16, + MSG0, 1 /* GPO30, message LED */ + } + + Method (\_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep, Arg0 is target S-state + { + If (LNotEqual (Arg0, 0x05)) /* Off */ + { + Store (0x00, FANM) /* \FANM */ + Store (0x00, PLED) /* \PLED */ + } + + If (LEqual (Arg0, 0x01)) + { + Store (One, TO12) /* \TO12, arms SMI for device 12 */ + } + + Store (One, TO12) /* \TO12 */ + Or (Arg0, 0xF0, Local2) + Store (Local2, P80) /* Put out a POST code. */ + } + + /* ACPI Message */ + Scope (\_SI) + { + Method (_MSG, 1, NotSerialized) + { + If (LEqual (Arg0, Zero)) + { + Store (One, MSG0) + } + Else + { + Store (Zero, MSG0) + } + } + } +} -- To view, visit https://review.coreboot.org/21672 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87 Gerrit-Change-Number: 21672 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: [WIP] sb/intel/i82371eb: Rework ACPI DSDT table
by Keith Hui (Code Review) 25 Sep '17

25 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21671 Change subject: [WIP] sb/intel/i82371eb: Rework ACPI DSDT table ...................................................................... [WIP] sb/intel/i82371eb: Rework ACPI DSDT table Enter a major ACPI table rework based on a mix of previous work on asus/p2b, other boards in tree with better ACPI support, and OEM BIOS. Pulls in DSDT table for superios if one is defined (only winbond/w83977tf in this group of patches). To be pulled in by DSDTs of mainboards using this southbridge. Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/southbridge/intel/i82371eb/acpi/i82371eb.asl M src/southbridge/intel/i82371eb/acpi/pirq.asl 2 files changed, 245 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21671/1 diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl new file mode 100644 index 0000000..9f3916c --- /dev/null +++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl @@ -0,0 +1,241 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2017 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ +#include "southbridge/intel/i82371eb/i82371eb.h" + +// Intel LPC Bus Device - 0:4.0 +Device (PX40) +{ + Name(_ADR, 0x00040000) + OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) + Field (PIRQ, ByteAcc, NoLock, Preserve) + { + PIRA, 8, + PIRB, 8, + PIRC, 8, + PIRD, 8 + } +/* + * OEM BIOS for asus/p2b-ls reports mainboard resources here whereas + * ACPI programming of asus/p2b fills this in at runtime. + */ +#if 0 + Device (SYSR) + { + Name (_HID, EisaId ("PNP0C02")) + Method (_CRS, 0, NotSerialized) + { + Name (BUF1, ResourceTemplate () + { + IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) + IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) + IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) + IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) + IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C, ) + IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) + IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) + IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) + IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) + IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) + IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) + IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) + IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) + }) + CreateByteField (BUF1, _Y06._MIN, PMLO) // _MIN: Minimum Base Address + CreateByteField (BUF1, 0x03, PMHI) + CreateByteField (BUF1, _Y06._MAX, PMRL) // _MAX: Maximum Base Address + CreateByteField (BUF1, 0x05, PMRH) + CreateByteField (BUF1, _Y07._MIN, SBLO) // _MIN: Minimum Base Address + CreateByteField (BUF1, 0x0B, SBHI) + CreateByteField (BUF1, _Y07._MAX, SBRL) // _MAX: Maximum Base Address + CreateByteField (BUF1, 0x0D, SBRH) + Store (\_SB.PCI0.PX43.PM00, Local0) + And (Local0, 0xFE, PMLO) /* \_SB_.PCI0.PX40.SYSR._CRS.PMLO */ + Store (\_SB.PCI0.PX43.PM01, PMHI) /* \_SB_.PCI0.PX40.SYSR._CRS.PMHI */ + Store (\_SB.PCI0.PX43.SB00, Local0) + And (Local0, 0xFE, SBLO) /* \_SB_.PCI0.PX40.SYSR._CRS.SBLO */ + Store (\_SB.PCI0.PX43.SB01, SBHI) /* \_SB_.PCI0.PX40.SYSR._CRS.SBHI */ + Store (PMLO, PMRL) /* \_SB_.PCI0.PX40.SYSR._CRS.PMRL */ + Store (PMHI, PMRH) /* \_SB_.PCI0.PX40.SYSR._CRS.PMRH */ + Store (SBLO, SBRL) /* \_SB_.PCI0.PX40.SYSR._CRS.SBRL */ + Store (SBHI, SBRH) /* \_SB_.PCI0.PX40.SYSR._CRS.SBRH */ + Return (BUF1) /* \_SB_.PCI0.PX40.SYSR._CRS.BUF1 */ + } + } +#endif +/* If a superio (with DSDT table) is selected in mainboard Kconfig, + * include its ASL code here, otherwise declare a few basic devices + * that seems to be important for WinXP install. */ +#ifdef CONFIG_SUPERIO_WINBOND_W83977TF +#include "superio/winbond/w83977tf/acpi/superio.asl" +#else + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* PS/2 floppy controller */ + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (BUF0, ResourceTemplate () { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) + IRQNoFlags () {6} + DMA (Compatibility, NotBusMaster, Transfer8) {2} + }) + Return (BUF0) + } + } +#endif + /* PNP Motherboard Resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + External(_CRS) /* Resource Template in SSDT */ + } + + /* 8259-compatible Programmable Interrupt Controller */ + Device (PIC) + { + Name (_HID, EisaId ("PNP0000") ) + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, ) + IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, ) + IRQNoFlags () {2} + }) + } + + /* PC-class DMA Controller */ + Device (DMA1) + { + Name (_HID, EisaId ("PNP0200") ) + Name (_CRS, ResourceTemplate () + { + DMA (Compatibility, BusMaster, Transfer8, ) {4} + IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,) + IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,) + IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,) + IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20,) + }) + } + + /* PC-class System Timer */ + Device (TMR) + { + Name (_HID, EisaId ("PNP0100")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16,0x0040,0x0040,0x01,0x04,) + IRQNoFlags () {0} + }) + } + + /* AT Real-Time Clock */ + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") ) + Name (_CRS, ResourceTemplate () + { + IO (Decode16,0x0070,0x0070,0x01,0x04,) + IRQNoFlags () {8} + }) + } + + Device (SPKR) + { + Name (_HID, EisaId ("PNP0800")) + Name (_CRS, ResourceTemplate () + { + IO (Decode16,0x0061,0x0061,0x01,0x01,) + }) + } + + /* x87-compatible Floating Point Processing Unit */ + Device (COPR) + { + Name (_HID, EisaId ("PNP0C04") ) + Name (_CRS, ResourceTemplate () + { + IO (Decode16,0x00F0,0x00F0,0x01,0x10,) + IRQNoFlags () {13} + }) + } + +} +/* Power management functions to allow ACPI reporting of + * PM and SMBus base port resources */ +Device (PX43) +{ + Name (_ADR, 0x00040003) // _ADR: Address + OperationRegion (IPMU, PCI_Config, PMBA, 0x02) + Field (IPMU, ByteAcc, NoLock, Preserve) + { + PM00, 8, + PM01, 8 + } + + OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) + Field (ISMB, ByteAcc, NoLock, Preserve) + { + SB00, 8, + SB01, 8 + } +} diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl index 6525e1e..e36a0ec 100644 --- a/src/southbridge/intel/i82371eb/acpi/pirq.asl +++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl @@ -12,16 +12,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -Field (\_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve) -{ - Offset (0x60), // Interrupt Routing Registers - PRTA, 8, - PRTB, 8, - PRTC, 8, - PRTD, 8, -} - Name(IRQB, ResourceTemplate(){ IRQ(Level,ActiveLow,Shared){15} }) @@ -69,7 +59,7 @@ } \ } \ -PCI_INTX_DEV(LNKA, PRTA, 1) -PCI_INTX_DEV(LNKB, PRTB, 2) -PCI_INTX_DEV(LNKC, PRTC, 3) -PCI_INTX_DEV(LNKD, PRTD, 4) +PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) +PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) +PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3) +PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4) -- To view, visit https://review.coreboot.org/21671 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 Gerrit-Change-Number: 21671 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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coreboot-gerrit September 2017