coreboot-gerrit September 2017

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Change in coreboot[master]: device/dram/ddr2.c: Store the checksum in the decoded SPD struct
by Arthur Heymans (Code Review) 25 Sep '17

25 Sep '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21676 Change subject: device/dram/ddr2.c: Store the checksum in the decoded SPD struct ...................................................................... device/dram/ddr2.c: Store the checksum in the decoded SPD struct Change-Id: I53f4a3e4030ea19e10c0fe11a99a3480644f5fae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/dram/ddr2.c M src/include/device/dram/ddr2.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/21676/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index d524238..c6cf8df 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -322,6 +322,7 @@ dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_CRC_ERROR; } + dimm->checksum = spd[63]; reg8 = spd[62]; if ((reg8 & 0xf0) != 0x10) { diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 288c102..7322b12 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -186,6 +186,7 @@ u32 tPLL; u32 tRR; + u8 checksum; /* Manufacturer ID */ u32 manufacturer_id; /* ASCII part number - NULL terminated */ -- To view, visit https://review.coreboot.org/21676 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I53f4a3e4030ea19e10c0fe11a99a3480644f5fae Gerrit-Change-Number: 21676 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/i82801{i, j}x: Hook up spi code
by Arthur Heymans (Code Review) 25 Sep '17

25 Sep '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21675 Change subject: sb/intel/i82801{i,j}x: Hook up spi code ...................................................................... sb/intel/i82801{i,j}x: Hook up spi code Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801jx/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21675/1 diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 6879bce..3913e7a 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -18,6 +18,7 @@ bool select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 5edaf1a..e418a94 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -18,6 +18,7 @@ bool select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET -- To view, visit https://review.coreboot.org/21675 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732 Gerrit-Change-Number: 21675 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI to include spi code
by Arthur Heymans (Code Review) 25 Sep '17

25 Sep '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21674 Change subject: sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI to include spi code ...................................................................... sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI to include spi code Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/fsp_bd82x6x/Kconfig M src/southbridge/intel/fsp_bd82x6x/Makefile.inc M src/southbridge/intel/fsp_i89xx/Kconfig M src/southbridge/intel/fsp_i89xx/Makefile.inc M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/Makefile.inc M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/Makefile.inc M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/Makefile.inc 14 files changed, 15 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21674/1 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index e3772ba..fe1ca34 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -26,6 +26,7 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI select IOAPIC select HAVE_HARD_RESET select HAVE_USBDEBUG_OPTIONS @@ -33,7 +34,6 @@ select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK - select SPI_FLASH select COMMON_FADT select ACPI_SATA_GENERATOR select HAVE_INTEL_FIRMWARE diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 8e88268..a5825a8 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -35,8 +35,6 @@ ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += ../common/spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 304ecbf..616658e 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -8,6 +8,10 @@ def_bool n select HAVE_DEBUG_SMBUS +config SOUTHBRIDGE_INTEL_COMMON_SPI + def_bool n + select SPI_FLASH + config HAVE_INTEL_CHIPSET_LOCKDOWN def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 5810394..0128505 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -28,4 +28,9 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c +endif + endif diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index 08400b3..877a335 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -28,11 +28,11 @@ select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK - select SPI_FLASH select COMMON_FADT select HAVE_INTEL_FIRMWARE select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_INTEL_CHIPSET_LOCKDOWN config EHCI_BAR diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 265633c..93253e9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -27,8 +27,6 @@ ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += ../common/spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig index 67c2665..d0cb45c 100644 --- a/src/southbridge/intel/fsp_i89xx/Kconfig +++ b/src/southbridge/intel/fsp_i89xx/Kconfig @@ -28,12 +28,12 @@ select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK - select SPI_FLASH select COMMON_FADT select HAVE_INTEL_FIRMWARE select NO_EARLY_BOOTBLOCK_POSTCODES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_i89xx/Makefile.inc b/src/southbridge/intel/fsp_i89xx/Makefile.inc index f9bbdc6..d8eb067 100644 --- a/src/southbridge/intel/fsp_i89xx/Makefile.inc +++ b/src/southbridge/intel/fsp_i89xx/Makefile.inc @@ -26,8 +26,6 @@ ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += ../common/spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index fd7579a..9fd19ed 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -23,9 +23,9 @@ select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select COMMON_FADT - select SPI_FLASH select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 5b3ba6a..bb68d93 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -27,7 +27,6 @@ ramstage-y += smbus.c ramstage-y += usb.c ramstage-y += usb_ehci.c -ramstage-y += ../common/spi.c ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 4b78118..60af933 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -28,9 +28,9 @@ select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK - select SPI_FLASH select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 41d3afb..7714f95 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -35,9 +35,7 @@ ramstage-y += ../bd82x6x/watchdog.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c -ramstage-y += ../common/spi.c ramstage-y += madt.c -smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-y += smi.c smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 646d480..8d5cbbf 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -23,13 +23,13 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SPI select IOAPIC select HAVE_HARD_RESET select HAVE_USBDEBUG_OPTIONS select USE_WATCHDOG_ON_BOOT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK - select SPI_FLASH select HAVE_INTEL_FIRMWARE select HAVE_SPI_CONSOLE_SUPPORT select RTC diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 3b1ce5a..6abdf4d 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,8 +41,6 @@ ramstage-y += acpi.c ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += ../common/spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c -- To view, visit https://review.coreboot.org/21674 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Gerrit-Change-Number: 21674 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: memtest: Add disable SPD option to coreboot menuconfig
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21632 ) Change subject: memtest: Add disable SPD option to coreboot menuconfig ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61024/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16199/ : SUCCESS -- To view, visit https://review.coreboot.org/21632 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I72774f296bb977ddb7aedd77ccbd6f1ad6b30916 Gerrit-Change-Number: 21632 Gerrit-PatchSet: 5 Gerrit-Owner: Micha? ?ygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Micha? ?ygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 09:04:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: fix a hidden syntax error introduced earlier
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21673 ) Change subject: device/dram/ddr2.c: fix a hidden syntax error introduced earlier ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61023/ : SUCCESS -- To view, visit https://review.coreboot.org/21673 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b Gerrit-Change-Number: 21673 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 08:46:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: fix a minor regression introduced earlier
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21673 ) Change subject: device/dram/ddr2.c: fix a minor regression introduced earlier ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61022/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16198/ : SUCCESS -- To view, visit https://review.coreboot.org/21673 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b Gerrit-Change-Number: 21673 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 08:05:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: fix a minor regression introduced earlier
by Arthur Heymans (Code Review) 25 Sep '17

25 Sep '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21673 ) Change subject: device/dram/ddr2.c: fix a minor regression introduced earlier ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/21673 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b Gerrit-Change-Number: 21673 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 25 Sep 2017 08:01:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: fix a minor regression introduced earlier
by Bill XIE (Code Review) 25 Sep '17

25 Sep '17

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/21673 Change subject: device/dram/ddr2.c: fix a minor regression introduced earlier ...................................................................... device/dram/ddr2.c: fix a minor regression introduced earlier A regression is hidden in Change I091121a5d08159cea4befdedb5f3a92ce132c6e5, which breaks the build procedure when CONFIG_DEBUG_RAM_SETUP is set. Maybe it had better implement "printram" and the like as inline functions instead of macros. Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/device/dram/ddr2.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21673/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index d524238..e06e342 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -547,7 +547,7 @@ ret = SPD_STATUS_INVALID_FIELD; dimm->flags.self_refresh = (spd[12] >> 7) & 1; printram("The assembly supports self refresh: %s\n", - dimm->flags.self_refresh ? "true", "false"); + dimm->flags.self_refresh ? "true" : "false"); /* Number of PLLs on DIMM */ if (dimm->rev >= 0x11) -- To view, visit https://review.coreboot.org/21673 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b Gerrit-Change-Number: 21673 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com>

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Change in coreboot[master]: memtest: Add disable SPD option to coreboot menuconfig
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21632 ) Change subject: memtest: Add disable SPD option to coreboot menuconfig ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61021/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16197/ : SUCCESS -- To view, visit https://review.coreboot.org/21632 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I72774f296bb977ddb7aedd77ccbd6f1ad6b30916 Gerrit-Change-Number: 21632 Gerrit-PatchSet: 4 Gerrit-Owner: Micha? ?ygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Micha? ?ygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 06:29:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add support in SKL for PMC common code
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20499 ) Change subject: soc/intel/skylake: Add support in SKL for PMC common code ...................................................................... Patch Set 13: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61020/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16196/ : SUCCESS -- To view, visit https://review.coreboot.org/20499 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Gerrit-Change-Number: 20499 Gerrit-PatchSet: 13 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 06:14:32 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017