coreboot-gerrit September 2017

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Change in coreboot[master]: soc/intel/skylake: [WIP] Add config for mbx command for Intersil VR C...
by Rizwan Qureshi (Code Review) 25 Sep '17

25 Sep '17

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/21680 Change subject: soc/intel/skylake: [WIP] Add config for mbx command for Intersil VR C-state issues ...................................................................... soc/intel/skylake: [WIP] Add config for mbx command for Intersil VR C-state issues Config for activating VR mailbox command for Intersil VR C-state issues. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/21680/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 606078b..8c6e45a 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -518,6 +518,14 @@ /* coreboot handles locking */ CHIPSET_LOCKDOWN_COREBOOT, } chipset_lockdown; + + /* + * Activates VR mailbox command for Intersil VR C-state issues. + * 0 - no mailbox command sent. + * 1 - VR mailbox command sent for IA/GT rails only. + * 2 - VR mailbox command sent for IA/GT/SA rails. + */ + u8 IslVrCmd; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index b1697ae..ac60125 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -271,6 +271,14 @@ */ params->SendVrMbxCmd1 = config->SendVrMbxCmd; + /* + * Activates VR mailbox command for Intersil VR C-state issues. + * 0 - no mailbox command sent. + * 1 - VR mailbox command sent for IA/GT rails only. + * 2 - VR mailbox command sent for IA/GT/SA rails. + */ + params->IslVrCmd = config->IslVrCmd; + /* Acoustic Noise Mitigation */ params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; params->SlowSlewRateForIa = config->SlowSlewRateForIa; -- To view, visit https://review.coreboot.org/21680 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4 Gerrit-Change-Number: 21680 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: FSP.2.7.2 :[WIP] Update of header files
by Rizwan Qureshi (Code Review) 25 Sep '17

25 Sep '17

Hello Balaji Manigandan, I'd like you to do a code review. Please visit https://review.coreboot.org/21679 to review the following change. Change subject: FSP.2.7.2 :[WIP] Update of header files ...................................................................... FSP.2.7.2 :[WIP] Update of header files Updating the variable changed in meminfo hob Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h M src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h 5 files changed, 187 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/21679/1 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index c43bdc3..cbf934e 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -80,11 +80,11 @@ dimm_max = ARRAY_SIZE(mem_info->dimm); ctrlr_info = &memory_info_hob->Controller[0]; for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { - channel_info = &ctrlr_info->Channel[channel]; + channel_info = &ctrlr_info->ChannelInfo[channel]; if (channel_info->Status != 2) continue; for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { - src_dimm = &channel_info->Dimm[dimm]; + src_dimm = &channel_info->DimmInfo[dimm]; dest_dimm = &mem_info->dimm[index]; if (src_dimm->Status != DIMM_PRESENT) @@ -93,8 +93,8 @@ /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, - memory_info_hob->DdrType, - memory_info_hob->Frequency, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, channel_info->ChannelId, src_dimm->DimmId, (const char *)src_dimm->ModulePartNum, diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h index c8cdc5f..5a32d78 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h @@ -1,20 +1,34 @@ /** @file FSP CPU Data Config Block. -@copyright - Copyright (c) 2016 Intel Corporation. All rights reserved - This software and associated documentation (if any) is furnished - under a license and may only be used or copied in accordance - with the terms of the license. Except as permitted by the - license, no part of this software or documentation may be - reproduced, stored in a retrieval system, or transmitted in any - form or by any means without the express written consent of - Intel Corporation. - This file contains an 'Intel Peripheral Driver' and is uniquely - identified as "Intel Reference Module" and is licensed for Intel - CPUs and chipsets under the terms of your license agreement with - Intel or your vendor. This file may be modified by the user, subject - to additional terms of the license agreement. + @copyright + INTEL CONFIDENTIAL + Copyright 2016 Intel Corporation. + + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. + + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. + + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. + + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. @par Specification Reference: **/ @@ -63,9 +77,10 @@ UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. UINT32 RsvdBits : 15; ///< Reserved for future use UINT32 Reserved; - } Bits; - UINT32 Uint32[2]; -} CPU_CONFIG_FSP_DATA; + } Bits; + UINT32 Uint32[2]; + } CPU_CONFIG_FSP_DATA; + #pragma pack (pop) #endif // _CPU_CONFIG_FSP_DATA_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h index 1916e4e..f3aa4c8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -844,7 +844,7 @@ /** Offset 0x02E3 - Ring Downbin Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. + lower than the core ratio. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 RingDownBin; @@ -1255,9 +1255,15 @@ **/ UINT8 Avx3RatioOffset; -/** Offset 0x051B +/** Offset 0x051B - Ask MRC to clear memory content + Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. + $EN_DIS **/ - UINT8 ReservedFspmUpd[5]; + UINT8 CleanMemory; + +/** Offset 0x051C +**/ + UINT8 ReservedFspmUpd[4]; } FSP_M_CONFIG; /** Fsp M Test Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h index b3c7698..f4f4bad 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -167,7 +167,7 @@ /** Offset 0x0036 - Flash Configuration Lock Down Enable/disable flash lock down. If platform decides to skip this programming, it - must lock SPI flash register before end of post. + must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. $EN_DIS **/ UINT8 SpiFlashCfgLockDown; @@ -484,7 +484,7 @@ /** Offset 0x020C - PCIe DeEmphasis control per root port 0: -6dB, 1(Default): -3.5dB - 0:Disable, 2:L1 + 0:-6dB, 1:-3.5dB **/ UINT8 PegDeEmphasis[3]; @@ -2060,9 +2060,15 @@ **/ UINT8 MeUnconfigIsValid; -/** Offset 0x077A +/** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues. + Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox + command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails. **/ - UINT8 ReservedFspsUpd[6]; + UINT8 IslVrCmd; + +/** Offset 0x077B +**/ + UINT8 ReservedFspsUpd[5]; } FSP_S_CONFIG; /** Fsp S Test Configuration @@ -2107,7 +2113,7 @@ UINT8 DmiIot; /** Offset 0x0789 - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0X2: Force 256B + 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B **/ UINT8 PegMaxPayload[3]; @@ -2520,25 +2526,25 @@ /** Offset 0x07DA - Enable or Disable Package C-State Demotion Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; 2: Auto (Auto: Enabled for Skylake; Disabled for Kabylake) - $EN_DIS + 0:Disable, 1:Enable, 2:Auto **/ UINT8 PkgCStateDemotion; /** Offset 0x07DB - Enable or Disable Package C-State UnDemotion Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; 2: Auto (Auto: Enabled for Skylake; Disabled for Kabylake) - $EN_DIS + 0:Disable, 1:Enable, 2:Auto **/ UINT8 PkgCStateUnDemotion; /** Offset 0x07DC - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. Disable; 1: Enable + Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; /** Offset 0x07DD - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. Disable; 1: Enable + Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; @@ -2606,7 +2612,7 @@ /** Offset 0x07E8 - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate + Up; 0xFF: Deactivate 0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate **/ UINT8 ConfigTdpLevel; @@ -2632,12 +2638,14 @@ UINT16 StateRatio[40]; /** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0 - Interrupt Response Time Limit of C-State LatencyContol0. Range of value 0 to 0x3FF + Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF, + Default is 0x4E, Server Platform is 0x4B **/ UINT16 CstateLatencyControl0Irtl; /** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF + Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF, + Default is 0x76, Server Platform is 0x6B **/ UINT16 CstateLatencyControl1Irtl; @@ -2783,11 +2791,18 @@ **/ UINT8 EightCoreRatioLimit; -/** Offset 0x0888 - ReservedCpuPostMemTest +/** Offset 0x0888 - Set Three Strike Counter Disable + False (default): Three Strike counter will be incremented and True: Prevents Three + Strike counter from incrementing; 0: False; 1: True. + 0: False, 1: True +**/ + UINT8 ThreeStrikeCounterDisable; + +/** Offset 0x0889 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[2]; + UINT8 ReservedCpuPostMemTest[1]; /** Offset 0x088A - SgxSinitDataFromTpm SgxSinitDataFromTpm default values @@ -2923,7 +2938,7 @@ UINT8 PchPmDisableEnergyReport; /** Offset 0x0A2F - PCH Pm Pmc Read Disable - When set to true, this bit disallows host reads to PMC XRAM. + Deprecated $EN_DIS **/ UINT8 PchPmPmcReadDisable; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h index 8dc2db9..11f79ca 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h @@ -1,33 +1,38 @@ /** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. -Copyright (c) 2016, Intel Corporation. All rights reserved. + @copyright + INTEL CONFIDENTIAL + Copyright 1999 - 2017 Intel Corporation. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: + The source code contained or described herein and all documents related to the + source code ("Material") are owned by Intel Corporation or its suppliers or + licensors. Title to the Material remains with Intel Corporation or its suppliers + and licensors. The Material may contain trade secrets and proprietary and + confidential information of Intel Corporation and its suppliers and licensors, + and is protected by worldwide copyright and trade secret laws and treaty + provisions. No part of the Material may be used, copied, reproduced, modified, + published, uploaded, posted, transmitted, distributed, or disclosed in any way + without Intel's prior express written permission. -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. + No license under any patent, copyright, trade secret or other intellectual + property right is granted to or conferred upon you by disclosure or delivery + of the Materials, either expressly, by implication, inducement, estoppel or + otherwise. Any license under such intellectual property rights must be + express and approved by Intel in writing. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. + Unless otherwise agreed by Intel in writing, you may not remove or alter + this notice or any other notice embedded in Materials by Intel or + Intel's suppliers or licensors in any way. - This file is automatically generated. Please do NOT modify !!! + This file contains an 'Intel Peripheral Driver' and is uniquely identified as + "Intel Reference Module" and is licensed for Intel CPUs and chipsets under + the terms of your license agreement with Intel or your vendor. This file may + be modified by the user, subject to additional terms of the license agreement. +@par Specification Reference: **/ #ifndef _MEM_INFO_HOB_H_ #define _MEM_INFO_HOB_H_ @@ -52,6 +57,25 @@ #define B_RANK1_PRS BIT1 #define B_RANK2_PRS BIT4 #define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif /// /// Defines taken from MRC so avoid having to include MrcInterface.h @@ -122,7 +146,7 @@ #define MRC_DDR_TYPE_UNKNOWN 3 #endif -#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_PROFILE_NUM 4 // number of memory profiles supported #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported // @@ -151,64 +175,102 @@ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. } MRC_CH_TIMING; +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. +} MRC_TA_TIMING; + /// /// Memory SMBIOS & OC Memory Data Hob /// typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. } DIMM_INFO; typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics. + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. } CHANNEL_INFO; typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions. + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. + MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings + MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings + MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings + MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings } CONTROLLER_INFO; typedef struct { UINT8 Revision; - UINT16 DataWidth; + UINT16 DataWidth; ///< Data width, in bits, of this memory device /** As defined in SMBIOS 3.0 spec Section 7.18.2 and Table 75 **/ - UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT32 Frequency; ///< The system's common memory controller frequency in MT/s. + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) /** As defined in SMBIOS 3.0 spec Section 7.17.3 and Table 72 **/ UINT8 ErrorCorrectionType; SiMrcVersion Version; - UINT32 FreqMax; BOOLEAN EccSupport; UINT8 MemoryProfile; UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. UINT8 Ratio; UINT8 RefClk; UINT32 VddVoltage[MAX_PROFILE_NUM]; CONTROLLER_INFO Controller[MAX_NODE]; } MEMORY_INFO_DATA_HOB; +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT32 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + #pragma pack (pop) #endif // _MEM_INFO_HOB_H_ -- To view, visit https://review.coreboot.org/21679 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Gerrit-Change-Number: 21679 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com>

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Change in coreboot[master]: nb/intel/x4x: Use SPI flash to cache raminit results
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21677 ) Change subject: nb/intel/x4x: Use SPI flash to cache raminit results ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61041/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16216/ : SUCCESS -- To view, visit https://review.coreboot.org/21677 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f Gerrit-Change-Number: 21677 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 12:15:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x: Use SPI flash to cache raminit results
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21677 ) Change subject: nb/intel/x4x: Use SPI flash to cache raminit results ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61037/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16212/ : SUCCESS -- To view, visit https://review.coreboot.org/21677 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f Gerrit-Change-Number: 21677 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 11:22:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: Store the checksum in the decoded SPD struct
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21676 ) Change subject: device/dram/ddr2.c: Store the checksum in the decoded SPD struct ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61036/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16211/ : SUCCESS -- To view, visit https://review.coreboot.org/21676 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53f4a3e4030ea19e10c0fe11a99a3480644f5fae Gerrit-Change-Number: 21676 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 11:20:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82801jx: Hook up spi code
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21675 ) Change subject: sb/intel/i82801jx: Hook up spi code ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61035/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16210/ : SUCCESS -- To view, visit https://review.coreboot.org/21675 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732 Gerrit-Change-Number: 21675 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 11:19:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82801jx: Hook up spi code
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21675 ) Change subject: sb/intel/i82801jx: Hook up spi code ...................................................................... Patch Set 2: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/61032/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/16207/ : SUCCESS -- To view, visit https://review.coreboot.org/21675 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732 Gerrit-Change-Number: 21675 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 11:14:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82801jx: Hook up spi code
by Arthur Heymans (Code Review) 25 Sep '17

25 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21675 to look at the new patch set (#3). Change subject: sb/intel/i82801jx: Hook up spi code ...................................................................... sb/intel/i82801jx: Hook up spi code Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/i82801jx/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21675/3 -- To view, visit https://review.coreboot.org/21675 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie83c800a0bcd12fa501c91a1c2b1ee756de9d732 Gerrit-Change-Number: 21675 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: device/dram/ddr2.c: Store the checksum in the decoded SPD struct
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21676 ) Change subject: device/dram/ddr2.c: Store the checksum in the decoded SPD struct ...................................................................... Patch Set 2: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61033/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16208/ : SUCCESS -- To view, visit https://review.coreboot.org/21676 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53f4a3e4030ea19e10c0fe11a99a3480644f5fae Gerrit-Change-Number: 21676 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 11:13:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x: Use SPI flash to cache raminit results
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21677 ) Change subject: nb/intel/x4x: Use SPI flash to cache raminit results ...................................................................... Patch Set 2: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/61034/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/16209/ : SUCCESS -- To view, visit https://review.coreboot.org/21677 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f Gerrit-Change-Number: 21677 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 11:09:37 +0000 Gerrit-HasComments: No

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