coreboot-gerrit September 2017

coreboot-gerrit@coreboot.org

1 participants
1960 discussions

Change in coreboot[master]: [WIP] winbond/w83977tf: Add ACPI DSDT table
by Keith Hui (Code Review) 25 Sep '17

25 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21670 Change subject: [WIP] winbond/w83977tf: Add ACPI DSDT table ...................................................................... [WIP] winbond/w83977tf: Add ACPI DSDT table Add DSDT table for this superio to be incorporated into ACPI tables for mainboards with this superio. Part of the in-progress work to add ACPI support to asus/p[23]b* family of mainboards. Change-Id: If113807901619bc0f4250607546be415f9e5e45b Signed-off-by: Keith Hui <buurin(a)gmail.com> --- A src/superio/winbond/w83977tf/acpi/superio.asl 1 file changed, 424 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21670/1 diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl new file mode 100644 index 0000000..030ba86 --- /dev/null +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -0,0 +1,424 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a southbridge ASL block and it will + * expose the W83977TF/EF SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * WINBOND_SHOW_UARTA If defined, UARTA will be exposed. + * WINBOND_SHOW_UARTB If defined, UARTB will be exposed. + * WINBOND_SHOW_FDC If defined, floppy controller will be exposed. + * WINBOND_SHOW_LPT If defined, parallel port will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME W83977TF +#include <superio/acpi/pnp.asl> +#include <superio/winbond/w83977tf/w83977tf.h> +/* +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Winbond W83977TF/EF Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) +*/ + /* Mutex for accesses to the configuration ports */ + + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + Offset (0x20), + DID, 8, /* Device ID: TF=0x97, EF=0x52 */ + DREV, 8, /* Device revision */ + FDPW, 1, /* FDC Power Down */ + , 2, + PRPW, 1, /* PRT Power Down */ + UAPW, 1, /* UART A Power Down */ + UBPW, 1, /* UART B Power Down */ + Offset (0x23), + IPD, 1, /* Immediate Chip Power Down */ + Offset (0x30), + PNP_DEVICE_ACTIVE, 8, /* PNP_DEVICE_ACTIVE = "ACTR" to match common ASLs */ + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, + PNP_IO0_LOW_BYTE, 8, + PNP_IO1_HIGH_BYTE, 8, + PNP_IO1_LOW_BYTE, 8, + PNP_IO2_HIGH_BYTE, 8, + PNP_IO2_LOW_BYTE, 8, + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + Offset (0x72), + PNP_IRQ1, 8, /* Second IRQ */ + Offset (0x74), + PNP_DMA0, 8, /* DMA */ + Offset (0xE0), + MSWK, 8, + Offset (0xE4), + KBWK, 8, + Offset (0xF0), + OPT1, 8, + OPT2, 8 + } + +#undef PNP_ENTER_MAGIC_1ST +#undef PNP_ENTER_MAGIC_2ND +#undef PNP_ENTER_MAGIC_3RD +#undef PNP_ENTER_MAGIC_4TH +#undef PNP_EXIT_MAGIC_1ST +#undef PNP_EXIT_SPECIAL_REG +#undef PNP_EXIT_SPECIAL_VAL +#define PNP_ENTER_MAGIC_1ST 0x87 +#define PNP_ENTER_MAGIC_2ND 0x87 +#define PNP_EXIT_MAGIC_1ST 0xaa +#include <superio/acpi/pnp_config.asl> + +/* This version from OEM bios waits up to 17 cycles till superio identifies itself +Method (ENFG, 0, NotSerialized) +{ + Store (0x00, Local0) + Store (0x11, Local1) + While (LNotEqual (Local0, 0x71)) + { + Store (0x87, ADDR) + Store (0x87, ADDR) + If (LOr (LEqual (DEVI, 0x97), LEqual (DEVI, 0x52))) + { + Store (0x71, Local0) + } + + Decrement (Local1) + If (LEqual (Local1, 0x00)) + { + Store (0x71, Local0) + } + } +} +*/ + /* PM: indicate IPD (Immediate Power Down) bit state as D0/D2 */ + Method (_PSC) { + ENCM (0xFF) + Store (IPD, Local0) + EXCM () + If (Local0) { Return (2) } + Else { Return (0) } + } + +#ifdef WINBOND_SHOW_FDC +Device (FDC0) +{ + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + PNP_GENERIC_STA(W83977TF_FDC) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PNP_GENERIC_DIS(W83977TF_FDC) + } + + Method (_CRS, 0) // _CRS: Current Resource Settings + { + Name (BUF0, ResourceTemplate () + { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04, IO0) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01, IO1) + IRQ (Edge, ActiveHigh, Exclusive, Y08) {6} + DMA (Compatibility, NotBusMaster, Transfer8, Y09) {2} + }) + CreateWordField (BUF0, IO1._MIN, IO1I) + CreateWordField (BUF0, IO1._MAX, IO1A) + + ENTER_CONFIG_MODE(W83977TF_FDC) + /* OEM BIOS does not report actual programmed base port */ + /* xx0 is read from superio */ + PNP_READ_IO(PNP_IO0, BUF0, IO0) + /* Store xx7 range first so the value isn't overwritten + * for below */ + Add(IO0I, 7, IO1I) + Store(IO1I, IO1A) + /* Store xx2 range */ + Add(IO0I, 2, IO0I) + Store(IO0I, IO0A) + /* End OEM BIOS deficiency */ + PNP_READ_IRQ(PNP_IRQ0, BUF0, Y08) + PNP_READ_DMA(PNP_DMA0, BUF0, Y09) + EXIT_CONFIG_MODE() + Return (BUF0) + } + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04, ) + IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01, ) + IRQ (Edge, ActiveHigh, Exclusive, ) {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) {2} + }) + Method (_SRS, 1, NotSerialized) + { + CreateByteField (Arg0, 0x02, IOLO) + CreateByteField (Arg0, 0x03, IOHI) + CreateWordField (Arg0, 0x11, IRQW) + CreateByteField (Arg0, 0x15, DMAV) + ENTER_CONFIG_MODE(W83977TF_FDC) + /* FDC base port on 8-byte boundary. */ + And (IOLO, 0xF8, PNP_IO0_LOW_BYTE) + Store (IOHI, PNP_IO0_HIGH_BYTE) + Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0) + Subtract (FindSetLeftBit (DMAV), 1, PNP_DMA0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE() + } +} +#endif +#ifdef WINBOND_SHOW_LPT +Device (LPT) +{ + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + ENTER_CONFIG_MODE(W83977TF_PP) + And (OPT1, 0x02, Local0) + If (LOr (IO0H, IO0L)) + { + If (LEqual (Local0, 0x02)) /* Report device not present if ECP is enabled */ + { + EXIT_CONFIG_MODE() + Return (0x00) + } + ElseIf (ACTR) + { + EXIT_CONFIG_MODE() + Return (0x0F) + } + Else + { + EXIT_CONFIG_MODE() + Return (0x0D) + } + } + + EXIT_CONFIG_MODE() + Return (0) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PNP_GENERIC_DIS(W83977TF_PP) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (BUF5, ResourceTemplate () + { + IO (Decode16,0x0378,0x0378,0x00,0x04,Y0A) + IRQ (Edge, ActiveHigh, Exclusive, Y0B) + {7} + }) + ENTER_CONFIG_MODE(W83977TF_PP) + PNP_READ_IO(PNP_IO0,BUF5,Y0A) + PNP_READ_IRQ(PNP_IRQ0,BUF5,Y0B) + EXIT_CONFIG_MODE() + Return (BUF5) + } + + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x0378,0x0378,0x00,0x08,) + IRQ (Edge, ActiveHigh, Exclusive, ) + {5,7} + } + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x0278,0x0278,0x00,0x08,) + IRQ (Edge, ActiveHigh, Exclusive, ) + {5,7} + } + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x03BC,0x03BC,0x00,0x04,) + IRQ (Edge, ActiveHigh, Exclusive, ) + {5,7} + } + EndDependentFn () + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateByteField (Arg0, 0x02, IOLO) + CreateByteField (Arg0, 0x03, IOHI) + CreateWordField (Arg0, 0x09, IRQW) + ENTER_CONFIG_MODE(W83977TF_PP) + Store (IOLO, PNP_IO0_LOW_BYTE) + Store (IOHI, PNP_IO0_HIGH_BYTE) + Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE() + } +} +/* ECP Parallel Port */ +Device (ECP) +{ + Name (_HID, EisaId ("PNP0401")) + Method (_STA, 0, NotSerialized) + { + ENTER_CONFIG_MODE(W83977TF_PP) + And (OPT1, 0x02, Local0) + If (LOr (IO0H, IO0L)) + { + If (LEqual (Local0, 0x02)) + { + If (ACTR) + { + EXIT_CONFIG_MODE() + Return (0x0F) + } + Else + { + EXIT_CONFIG_MODE() + Return (0x05) + } + } + } + + EXIT_CONFIG_MODE() + Return (0x00) + } + + Method (_DIS, 0, NotSerialized) + { + PNP_GENERIC_DIS(W83977TF_PP) + } + + Method (_CRS, 0, NotSerialized) + { + Name (BUF6, ResourceTemplate () + { + IO (Decode16,0x0378,0x0378,0,4,IO0) + IO (Decode16,0x0778,0x0778,0,4,IO1) + IRQ (Edge, ActiveHigh, Exclusive, IR1) {7} + DMA (Compatibility, NotBusMaster, Transfer8, Y0F) {1} + }) + ENTER_CONFIG_MODE(W83977TF_PP) + PNP_READ_IO(PNP_IO0, BUF6, IO0) + PNP_READ_IO(PNP_IO1, BUF6, IO1) + PNP_READ_IRQ(PNP_IRQ0, BUF6, IR1) + PNP_READ_DMA(PNP_DMA0, BUF6, Y0F) + + /* Report a second port range that is 0x400 above base port. */ + CreateByteField (BUF6, 0x03, IOHI) + CreateByteField (BUF6, 0x0B, I2HI) + CreateByteField (BUF6, 0x0D, I2RH) + Add (IOHI, 0x04, I2HI) + Add (IOHI, 0x04, I2RH) + EXIT_CONFIG_MODE() + Return (BUF6) + } + + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x0378,0x0378,0,4,) + IO (Decode16,0x0778,0x0778,0,4,) + IRQ (Edge, ActiveHigh, Exclusive, ) {5,7} + DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3} + } + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x0278,0x0278,0,4,) + IO (Decode16,0x0678,0x0678,0,4,) + IRQ (Edge, ActiveHigh, Exclusive, ) {5,7} + DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3} + } + StartDependentFn (0x01, 0x01) + { + IO (Decode16,0x03BC,0x03BC,0,4,) + IO (Decode16,0x07BC,0x07BC,0,4,) + IRQ (Edge, ActiveHigh, Exclusive, ) {5,7} + DMA (Compatibility, NotBusMaster, Transfer8, ) {0,1,3} + } + EndDependentFn () + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateByteField (Arg0, 0x02, IOLO) + CreateByteField (Arg0, 0x03, IOHI) + CreateWordField (Arg0, 0x11, IRQW) + CreateByteField (Arg0, 0x15, DMAC) + + ENTER_CONFIG_MODE(W83977TF_PP) + Store (IOLO, PNP_IO0_LOW_BYTE) + Store (IOHI, PNP_IO0_HIGH_BYTE) + Subtract (FindSetLeftBit (IRQW), 1, PNP_IRQ0) + Subtract (FindSetLeftBit (DMAC), 1, PNP_DMA0) + Store (One, PNP_DEVICE_ACTIVE) + EXIT_CONFIG_MODE() +} +} +#endif + +#undef SUPERIO_UART_PM_VAL +#undef SUPERIO_UART_PM_LDN +#undef SUPERIO_UART_DDN +#define SUPERIO_UART_PM_VAL 0 +#define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + +#ifdef WINBOND_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_PM_REG + #define SUPERIO_UART_LDN W83977TF_SP1 + #define SUPERIO_UART_PM_REG UAPW + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef WINBOND_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_PM_REG + #define SUPERIO_UART_LDN W83977TF_SP2 + #define SUPERIO_UART_PM_REG UBPW + #include <superio/acpi/pnp_uart.asl> +#endif + +/* TODO: IrDA device; + * '977EF=LDN 3 aka UARTB + * Some revisions of TF=LDN 6 + */ + +#define SUPERIO_KBC_LDN W83977TF_KBC +#define SUPERIO_KBC_PS2M /* Mouse shares same LDN */ +#undef SUPERIO_KBC_PS2LDN +#include <superio/acpi/pnp_kbc.asl> +/* +} +*/ -- To view, visit https://review.coreboot.org/21670 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If113807901619bc0f4250607546be415f9e5e45b Gerrit-Change-Number: 21670 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

1 0

Change in coreboot[master]: soraka: Update I2C5 bus tuning parameters
by Furquan Shaikh (Code Review) 25 Sep '17

25 Sep '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/21669 Change subject: soraka: Update I2C5 bus tuning parameters ...................................................................... soraka: Update I2C5 bus tuning parameters Update I2C5 bus parameters to obtain clock frequency <400kHz. BUG=b:65062416 TEST=Verified that I2C5 bus frequency in factory is ~397kHz. Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/soraka/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/21669/1 diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index fa16ae0..6d4e8a5 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -226,8 +226,8 @@ .speed = I2C_SPEED_FAST, .speed_config[0] = { .speed = I2C_SPEED_FAST, - .scl_lcnt = 180, - .scl_hcnt = 80, + .scl_lcnt = 195, + .scl_hcnt = 90, .sda_hold = 36, }, }" -- To view, visit https://review.coreboot.org/21669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517 Gerrit-Change-Number: 21669 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

1 0

Change in coreboot[master]: ec/hp/kbc1126/acpi/ec.asl: Name _Q04 event in ACPI debug message
by Iru Cai (Code Review) 25 Sep '17

25 Sep '17

Iru Cai has abandoned this change. ( https://review.coreboot.org/21667 ) Change subject: ec/hp/kbc1126/acpi/ec.asl: Name _Q04 event in ACPI debug message ...................................................................... Abandoned also found when just unplugging the AC without a dock, needs investigating later -- To view, visit https://review.coreboot.org/21667 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ifeecb1493d3cbcb26d786cbd18c90a520eee8ea4 Gerrit-Change-Number: 21667 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: ec/hp/kbc1126/acpi/battery.asl: \ISTR should be Serialized
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21668 ) Change subject: ec/hp/kbc1126/acpi/battery.asl: \ISTR should be Serialized ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61012/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16188/ : SUCCESS -- To view, visit https://review.coreboot.org/21668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I36e814acc0746cb011b595493d8254f3fb73baf5 Gerrit-Change-Number: 21668 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 02:49:10 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: ec/hp/kbc1126/acpi/ec.asl: Name _Q04 event in ACPI debug message
by build bot (Jenkins) (Code Review) 25 Sep '17

25 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21667 ) Change subject: ec/hp/kbc1126/acpi/ec.asl: Name _Q04 event in ACPI debug message ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61011/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16187/ : SUCCESS -- To view, visit https://review.coreboot.org/21667 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifeecb1493d3cbcb26d786cbd18c90a520eee8ea4 Gerrit-Change-Number: 21667 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Sep 2017 02:47:38 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: ec/hp/kbc1126/acpi/battery.asl: \ISTR should be Serialized
by Iru Cai (Code Review) 25 Sep '17

25 Sep '17

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/21668 Change subject: ec/hp/kbc1126/acpi/battery.asl: \ISTR should be Serialized ...................................................................... ec/hp/kbc1126/acpi/battery.asl: \ISTR should be Serialized Change-Id: I36e814acc0746cb011b595493d8254f3fb73baf5 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/ec/hp/kbc1126/acpi/battery.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21668/1 diff --git a/src/ec/hp/kbc1126/acpi/battery.asl b/src/ec/hp/kbc1126/acpi/battery.asl index a659cfa..0cc9854 100644 --- a/src/ec/hp/kbc1126/acpi/battery.asl +++ b/src/ec/hp/kbc1126/acpi/battery.asl @@ -235,7 +235,7 @@ 0x04B0 }) -Method (\ISTR, 2, NotSerialized) +Method (\ISTR, 2, Serialized) { Name (NUMB, Buffer (6) { " " }) Local0 = Arg0 -- To view, visit https://review.coreboot.org/21668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I36e814acc0746cb011b595493d8254f3fb73baf5 Gerrit-Change-Number: 21668 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com>

1 0

Change in coreboot[master]: ec/hp/kbc1126/acpi/ec.asl: Name _Q04 event in ACPI debug message
by Iru Cai (Code Review) 25 Sep '17

25 Sep '17

Iru Cai has uploaded this change for review. ( https://review.coreboot.org/21667 Change subject: ec/hp/kbc1126/acpi/ec.asl: Name _Q04 event in ACPI debug message ...................................................................... ec/hp/kbc1126/acpi/ec.asl: Name _Q04 event in ACPI debug message It's found in hp/8470p when unplug the laptop from the dock. Change-Id: Ifeecb1493d3cbcb26d786cbd18c90a520eee8ea4 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/ec/hp/kbc1126/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/21667/1 diff --git a/src/ec/hp/kbc1126/acpi/ec.asl b/src/ec/hp/kbc1126/acpi/ec.asl index 6e636ed3..aaff664 100644 --- a/src/ec/hp/kbc1126/acpi/ec.asl +++ b/src/ec/hp/kbc1126/acpi/ec.asl @@ -215,7 +215,7 @@ Method (_Q04, 0, NotSerialized) { - Store ("EC: _Q04", Debug) + Store ("EC: DOCK REMOVED", Debug) PNOT() } -- To view, visit https://review.coreboot.org/21667 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifeecb1493d3cbcb26d786cbd18c90a520eee8ea4 Gerrit-Change-Number: 21667 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com>

1 0

Change in coreboot[master]: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection
by Jonathan Neuschäfer (Code Review) 24 Sep '17

24 Sep '17

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/21587 ) Change subject: mb/lenovo/x2?0/devicetree: Fix regression of BDC detection ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/21587 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c Gerrit-Change-Number: 21587 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Sep 2017 20:47:04 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: console/init.c: Don't fetch console loglevel from cmos in romstage
by build bot (Jenkins) (Code Review) 24 Sep '17

24 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21658 ) Change subject: console/init.c: Don't fetch console loglevel from cmos in romstage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61000/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16178/ : SUCCESS -- To view, visit https://review.coreboot.org/21658 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2fbf9febd695b012b8b4f04019fba806ac3181cf Gerrit-Change-Number: 21658 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Sep 2017 09:39:36 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: console/init.c: Don't fetch console loglevel from cmos in romstage
by Arthur Heymans (Code Review) 24 Sep '17

24 Sep '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21658 Change subject: console/init.c: Don't fetch console loglevel from cmos in romstage ...................................................................... console/init.c: Don't fetch console loglevel from cmos in romstage Runtime console loglevel is not supported in romstage and the get_option function has printk() in it which should not be used before hardware is initialized. Change-Id: I2fbf9febd695b012b8b4f04019fba806ac3181cf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/console/init.c 1 file changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/21658/1 diff --git a/src/console/init.c b/src/console/init.c index c1565a4..be99565 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -39,21 +39,15 @@ return console_loglevel; } -static inline void set_log_level(int new_level) -{ - if (CONSOLE_LEVEL_CONST) - return; - - console_loglevel = new_level; -} - static void init_log_level(void) { int debug_level = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; - get_option(&debug_level, "debug_level"); + if (CONSOLE_LEVEL_CONST) + return; - set_log_level(debug_level); + get_option(&debug_level, "debug_level"); + console_loglevel = debug_level; } int console_log_level(int msg_level) -- To view, visit https://review.coreboot.org/21658 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2fbf9febd695b012b8b4f04019fba806ac3181cf Gerrit-Change-Number: 21658 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2017