coreboot-gerrit September 2017

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Change in coreboot[master]: soc/intel/cannonlake: Add config option of CpuRatio
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21709 ) Change subject: soc/intel/cannonlake: Add config option of CpuRatio ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61164/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16328/ : SUCCESS -- To view, visit https://review.coreboot.org/21709 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a1df15c619038f17c1bef5b7f53d322e352c56b Gerrit-Change-Number: 21709 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 22:28:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/amd/gardenia: Remove direct AGESA header includes
by Martin Roth (Code Review) 26 Sep '17

26 Sep '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21717 Change subject: mb/amd/gardenia: Remove direct AGESA header includes ...................................................................... mb/amd/gardenia: Remove direct AGESA header includes All AGESA headers should be included only through agesawrapper.h Change-Id: I3c9ae7a435fadabf577f1f65ad4a6aa6234e9a29 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/gardenia/OemCustomize.c M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c M src/mainboard/amd/gardenia/bootblock/OemCustomize.c 4 files changed, 2 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/21717/1 diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 1d06411..5a8eb19 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -13,9 +13,8 @@ * GNU General Public License for more details. */ -#include <AGESA.h> +#include <agesawrapper.h> #include <BiosCallOuts.h> -#include <FchPlatform.h> #include <soc/imc.h> #include <soc/southbridge.h> #include <stdlib.h> diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 8bd8e7c..1cee585 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include <AGESA.h> #include <agesawrapper.h> -#include <PlatformMemoryConfiguration.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c index b0a3e23..f084dfc 100644 --- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c @@ -13,9 +13,8 @@ * GNU General Public License for more details. */ -#include <AGESA.h> +#include <agesawrapper.h> #include <BiosCallOuts.h> -#include <FchPlatform.h> #include <soc/southbridge.h> #include <stdlib.h> diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c index 52148fd..8f61442 100644 --- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c +++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include <AGESA.h> #include <agesawrapper.h> -#include <PlatformMemoryConfiguration.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE -- To view, visit https://review.coreboot.org/21717 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3c9ae7a435fadabf577f1f65ad4a6aa6234e9a29 Gerrit-Change-Number: 21717 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Remove direct AGESA header includes
by Martin Roth (Code Review) 26 Sep '17

26 Sep '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21716 Change subject: soc/amd/stoneyridge: Remove direct AGESA header includes ...................................................................... soc/amd/stoneyridge: Remove direct AGESA header includes All AGESA headers should be included only through agesawrapper.h Change-Id: Iadc516e11148048ed9bf43c7a46827793245027a Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/stoneyridge/dimmSpd.c M src/soc/amd/stoneyridge/early_setup.c M src/soc/amd/stoneyridge/imc.c M src/soc/amd/stoneyridge/include/fchec.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/smbus_spd.c 6 files changed, 7 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/21716/1 diff --git a/src/soc/amd/stoneyridge/dimmSpd.c b/src/soc/amd/stoneyridge/dimmSpd.c index ace22bb..f306cf9 100644 --- a/src/soc/amd/stoneyridge/dimmSpd.c +++ b/src/soc/amd/stoneyridge/dimmSpd.c @@ -16,12 +16,8 @@ #include <device/pci_def.h> #include <device/device.h> #include <stdlib.h> - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> -#include <AGESA.h> -#include <amdlib.h> #include "chip.h" +#include <agesawrapper.h> #include <dimmSpd.h> AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index 5166a7f..cb4183c 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -23,7 +23,7 @@ #include <cbmem.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <Fch/Fch.h> +#include <agesawrapper.h> #include <cpu/x86/msr.h> #include <delay.h> diff --git a/src/soc/amd/stoneyridge/imc.c b/src/soc/amd/stoneyridge/imc.c index e7c6fac..d3dc496 100644 --- a/src/soc/amd/stoneyridge/imc.c +++ b/src/soc/amd/stoneyridge/imc.c @@ -19,12 +19,7 @@ #include <arch/io.h> #include <device/device.h> #include <delay.h> -#include <Porting.h> -#include <AGESA.h> -#include <Lib/amdlib.h> -#include <Proc/Fch/Common/FchCommonCfg.h> -#include <Proc/Fch/Fch.h> -#include <Proc/Fch/FchPlatform.h> +#include <agesawrapper.h> #define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE) diff --git a/src/soc/amd/stoneyridge/include/fchec.h b/src/soc/amd/stoneyridge/include/fchec.h index acbc138..3409be9 100644 --- a/src/soc/amd/stoneyridge/include/fchec.h +++ b/src/soc/amd/stoneyridge/include/fchec.h @@ -17,9 +17,7 @@ #define __AMD_STONEY_FCHEC__ #include <soc/imc.h> -#include "Porting.h" -#include "AGESA.h" -#include "FchCommonCfg.h" +#include <agesawrapper.h> extern VOID FchECfancontrolservice (IN VOID *FchDataPtr); void agesawrapper_fchecfancontrolservice(void); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 049bcd0..796a0c9 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -39,10 +39,7 @@ * AMD vendorcode files. Place at the end so coreboot defaults and maintained * and not set by vendorcode */ -#include <AGESA.h> -#include <FieldAccessors.h> -#include <Porting.h> -#include <Topology.h> +#include <agesawrapper.h> typedef struct dram_base_mask { u32 base; /* [47:27] at [28:8] */ @@ -532,7 +529,7 @@ } /* Get max and actual number of cores */ - pccount = cpuid_ecx(0x80000008); + pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT); core_max = 1 << ((pccount >> 12) & 0xf); core_nums = (pccount & 0xF); diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 6669ccb..9ec7040 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -16,9 +16,7 @@ #include <device/pci_def.h> #include <device/device.h> -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> -#include <AGESA.h> +#include <agesawrapper.h> #include <amdlib.h> #include <soc/southbridge.h> #include <dimmSpd.h> -- To view, visit https://review.coreboot.org/21716 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iadc516e11148048ed9bf43c7a46827793245027a Gerrit-Change-Number: 21716 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd/common: Remove direct AGESA header includes
by Martin Roth (Code Review) 26 Sep '17

26 Sep '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21715 Change subject: soc/amd/common: Remove direct AGESA header includes ...................................................................... soc/amd/common: Remove direct AGESA header includes All AGESA headers should be included only through agesawrapper.h Change-Id: I94140235f46a627dda99540af8619aeca3f4f157 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/BiosCallOuts.h M src/soc/amd/common/agesawrapper.c M src/soc/amd/common/agesawrapper_call.h M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/def_callouts.c M src/soc/amd/common/heapmanager.c 6 files changed, 5 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/21715/1 diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h index 4456466..4de1683 100644 --- a/src/soc/amd/common/BiosCallOuts.h +++ b/src/soc/amd/common/BiosCallOuts.h @@ -17,8 +17,7 @@ #ifndef __CALLOUTS_AMD_AGESA_H__ #define __CALLOUTS_AMD_AGESA_H__ -#include <Porting.h> -#include <AGESA.h> +#include <agesawrapper.h> #define BIOS_HEAP_START_ADDRESS 0x010000000 #define BIOS_HEAP_SIZE 0x30000 diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index b95d61a..f493971 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -13,13 +13,10 @@ * GNU General Public License for more details. */ -#include <AGESA.h> #include <cbfs.h> #include <cbmem.h> #include <delay.h> #include <cpu/x86/mtrr.h> -#include <FchPlatform.h> -#include <heapManager.h> #include <agesawrapper.h> #include <BiosCallOuts.h> diff --git a/src/soc/amd/common/agesawrapper_call.h b/src/soc/amd/common/agesawrapper_call.h index 21a1e23..d5b5a2c 100644 --- a/src/soc/amd/common/agesawrapper_call.h +++ b/src/soc/amd/common/agesawrapper_call.h @@ -16,7 +16,7 @@ #include <stdint.h> #include <console/console.h> -#include <AGESA.h> +#include <agesawrapper.h> /* * Possible AGESA_STATUS values: diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index 42b9fb7..63e64f8 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -18,8 +18,7 @@ #include <stdint.h> #include <compiler.h> -#include <Porting.h> -#include <Proc/Psp/PspBaseLib/PspBaseLib.h> +#include <agesawrapper.h> /* x86 to PSP commands */ #define MBOX_BIOS_CMD_DRAM_INFO 0x01 diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/def_callouts.c index fda0013..428d9dd 100644 --- a/src/soc/amd/common/def_callouts.c +++ b/src/soc/amd/common/def_callouts.c @@ -17,9 +17,6 @@ #include <cbfs.h> #include <spd_bin.h> -#include <AGESA.h> -#include <amdlib.h> -#include <Ids.h> #include <agesawrapper.h> #include <BiosCallOuts.h> #include <dimmSpd.h> diff --git a/src/soc/amd/common/heapmanager.c b/src/soc/amd/common/heapmanager.c index 6c240eb..2a52f6d 100644 --- a/src/soc/amd/common/heapmanager.c +++ b/src/soc/amd/common/heapmanager.c @@ -12,12 +12,11 @@ */ -#include <AGESA.h> +#include <agesawrapper.h> #include <amdlib.h> #include <arch/acpi.h> #include <BiosCallOuts.h> #include <cbmem.h> -#include <heapManager.h> #include <string.h> UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader) @@ -38,6 +37,7 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINTN Data, VOID *ConfigPtr) { + UINT32 AvailableHeapSize; UINT8 *BiosHeapBaseAddr; UINT32 CurrNodeOffset; -- To view, visit https://review.coreboot.org/21715 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I94140235f46a627dda99540af8619aeca3f4f157 Gerrit-Change-Number: 21715 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mb/google/kahlee: Remove direct AGESA header includes
by Martin Roth (Code Review) 26 Sep '17

26 Sep '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21714 Change subject: mb/google/kahlee: Remove direct AGESA header includes ...................................................................... mb/google/kahlee: Remove direct AGESA header includes All AGESA headers should be included only through agesawrapper.h Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/BiosCallOuts.c M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/bootblock/BiosCallOuts.c M src/mainboard/google/kahlee/bootblock/OemCustomize.c M src/mainboard/google/kahlee/gpio.c 5 files changed, 3 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21714/1 diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index f651876..b131e4c 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -13,9 +13,8 @@ * GNU General Public License for more details. */ -#include <AGESA.h> +#include <agesawrapper.h> #include <BiosCallOuts.h> -#include <FchPlatform.h> #include <soc/southbridge.h> #include <stdlib.h> diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 528c7b3..6ba94a4 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include <AGESA.h> #include <agesawrapper.h> -#include <PlatformMemoryConfiguration.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c index 162fc50..a659b1a 100644 --- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c @@ -13,9 +13,8 @@ * GNU General Public License for more details. */ -#include <AGESA.h> +#include <agesawrapper.h> #include <BiosCallOuts.h> -#include <FchPlatform.h> #include <soc/southbridge.h> #include <stdlib.h> diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/bootblock/OemCustomize.c index 38d08e5..adaee9c 100644 --- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c +++ b/src/mainboard/google/kahlee/bootblock/OemCustomize.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include <AGESA.h> #include <agesawrapper.h> -#include <PlatformMemoryConfiguration.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/google/kahlee/gpio.c b/src/mainboard/google/kahlee/gpio.c index b815ac3..9f1e2b3 100644 --- a/src/mainboard/google/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/gpio.c @@ -13,8 +13,7 @@ * GNU General Public License for more details. */ -#include <AGESA.h> -#include <FchPlatform.h> +#include <agesawrapper.h> #include <soc/southbridge.h> #include <stdlib.h> -- To view, visit https://review.coreboot.org/21714 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a Gerrit-Change-Number: 21714 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: amd pi: Add agesa_headers.h for all PIs
by Martin Roth (Code Review) 26 Sep '17

26 Sep '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21713 Change subject: amd pi: Add agesa_headers.h for all PIs ...................................................................... amd pi: Add agesa_headers.h for all PIs - Create header files for each PI that pull in all AGESA pi headers. - Add that header to agesawrapper.h and enclose it in #pragma pack push and pop to keep the '#pragma pack(1)' in Porting.h from leaking. Following patches will update the coreboot code to use only agesawrapper.h to pull in the AGESA headers. Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/agesawrapper.h A src/vendorcode/amd/pi/00630F01/agesa_headers.h A src/vendorcode/amd/pi/00660F01/agesa_headers.h A src/vendorcode/amd/pi/00670F00/agesa_headers.h A src/vendorcode/amd/pi/00730F01/agesa_headers.h 5 files changed, 205 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/21713/1 diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h index b42f531..d9b4c65 100644 --- a/src/soc/amd/common/agesawrapper.h +++ b/src/soc/amd/common/agesawrapper.h @@ -17,8 +17,10 @@ #define __AGESAWRAPPER_H__ #include <stdint.h> +#pragma pack(push) #include <Porting.h> -#include <AGESA.h> +#include <agesa_headers.h> +#pragma pack(pop) enum { PICK_DMI, /* DMI Interface */ diff --git a/src/vendorcode/amd/pi/00630F01/agesa_headers.h b/src/vendorcode/amd/pi/00630F01/agesa_headers.h new file mode 100644 index 0000000..62a68d9 --- /dev/null +++ b/src/vendorcode/amd/pi/00630F01/agesa_headers.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AGESA_HEADERS_H__ +#define __AGESA_HEADERS_H__ + +#include "AMD.h" +#include "AGESA.h" +#include "Proc/Fch/Common/FchCommonCfg.h" + +#include "binaryPI/FieldAccessors.h" +#include "Dispatcher.h" +#include "Include/Filecode.h" +#include "Include/Ids.h" +#include "Include/IdsPerf.h" +#include "Include/Options.h" +#include "Include/PlatformMemoryConfiguration.h" +#include "Include/Topology.h" +#include "Proc/Common/AmdFch.h" +#include "Proc/CPU/cpuApicUtilities.h" +#include "Proc/CPU/cpuEarlyInit.h" +#include "Proc/CPU/cpuLateInit.h" +#include "Proc/CPU/cpuRegisters.h" +#include "Proc/CPU/Family/cpuFamRegisters.h" +#include "Proc/CPU/Feature/cpuCacheInit.h" +#include "Proc/CPU/heapManager.h" +#include "Proc/Fch/Common/AcpiLib.h" +#include "Proc/Fch/Common/FchBiosRamUsage.h" +#include "Proc/Fch/Common/FchDef.h" +#include "Proc/Fch/Fch.h" +#include "Proc/Fch/FchPlatform.h" +#include "Proc/IDS/Debug/IdsDebugPrint.h" +#include "Proc/IDS/Debug/IdsDpHdtout.h" +#include "Proc/IDS/Debug/IdsDpRam.h" +#include "Proc/IDS/Family/0x15/IdsF15AllService.h" +#include "Proc/IDS/Family/0x15/KV/IdsF15KvAllService.h" +#include "Proc/IDS/Family/0x15/KV/IdsF15KvNvDef.h" +#include "Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h" +#include "Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h" +#include "Proc/IDS/IdsLib.h" +#include "Proc/IDS/OptionsIds.h" + +#endif /* __AGESA_HEADERS_H__ */ diff --git a/src/vendorcode/amd/pi/00660F01/agesa_headers.h b/src/vendorcode/amd/pi/00660F01/agesa_headers.h new file mode 100644 index 0000000..e0f6ad9 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/agesa_headers.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AGESA_HEADERS_H__ +#define __AGESA_HEADERS_H__ + +#include "AMD.h" +#include "AGESA.h" +#include "Proc/Fch/Common/FchCommonCfg.h" + +#include "binaryPI/FieldAccessors.h" +#include "binaryPI/OptionsIds.h" +#include "Dispatcher.h" +#include "Include/Filecode.h" +#include "Include/GeneralServices.h" +#include "Include/Ids.h" +#include "Include/IdsPerf.h" +#include "Include/Options.h" +#include "Include/PlatformMemoryConfiguration.h" +#include "Include/Topology.h" +#include "Proc/Common/AmdFch.h" +#include "Proc/CPU/cpuEarlyInit.h" +#include "Proc/CPU/cpuLateInit.h" +#include "Proc/CPU/cpuRegisters.h" +#include "Proc/CPU/Family/cpuFamRegisters.h" +#include "Proc/CPU/Feature/cpuCacheInit.h" +#include "Proc/CPU/heapManager.h" +#include "Proc/Fch/Common/AcpiLib.h" +#include "Proc/Fch/Common/FchBiosRamUsage.h" +#include "Proc/Fch/Common/FchDef.h" +#include "Proc/Fch/Fch.h" +#include "Proc/Fch/FchPlatform.h" +#include "Proc/Fch/Kern/KernFch.h" +#include "Proc/Psp/PspBaseLib/PspBaseLib.h" +#include "Proc/Psp/PspBaseLib/PspDirectory.h" + +#endif /* __AGESA_HEADERS_H__ */ diff --git a/src/vendorcode/amd/pi/00670F00/agesa_headers.h b/src/vendorcode/amd/pi/00670F00/agesa_headers.h new file mode 100644 index 0000000..8c74dca --- /dev/null +++ b/src/vendorcode/amd/pi/00670F00/agesa_headers.h @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AGESA_HEADERS_H__ +#define __AGESA_HEADERS_H__ + +#include "AMD.h" +#include "AGESA.h" +#include "Proc/CPU/cpuRegisters.h" +#include "Proc/Fch/Common/FchCommonCfg.h" + +#include "binaryPI/FieldAccessors.h" +#include "binaryPI/OptionsIds.h" +#include "Dispatcher.h" +#include "Include/Filecode.h" +#include "Include/GeneralServices.h" +#include "Include/Ids.h" +#include "Include/IdsPerf.h" +#include "Include/Options.h" +#include "Include/PlatformMemoryConfiguration.h" +#include "Include/Topology.h" +#include "Proc/Common/AmdFch.h" +#include "Proc/CPU/cpuEarlyInit.h" +#include "Proc/CPU/cpuFamilyTranslation.h" +#include "Proc/CPU/cpuLateInit.h" +#include "Proc/CPU/cpuServices.h" +#include "Proc/CPU/Family/cpuFamRegisters.h" +#include "Proc/CPU/Feature/cpuCacheInit.h" +#include "Proc/CPU/heapManager.h" +#include "Proc/CPU/Table.h" +#include "Proc/Fch/Common/AcpiLib.h" +#include "Proc/Fch/Common/FchBiosRamUsage.h" +#include "Proc/Fch/Common/FchDef.h" +#include "Proc/Fch/Fch.h" +#include "Proc/Fch/FchPlatform.h" +#include "Proc/Fch/Kern/KernFch.h" +#include "Proc/Psp/PspBaseLib/PspBaseLib.h" +#include "Proc/Psp/PspBaseLib/PspDirectory.h" + +#endif /* __AGESA_HEADERS_H__ */ diff --git a/src/vendorcode/amd/pi/00730F01/agesa_headers.h b/src/vendorcode/amd/pi/00730F01/agesa_headers.h new file mode 100644 index 0000000..607d7e2 --- /dev/null +++ b/src/vendorcode/amd/pi/00730F01/agesa_headers.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AGESA_HEADERS_H__ +#define __AGESA_HEADERS_H__ + +#include "AMD.h" +#include "AGESA.h" +#include "Proc/Fch/Common/FchCommonCfg.h" + +#include "Proc/Common/AmdFch.h" +#include "Proc/Fch/Common/AcpiLib.h" +#include "Proc/Fch/Common/FchDef.h" +#include "Proc/Fch/Common/FchBiosRamUsage.h" +#include "Proc/Fch/Fch.h" +#include "Proc/Fch/FchPlatform.h" +#include "Proc/CPU/cpuApicUtilities.h" +#include "Proc/CPU/cpuRegisters.h" +#include "Proc/CPU/heapManager.h" +#include "Proc/CPU/cpuEarlyInit.h" +#include "Proc/CPU/Feature/cpuCacheInit.h" +#include "Proc/CPU/cpuLateInit.h" +#include "Proc/CPU/Family/cpuFamRegisters.h" +#include "binaryPI/FieldAccessors.h" +#include "binaryPI/OptionsIds.h" +#include "Dispatcher.h" +#include "Include/PlatformMemoryConfiguration.h" +#include "Include/Ids.h" +#include "Include/IdsPerf.h" +#include "Include/Options.h" +#include "Include/Topology.h" +#include "Include/Filecode.h" + +#endif /* __AGESA_HEADERS_H__ */ -- To view, visit https://review.coreboot.org/21713 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4 Gerrit-Change-Number: 21713 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: Fizz: Continue booting with EC in RW for EC-EFS
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21711 ) Change subject: Fizz: Continue booting with EC in RW for EC-EFS ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61163/ : SUCCESS -- To view, visit https://review.coreboot.org/21711 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Gerrit-Change-Number: 21711 Gerrit-PatchSet: 3 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 22:22:28 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: Fizz: Continue booting with EC in RW for EC-EFS
by Daisuke Nojiri (Code Review) 26 Sep '17

26 Sep '17

Hello Julius Werner, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21711 to look at the new patch set (#3). Change subject: Fizz: Continue booting with EC in RW for EC-EFS ...................................................................... Fizz: Continue booting with EC in RW for EC-EFS If EC does EFS, it jumps to RW in all cases except when recovery is requested manually. This patch makes coreboot on EC-EFS systems check whether EC is running in RO or not only when recovery is requested manually. BUG=b:66516882 BRANCH=none TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/vboot/bootmode.c M src/vboot/vboot_common.h 3 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/21711/3 -- To view, visit https://review.coreboot.org/21711 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Gerrit-Change-Number: 21711 Gerrit-PatchSet: 3 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: Fizz: Continue booting with EC in RW for EC-EFS
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21711 ) Change subject: Fizz: Continue booting with EC in RW for EC-EFS ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/61162/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/16327/ : SUCCESS -- To view, visit https://review.coreboot.org/21711 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Gerrit-Change-Number: 21711 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 22:12:19 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: Fizz: Continue booting with EC in RW for EC-EFS
by Daisuke Nojiri (Code Review) 26 Sep '17

26 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21711 to look at the new patch set (#2). Change subject: Fizz: Continue booting with EC in RW for EC-EFS ...................................................................... Fizz: Continue booting with EC in RW for EC-EFS If EC does EFS, it jumps to RW in all cases except when recovery is requested manually. This patch makes Coreboot on EC-EFS systems check whether EC is running in RO or not only when recovery is requested manually. BUG=b:66516882 BRANCH=none TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/ec.c M src/vboot/bootmode.c M src/vboot/vboot_common.h 3 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/21711/2 -- To view, visit https://review.coreboot.org/21711 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Gerrit-Change-Number: 21711 Gerrit-PatchSet: 2 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2017