coreboot-gerrit August 2017

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Change in coreboot[master]: arch/x86/Kconfig: Add deprecation warning to LATE_CBMEM_INIT's help text
by build bot (Jenkins) (Code Review) 20 Aug '17

20 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21112 ) Change subject: arch/x86/Kconfig: Add deprecation warning to LATE_CBMEM_INIT's help text ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58933/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/14287/ : SUCCESS -- To view, visit https://review.coreboot.org/21112 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Gerrit-Change-Number: 21112 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 23:03:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: arch/x86/Kconfig: Add deprecation warning to LATE_CBMEM_INIT's help text
by Jonathan Neuschäfer (Code Review) 20 Aug '17

20 Aug '17

Jonathan Neuschäfer has uploaded a new patch set (#2). ( https://review.coreboot.org/21112 ) Change subject: arch/x86/Kconfig: Add deprecation warning to LATE_CBMEM_INIT's help text ...................................................................... arch/x86/Kconfig: Add deprecation warning to LATE_CBMEM_INIT's help text The deprecation of late (post-romstage) CBMEM initialization was announced in this blog post: https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/ Arguably, extending the help text of CONFIG_LATE_CBMEM_INIT isn't very useful because neither menuconfig nor nconfig show it for options without a prompt. Therefore, I added warning to the mainboard menu. Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/x86/Kconfig M src/mainboard/Kconfig 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/21112/2 -- To view, visit https://review.coreboot.org/21112 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Gerrit-Change-Number: 21112 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: arch/x86/Kconfig: Add warning to config LATE_CBMEM_INIT help text
by Jonathan Neuschäfer (Code Review) 20 Aug '17

20 Aug '17

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/21112 Change subject: arch/x86/Kconfig: Add warning to config LATE_CBMEM_INIT help text ...................................................................... arch/x86/Kconfig: Add warning to config LATE_CBMEM_INIT help text The deprecation of late (post-romstage) CBMEM initialization was announced in this blog post: https://blogs.coreboot.org/blog/2017/05/08/announcing-coreboot-4-6/ Arguably, extending the help text of CONFIG_LATE_CBMEM_INIT isn't very useful because neither menuconfig nor nconfig show it for options without a prompt. Therefore, I added warning to the mainboard menu. Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/arch/x86/Kconfig M src/mainboard/Kconfig 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/21112/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e18d6d0..418448d 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -125,6 +125,10 @@ early get_top_of_ram() call for romstage. CBMEM tables will be allocated late in ramstage, after PCI devices resources are known. + WARNING: Late CBMEM initialization is deprecated. Platforms that + don't support early CBMEM initialization will be removed after + the release of coreboot 4.7. + config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xc00 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index bdaa9e7..47338ac 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -10,6 +10,9 @@ source "src/mainboard/*/Kconfig" +comment "WARNING: This mainboard uses LATE_CBMEM_INIT, which is deprecated" + depends on LATE_CBMEM_INIT + config BOARD_ROMSIZE_KB_64 bool config BOARD_ROMSIZE_KB_128 -- To view, visit https://review.coreboot.org/21112 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2d21a6ab2fc2811d44fc4febb05841bb2f8d1857 Gerrit-Change-Number: 21112 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: sb/nvidia/mcp55: Link early_setup_car.c
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21110 ) Change subject: sb/nvidia/mcp55: Link early_setup_car.c ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58928/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14282/ : SUCCESS -- To view, visit https://review.coreboot.org/21110 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I99170936b8a9851ca088a190b002da9de8ba6022 Gerrit-Change-Number: 21110 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 19:18:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/amd/amdk8: Link early_ht.c
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21111 ) Change subject: nb/amd/amdk8: Link early_ht.c ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58929/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14283/ : SUCCESS -- To view, visit https://review.coreboot.org/21111 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia47f2466c8d6583a9bb668cc35e91f45765c8238 Gerrit-Change-Number: 21111 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 19:01:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/amd/amdk8: Link early_ht.c
by Arthur Heymans (Code Review) 19 Aug '17

19 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21111 Change subject: nb/amd/amdk8: Link early_ht.c ...................................................................... nb/amd/amdk8: Link early_ht.c Change-Id: Ia47f2466c8d6583a9bb668cc35e91f45765c8238 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/amd/dbm690t/romstage.c M src/mainboard/amd/mahogany/romstage.c M src/mainboard/amd/pistachio/romstage.c M src/mainboard/asrock/939a785gmh/romstage.c M src/mainboard/asus/a8n_e/romstage.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/kfsn4-dre_k8/romstage.c M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/broadcom/blast/romstage.c M src/mainboard/gigabyte/ga_2761gxdk/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/hp/dl145_g3/romstage.c M src/mainboard/kontron/kt690/romstage.c M src/mainboard/msi/ms7135/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9185/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/siemens/sitemp_g1p1/romstage.c M src/mainboard/sunw/ultra40/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/technexion/tim5690/romstage.c M src/mainboard/technexion/tim8690/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/winent/mb6047/romstage.c M src/northbridge/amd/amdk8/Makefile.inc M src/northbridge/amd/amdk8/amdk8.h M src/northbridge/amd/amdk8/early_ht.c 32 files changed, 9 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/21111/1 diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index c8c8c40..4146197 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -51,7 +51,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index a723ee7..960df43 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -54,7 +54,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 052b71f..4e9c6ad 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -47,7 +47,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 21324e7..9607394 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -57,7 +57,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_init(void) { diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 20c57c1..44c080e 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -57,7 +57,6 @@ #include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 88a05f4..5d9856b 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <southbridge/via/vt8237r/vt8237r.h> diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 3628d07..c9e9552 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <southbridge/via/vt8237r/vt8237r.h> diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 83bf27b..de55231 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -33,7 +33,6 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83697hf/w83697hf.h> #include <southbridge/via/vt8237r/vt8237r.h> diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index f646c2b..d287bd6 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -59,7 +59,6 @@ #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" #define CK804_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/ diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 88b817d..e298c10 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -69,7 +69,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c" /* FIXME * Dummy method to allow build diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index d4cf882..cc42f0e 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -44,7 +44,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c" #define RC0 (6 << 8) #define RC1 (7 << 8) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index d56de52..f7871cb 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -74,7 +74,6 @@ #include <southbridge/sis/sis966/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 0acb9c2..428fa9d 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -75,7 +75,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index ce9d5ac..9fa5418 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -70,7 +70,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" #if 0 #include "ipmi.c" diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index ae5970e..89e998e 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -52,7 +52,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 7d8007c..3ba1a90 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -60,7 +60,6 @@ #include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c" static void ms7135_set_ram_voltage(void) { diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 3402b81..b7aaa6d 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -78,7 +78,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 33dc288..23f0275 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -69,7 +69,6 @@ #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" #define RC0 (0x10 << 8) #define RC1 (0x01 << 8) diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index f8e7e4b..ed4aecc 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -85,7 +85,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c" /* FIXME * Dummy method to allow build diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index a1665f8..c2c8049 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -77,7 +77,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index dec5c68..692e7dc 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -67,7 +67,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" #define __WARNING__(fmt, arg...) do_printk(BIOS_WARNING ,fmt, ##arg) #define __DEBUG__(fmt, arg...) do_printk(BIOS_DEBUG ,fmt, ##arg) diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 8a9d81e..b0b02c3 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -63,7 +63,6 @@ #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 589cee1..275c6cc 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -74,7 +74,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index edf717c..453a2d2 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -77,7 +77,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 9cd3311..f00f996 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -69,7 +69,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 520247e..84b52cd 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -54,7 +54,6 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "tn_post_code.c" #include "speaker.c" -#include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 1bb4a7f..01a0a11 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -53,7 +53,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index fb89141..d15732a 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -77,7 +77,6 @@ #include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index ac4c3b4..fd4ae5f 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -40,7 +40,6 @@ #if IS_ENABLED(CONFIG_SET_FIDVID) #include "cpu/amd/model_fxx/fidvid.c" #endif -#include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) { diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index 77bf375..ed55a7e 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += reset_test.c romstage-y += coherent_ht.c romstage-y += setup_resource_map.c +romstage-y += early_ht.c # Enable this if you want to check the values of the PCI routing registers. # Call show_all_routes() anywhere amdk8.h is included. diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index b183976..63c4e47 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -33,6 +33,7 @@ void setup_resource_map_x_offset(const unsigned int *register_values, int max, unsigned int offset_pci_dev, unsigned int offset_io_base); +void enumerate_ht_chain(void); #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void setup_coherent_ht_domain(void); diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 638511a..269bb77 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -2,7 +2,13 @@ 2005.11 yhlu add let the real sb to use small unitid */ // only for sb ht chain -static void enumerate_ht_chain(void) + +#include <arch/io.h> +#include <console/console.h> + +#include "amdk8.h" + +void enumerate_ht_chain(void) { #if CONFIG_HT_CHAIN_UNITID_BASE != 0 /* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ -- To view, visit https://review.coreboot.org/21111 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia47f2466c8d6583a9bb668cc35e91f45765c8238 Gerrit-Change-Number: 21111 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: nb/amd/amdk8: Link early_setup_car.c
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21109 ) Change subject: nb/amd/amdk8: Link early_setup_car.c ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58927/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14281/ : SUCCESS -- To view, visit https://review.coreboot.org/21109 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd2740ccf0b63fd73e3fcb08ed7377963b93a9bd Gerrit-Change-Number: 21109 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 18:54:12 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: sb/nvidia/mcp55: Link early_setup_car.c
by Arthur Heymans (Code Review) 19 Aug '17

19 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21110 Change subject: sb/nvidia/mcp55: Link early_setup_car.c ...................................................................... sb/nvidia/mcp55: Link early_setup_car.c Change-Id: I99170936b8a9851ca088a190b002da9de8ba6022 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/southbridge/nvidia/mcp55/Makefile.inc M src/southbridge/nvidia/mcp55/early_setup_car.c M src/southbridge/nvidia/mcp55/mcp55.h 16 files changed, 9 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/21110/1 diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 2ca0fbc..88b817d 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -68,7 +68,6 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 12939ca..0acb9c2 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -68,7 +68,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 0569365..3402b81 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -76,7 +76,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 2334c11..f8e7e4b 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -84,7 +84,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 11e9bc0..7ec5bb0 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -79,7 +79,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" static void sio_setup(void) { diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 3aa261b..a1665f8 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -75,7 +75,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 1dd09f6..589cee1 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -72,7 +72,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+61, 0x00, 0x05,/* GPIO62: enable/not-disable on-board TSB43AB22A Firewire */ #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 0255242..edf717c 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -75,7 +75,6 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index a57be62..9cd3311 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -67,7 +67,6 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index e100876..c4be7e4 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -47,7 +47,6 @@ #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 3554a05..86077c7 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -46,7 +46,6 @@ #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index c4804c5..fb89141 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -75,7 +75,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index b449f77..bec9741 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -68,7 +68,6 @@ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ #include <southbridge/nvidia/mcp55/early_setup_ss.h> -#include "southbridge/nvidia/mcp55/early_setup_car.c" unsigned get_sbdn(unsigned bus) { diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 7073b69..33d6106 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -21,6 +21,7 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c romstage-y += early_ctrl.c +romstage-y += early_setup_car.c ifeq ($(CONFIG_MCP55_USE_AZA),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 44a330c..8095a98 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -15,9 +15,15 @@ * GNU General Public License for more details. */ +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <delay.h> #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8) #include <northbridge/amd/amdk8/amdk8.h> #endif + +#include "mcp55.h" #ifdef UNUSED_CODE int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); @@ -339,7 +345,7 @@ #endif -static int mcp55_early_setup_x(void) +int mcp55_early_setup_x(void) { /* Find out how many MCP55 we have. */ unsigned busn[HT_CHAIN_NUM_MAX] = {0}; diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h index a244b82..67bc1db 100644 --- a/src/southbridge/nvidia/mcp55/mcp55.h +++ b/src/southbridge/nvidia/mcp55/mcp55.h @@ -40,6 +40,7 @@ int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address); int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val); +int mcp55_early_setup_x(void); #endif #endif -- To view, visit https://review.coreboot.org/21110 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I99170936b8a9851ca088a190b002da9de8ba6022 Gerrit-Change-Number: 21110 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: nb/amd/amdk8: Link early_setup_car.c
by Arthur Heymans (Code Review) 19 Aug '17

19 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21109 Change subject: nb/amd/amdk8: Link early_setup_car.c ...................................................................... nb/amd/amdk8: Link early_setup_car.c Change-Id: Ifd2740ccf0b63fd73e3fcb08ed7377963b93a9bd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/amd/dbm690t/romstage.c M src/mainboard/amd/mahogany/romstage.c M src/mainboard/amd/pistachio/romstage.c M src/mainboard/amd/serengeti_cheetah/romstage.c M src/mainboard/asrock/939a785gmh/romstage.c M src/mainboard/asus/a8n_e/romstage.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/kfsn4-dre_k8/romstage.c M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/asus/m2v-mx_se/romstage.c M src/mainboard/asus/m2v/romstage.c M src/mainboard/broadcom/blast/romstage.c M src/mainboard/gigabyte/ga_2761gxdk/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/hp/dl145_g3/romstage.c M src/mainboard/iwill/dk8_htx/romstage.c M src/mainboard/kontron/kt690/romstage.c M src/mainboard/msi/ms7135/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9185/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/siemens/sitemp_g1p1/romstage.c M src/mainboard/sunw/ultra40/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/technexion/tim5690/romstage.c M src/mainboard/technexion/tim8690/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/winent/mb6047/romstage.c M src/northbridge/amd/amdk8/Makefile.inc M src/northbridge/amd/amdk8/amdk8.h M src/northbridge/amd/amdk8/setup_resource_map.c M src/southbridge/nvidia/mcp55/early_setup_car.c 37 files changed, 34 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/21109/1 diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index faf3ef5..c8c8c40 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -30,7 +30,6 @@ #include <spd.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index c194996..a723ee7 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -30,7 +30,6 @@ #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 38b3003..052b71f 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -28,7 +28,6 @@ #include <spd.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index aaec8c7..be53cbb 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -30,7 +30,6 @@ #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 6343f10..21324e7 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -31,7 +31,6 @@ #include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <northbridge/amd/amdk8/pre_f.h> diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index ec66a5a..20c57c1 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -40,7 +40,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 87fec55..88a05f4 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -39,7 +39,7 @@ #include <southbridge/via/vt8237r/vt8237r.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" + #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index adcf381..3628d07 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -39,7 +39,6 @@ #include <southbridge/via/vt8237r/vt8237r.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 15c8f2e..83bf27b 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -39,7 +39,6 @@ #include <southbridge/via/vt8237r/vt8237r.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index 687dd6b..f646c2b 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -40,7 +40,6 @@ #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index cf1a0cd..2ca0fbc 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,7 +37,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 3267369..f54d599 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -39,7 +39,6 @@ #include <southbridge/via/vt8237r/vt8237r.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 0e822e8..563206e 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -39,7 +39,6 @@ #include <southbridge/via/vt8237r/vt8237r.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 10efb7b..d4cf882 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -16,7 +16,6 @@ #include <superio/nsc/pc87417/pc87417.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/pre_f.h> #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index d787580..d56de52 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -38,7 +38,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 4944bf6..12939ca 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -34,7 +34,6 @@ #include <superio/ite/it8716f/it8716f.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 9a8ef89..ce9d5ac 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -40,7 +40,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 683d773..34a8924 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -15,7 +15,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/pre_f.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index d2f6299..ae5970e 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -33,7 +33,6 @@ #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 57b0acb..7d8007c 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -37,7 +37,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include <northbridge/amd/amdk8/pre_f.h> diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 878a79e..0569365 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -37,7 +37,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 3d937f7..33dc288 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -38,7 +38,6 @@ #include <superio/nsc/pc87417/pc87417.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 3bfb9da..2334c11 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -37,7 +37,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> #include <spd.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <device/pci_ids.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d8076f0..3aa261b 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -36,7 +36,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 90f8084..dec5c68 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -36,7 +36,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index c11ffe7..8a9d81e 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -19,7 +19,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> #include "superio/smsc/lpc47b397/early_gpio.c" -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/pre_f.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 48c7963..1dd09f6 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -35,7 +35,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 17df141..0255242 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -33,7 +33,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index c71eaa1..a57be62 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -36,7 +36,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 64b1e27..520247e 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -31,7 +31,6 @@ #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 05e00e0..1bb4a7f 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -31,7 +31,6 @@ #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" #include <northbridge/amd/amdk8/f.h> diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 882d90d..c4804c5 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -36,7 +36,6 @@ #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 3271f74..ac4c3b4 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -18,7 +18,6 @@ #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/pre_f.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index 263e06f..77bf375 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -13,6 +13,7 @@ romstage-y += reset_test.c romstage-y += coherent_ht.c +romstage-y += setup_resource_map.c # Enable this if you want to check the values of the PCI routing registers. # Call show_all_routes() anywhere amdk8.h is included. diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 65b6fb6..b183976 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -19,6 +19,10 @@ #define NODE_MP(x) PCI_DEV(0,24+x,1) #define NODE_MC(x) PCI_DEV(0,24+x,3) +#define RES_PCI_IO 0x10 +#define RES_PORT_IO_8 0x22 +#define RES_PORT_IO_32 0x20 +#define RES_MEM_IO 0x40 #ifdef __PRE_RAM__ void showallroutes(int level, pci_devfn_t dev); @@ -26,6 +30,10 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); int optimize_link_coherent_ht(void); unsigned int get_nodes(void); +void setup_resource_map_x_offset(const unsigned int *register_values, int max, + unsigned int offset_pci_dev, + unsigned int offset_io_base); + #if IS_ENABLED(CONFIG_RAMINIT_SYSINFO) void setup_coherent_ht_domain(void); #else diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index 38f8fdd..31408f1 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -1,3 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> + #include "amdk8.h" #define RES_DEBUG 0 @@ -28,12 +45,9 @@ #endif } -#define RES_PCI_IO 0x10 -#define RES_PORT_IO_8 0x22 -#define RES_PORT_IO_32 0x20 -#define RES_MEM_IO 0x40 - -static void setup_resource_map_x_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) +void setup_resource_map_x_offset(const unsigned int *register_values, int max, + unsigned int offset_pci_dev, + unsigned int offset_io_base) { int i; diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 8019a8e..44a330c 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -15,6 +15,10 @@ * GNU General Public License for more details. */ +#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8) +#include <northbridge/amd/amdk8/amdk8.h> +#endif + #ifdef UNUSED_CODE int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); -- To view, visit https://review.coreboot.org/21109 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd2740ccf0b63fd73e3fcb08ed7377963b93a9bd Gerrit-Change-Number: 21109 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: util/inteltool: Remove doubled error message, switch to snprintf
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21025 ) Change subject: util/inteltool: Remove doubled error message, switch to snprintf ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58926/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14280/ : SUCCESS -- To view, visit https://review.coreboot.org/21025 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ccc37e404f278cafae0a451c5acaa27d7907cce Gerrit-Change-Number: 21025 Gerrit-PatchSet: 3 Gerrit-Owner: Maciej Sumi?ski <maciej.suminski(a)cern.ch> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 18:18:19 +0000 Gerrit-HasComments: No

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