coreboot-gerrit August 2017

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Change in coreboot[master]: mainboard/google/poppy: Update VR config settings
by Furquan Shaikh (Code Review) 19 Aug '17

19 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/21105 Change subject: mainboard/google/poppy: Update VR config settings ...................................................................... mainboard/google/poppy: Update VR config settings Update Psi2Threshold, IccMax, ACLoadline and DCLoadline VR config settings to match that of soraka. BUG=b:62063434 BRANCH=None TEST=Build and boot poppy. Change-Id: I2c294eb14257d319e1e2d4d1e529481d921ba6f8 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/baseboard/devicetree.cb 1 file changed, 20 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/21105/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 9d5b5b0..d67c9c0 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -75,65 +75,75 @@ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | - #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 35A | 35A | + #| IccMax | 5A | 24A | 24A | 24A | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AcLoadline | 15 | 5.7 | 5.5 | 5.5 | + #| DcLoadline | 14.3 | 4.83 | 4.2 | 4.2 | #+----------------+-------+-------+-------+-------+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(4), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(7), + .icc_max = VR_CFG_AMP(5), .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, }" register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(34), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, }" register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 550, + .dc_loadline = 420, }" register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, .psi1threshold = VR_CFG_AMP(20), - .psi2threshold = VR_CFG_AMP(5), + .psi2threshold = VR_CFG_AMP(2), .psi3threshold = VR_CFG_AMP(1), .psi3enable = 1, .psi4enable = 1, .imon_slope = 0x0, .imon_offset = 0x0, - .icc_max = VR_CFG_AMP(35), + .icc_max = VR_CFG_AMP(24), .voltage_limit = 1520, + .ac_loadline = 550, + .dc_loadline = 420, }" # Enable Root port 1. -- To view, visit https://review.coreboot.org/21105 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2c294eb14257d319e1e2d4d1e529481d921ba6f8 Gerrit-Change-Number: 21105 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mainboard/google/poppy: Remove MPS IMPV8 workaround
by Furquan Shaikh (Code Review) 19 Aug '17

19 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/21104 Change subject: mainboard/google/poppy: Remove MPS IMPV8 workaround ...................................................................... mainboard/google/poppy: Remove MPS IMPV8 workaround Poppy uses MPS2949 IMVP8 controller and does not need the VR workaroud similar to Eve. Change-Id: If6fb1890e024e1488d278bbe0a71a1a63ee321af Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/baseboard/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/21104/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index f10db59..9d5b5b0 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -60,7 +60,6 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" - register "SendVrMbxCmd" = "1" # IMVP8 workaround register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" -- To view, visit https://review.coreboot.org/21104 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If6fb1890e024e1488d278bbe0a71a1a63ee321af Gerrit-Change-Number: 21104 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS
by Raptor Engineering Automated Test Stand (Code Review) 19 Aug '17

19 Aug '17

Raptor Engineering Automated Test Stand has posted comments on this change. ( https://review.coreboot.org/20970 ) Change subject: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS ...................................................................... Patch Set 4: Verified-1 ASUS KFSN4-DRE: Boot and extended test successful. Boot log: https://testlab.coreboot.org/raptor/1503097564-0-20970,4.log.bz2 QEMU x86_64 Q35: Boot successful. Boot log: https://testlab.coreboot.org/raptor/1503097633-1-20970,4.log.bz2 ASUS KGPE-D16: Test FAILED. Boot log: https://testlab.coreboot.org/raptor/1503100415-3-20970,4.log.bz2 ASUS KGPE-D16: BOOT_FAILURE -- To view, visit https://review.coreboot.org/20970 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iebe8aa1c4c3019414c6a23404cc5dc7f668cd8eb Gerrit-Change-Number: 20970 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 23:53:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/amd/mct_ddr3/mct_d.c: Break out of allow_config_restore loop
by Raptor Engineering Automated Test Stand (Code Review) 19 Aug '17

19 Aug '17

Raptor Engineering Automated Test Stand has posted comments on this change. ( https://review.coreboot.org/20971 ) Change subject: nb/amd/mct_ddr3/mct_d.c: Break out of allow_config_restore loop ...................................................................... Patch Set 3: Verified-1 ASUS KFSN4-DRE: Boot and extended test successful. Boot log: https://testlab.coreboot.org/raptor/1503095818-0-20971,3.log.bz2 QEMU x86_64 Q35: Boot successful. Boot log: https://testlab.coreboot.org/raptor/1503095501-1-20971,3.log.bz2 ASUS KGPE-D16: Test FAILED. Boot log: https://testlab.coreboot.org/raptor/1503097114-3-20971,3.log.bz2 ASUS KGPE-D16: BOOT_FAILURE -- To view, visit https://review.coreboot.org/20971 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie669d1bc38411e40ab95c28b17ee8818874dc741 Gerrit-Change-Number: 20971 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 22:58:36 +0000 Gerrit-HasComments: No

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Change in libhwbase[master]: gnat.adc: Allow exception handlers in pure Ada code
by Arthur Heymans (Code Review) 18 Aug '17

18 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21094 ) Change subject: gnat.adc: Allow exception handlers in pure Ada code ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/21094 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5eb658f2ee0f55bb4f04da58e0e99bc9fc6780a5 Gerrit-Change-Number: 21094 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 18 Aug 2017 21:57:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/braswell/lpe: add resource allocation for BAR1
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21103 ) Change subject: soc/braswell/lpe: add resource allocation for BAR1 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58902/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14257/ : SUCCESS -- To view, visit https://review.coreboot.org/21103 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2 Gerrit-Change-Number: 21103 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 21:53:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/beltino: fix LED polarity for mccloud variant
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21102 ) Change subject: google/beltino: fix LED polarity for mccloud variant ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58901/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14256/ : SUCCESS -- To view, visit https://review.coreboot.org/21102 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e Gerrit-Change-Number: 21102 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 21:49:45 +0000 Gerrit-HasComments: No

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Change in libhwbase[master]: posix file: Add procedure to query the size of a file
by Arthur Heymans (Code Review) 18 Aug '17

18 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21095 ) Change subject: posix file: Add procedure to query the size of a file ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/21095 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib3b31e90ca98dc09185463ce467a70770e0f222d Gerrit-Change-Number: 21095 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Fri, 18 Aug 2017 21:48:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/braswell/lpe: add resource allocation for BAR1
by Matt DeVillier (Code Review) 18 Aug '17

18 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21103 Change subject: soc/braswell/lpe: add resource allocation for BAR1 ...................................................................... soc/braswell/lpe: add resource allocation for BAR1 coreboot's PCI resource allocator doesn't assign BAR1 for Braswell's LPE device, possibly because it's located where coreboot typically assigns BAR2 (0x18). Manually add the required resource via the existing lpe_read_resources function. TEST: boot google/cyan, observe MMIO values at BAR1 match expected values per datasheet (#332066-002) Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/lpe.c 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/21103/1 diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 58b5a8d..fe3fe9e 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -77,8 +77,7 @@ /* Save BAR0, BAR1, and firmware base to ACPI NVS */ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */ - /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); */ + assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2); assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); /* Device is enabled in ACPI mode */ @@ -165,8 +164,17 @@ static void lpe_read_resources(device_t dev) { + struct resource *res; pci_dev_read_resources(dev); + res = new_resource(dev, PCI_BASE_ADDRESS_2); + res->base = 0; + res->size = 0x1000; + res->limit = 0xffffffff; + res->gran = 0x0c; + res->align = 0x0c; + res->flags = IORESOURCE_MEM; + reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10, FIRMWARE_PHYS_LENGTH >> 10); -- To view, visit https://review.coreboot.org/21103 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2 Gerrit-Change-Number: 21103 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/beltino: fix LED polarity for mccloud variant
by Matt DeVillier (Code Review) 18 Aug '17

18 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21102 Change subject: google/beltino: fix LED polarity for mccloud variant ...................................................................... google/beltino: fix LED polarity for mccloud variant The LED polarity was set incorrectly, fix using values derived from original Chromium sources: branch firmware-mccloud-5827.B, ToT src/mainboard/google/mccloud/smihandler.c src/mainboard/google/mccloud/romstage.c TEST: boot google/mccloud, observe power LED on normally, blinking in S4/S4, and off in S5. Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/variants/mccloud/led.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/21102/1 diff --git a/src/mainboard/google/beltino/variants/mccloud/led.c b/src/mainboard/google/beltino/variants/mccloud/led.c index ce8d2d8..b47e50a 100644 --- a/src/mainboard/google/beltino/variants/mccloud/led.c +++ b/src/mainboard/google/beltino/variants/mccloud/led.c @@ -22,7 +22,7 @@ it8772f_gpio_led(IT8772F_GPIO_DEV, 1, /* set */ 0x01, /* select */ - state == LED_OFF ? 0x00 : 0x01, /* polarity */ + state == LED_BLINK ? 0x01 : 0x00, /* polarity */ state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */ 0x01, /* output */ state == LED_BLINK ? 0x00 : 0x01, /* I/O function */ -- To view, visit https://review.coreboot.org/21102 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e Gerrit-Change-Number: 21102 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit August 2017