coreboot-gerrit August 2017

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Change in coreboot[master]: util/msrtool: Exit program after displaying the help message
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21026 ) Change subject: util/msrtool: Exit program after displaying the help message ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58925/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14279/ : SUCCESS -- To view, visit https://review.coreboot.org/21026 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a183c267e306598627c1612f4633f1e19019f3c Gerrit-Change-Number: 21026 Gerrit-PatchSet: 3 Gerrit-Owner: Maciej Sumi?ski <maciej.suminski(a)cern.ch> Gerrit-Reviewer: Anton Kochkov <anton.kochkov(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 18:08:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/inteltool: Fix a comparison between signed and unsigned integers
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21024 ) Change subject: util/inteltool: Fix a comparison between signed and unsigned integers ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58924/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14278/ : SUCCESS -- To view, visit https://review.coreboot.org/21024 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6489c408a87213d3c39626c5379a44acea2c34d Gerrit-Change-Number: 21024 Gerrit-PatchSet: 2 Gerrit-Owner: Maciej Sumi?ski <maciej.suminski(a)cern.ch> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 18:02:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/msrtool: Exit program after displaying the help message
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21026 ) Change subject: util/msrtool: Exit program after displaying the help message ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58923/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/14277/ : SUCCESS -- To view, visit https://review.coreboot.org/21026 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a183c267e306598627c1612f4633f1e19019f3c Gerrit-Change-Number: 21026 Gerrit-PatchSet: 2 Gerrit-Owner: Maciej Sumi?ski <maciej.suminski(a)cern.ch> Gerrit-Reviewer: Anton Kochkov <anton.kochkov(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 18:01:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/inteltool: Remove doubled error message, switch to snprintf
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21025 ) Change subject: util/inteltool: Remove doubled error message, switch to snprintf ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58922/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14276/ : SUCCESS -- To view, visit https://review.coreboot.org/21025 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5ccc37e404f278cafae0a451c5acaa27d7907cce Gerrit-Change-Number: 21025 Gerrit-PatchSet: 2 Gerrit-Owner: Maciej Sumi?ski <maciej.suminski(a)cern.ch> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 17:59:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] sb/intel: Fix flashconsole on older architectures
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21107 ) Change subject: [WIP] sb/intel: Fix flashconsole on older architectures ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58919/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14273/ : SUCCESS -- To view, visit https://review.coreboot.org/21107 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 16:46:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] sb/intel: Fix flashconsole on older architectures
by Nicola Corna (Code Review) 19 Aug '17

19 Aug '17

Nicola Corna has posted comments on this change. ( https://review.coreboot.org/21107 ) Change subject: [WIP] sb/intel: Fix flashconsole on older architectures ...................................................................... Patch Set 1: With this patch I can obtain a working flashconsole for my x220 (Sandybridge) but only for ramstage, the romstage log is still silent. Any idea? -- To view, visit https://review.coreboot.org/21107 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Comment-Date: Sat, 19 Aug 2017 16:31:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] sb/intel: Fix flashconsole on older architectures
by Nicola Corna (Code Review) 19 Aug '17

19 Aug '17

Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/21107 Change subject: [WIP] sb/intel: Fix flashconsole on older architectures ...................................................................... [WIP] sb/intel: Fix flashconsole on older architectures Building coreboot with CONSOLE_SPI_FLASH on Sandybridge (and others) fails with the following errors: build/romstage/drivers/spi/spi-generic.o: In function `spi_setup_slave': src/drivers/spi/spi-generic.c:119: undefined reference to `spi_ctrlr_bus_map' src/drivers/spi/spi-generic.c:121: undefined reference to `spi_ctrlr_bus_map_count' src/drivers/spi/spi-generic.c:124: undefined reference to `spi_ctrlr_bus_map' This is due to the fact that sb/intel/common/spi.c is currently not built in romstage, but drivers/spi/spi-generic.c requires it. In this commit sb/intel/common/spi.c is adapted to the romstage and it is added to it. Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Signed-off-by: Nicola Corna <nicola(a)corna.info> --- M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/common/spi.c 2 files changed, 91 insertions(+), 74 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/21107/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index a570640..ae67b31 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -45,6 +45,7 @@ romstage-y += reset.c romstage-y += early_spi.c early_pch_common.c romstage-y += early_rcba.c +romstage-y += ../common/spi.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index a6a9ae5..ed0021b 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -15,6 +15,7 @@ */ /* This file is derived from the flashrom project. */ +#include <arch/early_variables.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -71,7 +72,7 @@ typedef struct spi_slave ich_spi_slave; -static int ichspi_lock = 0; +static int g_ichspi_lock CAR_GLOBAL = 0; typedef struct ich7_spi_regs { uint16_t spis; @@ -136,7 +137,7 @@ uint32_t *bbar; } ich_spi_controller; -static ich_spi_controller cntlr; +static ich_spi_controller g_cntlr CAR_GLOBAL; enum { SPIS_SCIP = 0x0001, @@ -278,17 +279,19 @@ static void ich_set_bbar(uint32_t minaddr) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); const uint32_t bbar_mask = 0x00ffff00; uint32_t ichspi_bbar; minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; + ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask; ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); + writel_(ichspi_bbar, cntlr->bbar); } void spi_init(void) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; @@ -299,32 +302,32 @@ #ifdef __SMM__ dev = PCI_DEV(0, 31, 0); #else - dev = dev_find_slot(0, PCI_DEVFN(31, 0)); + dev = (device_t)(dev_find_slot(0, PCI_DEVFN(31, 0))); #endif pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); - cntlr.ich9_spi = ich9_spi; + cntlr->ich9_spi = ich9_spi; hsfs = readw_(&ich9_spi->hsfs); - ichspi_lock = hsfs & HSFS_FLOCKDN; - cntlr.hsfs = hsfs; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; + car_set_var(g_ichspi_lock, hsfs & HSFS_FLOCKDN); + cntlr->hsfs = hsfs; + cntlr->opmenu = ich9_spi->opmenu; + cntlr->menubytes = sizeof(ich9_spi->opmenu); + cntlr->optype = &ich9_spi->optype; + cntlr->addr = &ich9_spi->faddr; + cntlr->data = (uint8_t *)ich9_spi->fdata; + cntlr->databytes = sizeof(ich9_spi->fdata); + cntlr->status = &ich9_spi->ssfs; + cntlr->control = (uint16_t *)ich9_spi->ssfc; + cntlr->bbar = &ich9_spi->bbar; + cntlr->preop = &ich9_spi->preop; - if (cntlr.hsfs & HSFS_FDV) + if (cntlr->hsfs & HSFS_FDV) { writel_ (4, &ich9_spi->fdoc); - cntlr.flmap0 = readl_(&ich9_spi->fdod); + cntlr->flmap0 = readl_(&ich9_spi->fdod); } ich_set_bbar(0); @@ -401,17 +404,18 @@ static int spi_setup_opcode(spi_transaction *trans) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; + uint8_t opmenu[cntlr->menubytes]; trans->opcode = trans->out[0]; spi_use_out(trans, 1); - if (!ichspi_lock) { + if (!car_get_var(g_ichspi_lock)) { /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); + writeb_(trans->opcode, cntlr->opmenu); + optypes = readw_(cntlr->optype); optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); + writew_(optypes, cntlr->optype); return 0; } else { /* The lock is on. See if what we need is on the menu. */ @@ -422,20 +426,20 @@ if (trans->opcode == SPI_OPCODE_WREN) return 0; - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; + read_reg(cntlr->opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr->menubytes; opcode_index++) { if (opmenu[opcode_index] == trans->opcode) break; } - if (opcode_index == cntlr.menubytes) { + if (opcode_index == cntlr->menubytes) { printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", trans->opcode); return -1; } - optypes = readw_(cntlr.optype); + optypes = readw_(cntlr->optype); optype = (optypes >> (opcode_index * 2)) & 0x3; if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && @@ -481,14 +485,15 @@ */ static int ich_status_poll(u16 bitmask, int wait_til_set) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int timeout = 600000; /* This will result in 6 seconds */ u16 status = 0; while (timeout--) { - status = readw_(cntlr.status); + status = readw_(cntlr->status); if (wait_til_set ^ ((status & bitmask) == 0)) { if (wait_til_set) - writew_((status & bitmask), cntlr.status); + writew_((status & bitmask), cntlr->status); return status; } udelay(10); @@ -501,14 +506,17 @@ static int spi_is_multichip (void) { - if (!(cntlr.hsfs & HSFS_FDV)) + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + + if (!(cntlr->hsfs & HSFS_FDV)) return 0; - return !!((cntlr.flmap0 >> 8) & 3); + return !!((cntlr->flmap0 >> 8) & 3); } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t control; int16_t opcode_index; int with_address; @@ -534,7 +542,7 @@ if (ich_status_poll(SPIS_SCIP, 0) == -1) return -1; - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + writew_(SPIS_CDS | SPIS_FCERR, cntlr->status); spi_setup_type(&trans); if ((opcode_index = spi_setup_opcode(&trans)) < 0) @@ -548,8 +556,8 @@ * in order to prevent the Management Engine from * issuing a transaction between WREN and DATA. */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); + if (!car_get_var(g_ichspi_lock)) + writew_(trans.opcode, cntlr->preop); return 0; } @@ -557,13 +565,13 @@ control = SPIC_SCGO | ((opcode_index & 0x07) << 4); /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) + if (readw_(cntlr->preop)) control |= SPIC_ACS; if (!trans.bytesout && !trans.bytesin) { /* SPI addresses are 24 bit only */ if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); /* * This is a 'no data' command (like Write Enable), its @@ -571,7 +579,7 @@ * spi_setup_opcode() above. Tell the chip to send the * command. */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* wait for the result */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -593,7 +601,7 @@ * and followed by other SPI commands, and this sequence is controlled * by the SPI chip driver. */ - if (trans.bytesout > cntlr.databytes) { + if (trans.bytesout > cntlr->databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" " spi_crop_chunk()?\n"); return -1; @@ -607,28 +615,28 @@ uint32_t data_length; /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + writel_(trans.offset & 0x00FFFFFF, cntlr->addr); if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); + data_length = min(trans.bytesout, cntlr->databytes); else - data_length = min(trans.bytesin, cntlr.databytes); + data_length = min(trans.bytesin, cntlr->databytes); /* Program data into FDATA0 to N */ if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); + write_reg(trans.out, cntlr->data, data_length); spi_use_out(&trans, data_length); if (with_address) trans.offset += data_length; } /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); + control &= ~((cntlr->databytes - 1) << 8); control |= SPIC_DS; control |= (data_length - 1) << 8; /* write it */ - writew_(control, cntlr.control); + writew_(control, cntlr->control); /* Wait for Cycle Done Status or Flash Cycle Error. */ status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); @@ -641,7 +649,7 @@ } if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); + read_reg(cntlr->data, trans.in, data_length); spi_use_in(&trans, data_length); if (with_address) trans.offset += data_length; @@ -649,7 +657,7 @@ } /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); + writew_(0, cntlr->preop); return 0; } @@ -657,8 +665,9 @@ /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { - uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; - writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); + uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF; + writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr); } /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. @@ -668,21 +677,22 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, unsigned int len) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfs; uint32_t addr; timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & + while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { udelay(8); } - writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); if (!timeout) { uint16_t hsfc; - addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&cntlr.ich9_spi->hsfc); + addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr->ich9_spi->hsfc); printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -692,8 +702,8 @@ if (hsfs & HSFS_FCERR) { uint16_t hsfc; - addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&cntlr.ich9_spi->hsfc); + addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF; + hsfc = readw_(&cntlr->ich9_spi->hsfc); printk(BIOS_ERR, "Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -707,6 +717,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u32 start, end, erase_size; int ret; uint16_t hsfc; @@ -729,17 +740,17 @@ while (offset < end) { /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); ich_hwseq_set_addr(offset); offset += erase_size; - hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr->ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr->ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, len)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); @@ -757,12 +768,13 @@ static void ich_read_data(uint8_t *data, int len) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); int i; uint32_t temp32 = 0; for (i = 0; i < len; i++) { if ((i % 4) == 0) - temp32 = readl_(cntlr.data + i); + temp32 = readl_(cntlr->data + i); data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; } @@ -771,6 +783,7 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, void *buf) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -784,20 +797,20 @@ } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); while (len > 0) { - block_len = min(len, cntlr.databytes); + block_len = min(len, cntlr->databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); - hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr->ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr->ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) return 1; @@ -816,6 +829,7 @@ */ static void ich_fill_data(const uint8_t *data, int len) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t temp32 = 0; int i; @@ -829,16 +843,17 @@ temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ - writel_(temp32, cntlr.data + (i - (i % 4))); + writel_(temp32, cntlr->data + (i - (i % 4))); } i--; if ((i % 4) != 3) /* Write remaining data to regs. */ - writel_(temp32, cntlr.data + (i - (i % 4))); + writel_(temp32, cntlr->data + (i - (i % 4))); } static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, const void *buf) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint16_t hsfc; uint16_t timeout = 100 * 60; uint8_t block_len; @@ -852,24 +867,24 @@ } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); + writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs); while (len > 0) { - block_len = min(len, cntlr.databytes); + block_len = min(len, cntlr->databytes); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; ich_hwseq_set_addr(addr); ich_fill_data(buf, block_len); - hsfc = readw_(&cntlr.ich9_spi->hsfc); + hsfc = readw_(&cntlr->ich9_spi->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.ich9_spi->hsfc); + writew_(hsfc, &cntlr->ich9_spi->hsfc); if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) { @@ -895,6 +910,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, struct spi_flash *flash) { + ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); uint32_t flcomp; /* Try generic probing first if spi_is_multichip returns 0. */ @@ -905,7 +921,7 @@ flash->name = "Opaque HW-sequencing"; ich_hwseq_set_addr (0); - switch ((cntlr.hsfs >> 3) & 3) + switch ((cntlr->hsfs >> 3) & 3) { case 0: flash->sector_size = 256; @@ -921,14 +937,14 @@ break; } - writel_ (0x1000, &cntlr.ich9_spi->fdoc); - flcomp = readl_(&cntlr.ich9_spi->fdod); + writel_ (0x1000, &cntlr->ich9_spi->fdoc); + flcomp = readl_(&cntlr->ich9_spi->fdod); flash->size = 1 << (19 + (flcomp & 7)); flash->ops = &spi_flash_ops; - if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) + if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3)) flash->size += 1 << (19 + ((flcomp >> 3) & 7)); printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); -- To view, visit https://review.coreboot.org/21107 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info>

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Change in coreboot[master]: drivers/i2c/ck505: Add generic driver to configure clockgen
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20042 ) Change subject: drivers/i2c/ck505: Add generic driver to configure clockgen ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58915/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14270/ : SUCCESS -- To view, visit https://review.coreboot.org/20042 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7 Gerrit-Change-Number: 20042 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Korolyov <andrey(a)xdel.ru> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Swift Geek <swiftgeek(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 08:55:17 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/intel/fsp2_0: Link Post PCI enumeration Notify with BS_DEV_EN...
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21084 ) Change subject: drivers/intel/fsp2_0: Link Post PCI enumeration Notify with BS_DEV_ENABLE ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58914/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14269/ : SUCCESS -- To view, visit https://review.coreboot.org/21084 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1 Gerrit-Change-Number: 21084 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Sat, 19 Aug 2017 06:54:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add function to DLOCK PR registers
by build bot (Jenkins) (Code Review) 19 Aug '17

19 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21063 ) Change subject: soc/intel/common: Add function to DLOCK PR registers ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58912/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14267/ : SUCCESS -- To view, visit https://review.coreboot.org/21063 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Gerrit-Change-Number: 21063 Gerrit-PatchSet: 5 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 19 Aug 2017 06:52:52 +0000 Gerrit-HasComments: No

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