coreboot-gerrit August 2017

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Change in coreboot[master]: google/cyan: Remove support for pre-EVT board
by Matt DeVillier (Code Review) 21 Aug '17

21 Aug '17

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/21123 ) Change subject: google/cyan: Remove support for pre-EVT board ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/21123/1/src/mainboard/google/cyan/smihandle… File src/mainboard/google/cyan/smihandler.c: https://review.coreboot.org/#/c/21123/1/src/mainboard/google/cyan/smihandle… PS1, Line 155: : : : : : : : This I'm not sure about -- all other Braswell boards added this to later board revisions and excluded earlier ones (prior to support for earlier revisions being dropped), but cyan does the reverse. Is that correct? -- To view, visit https://review.coreboot.org/21123 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f Gerrit-Change-Number: 21123 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 21 Aug 2017 05:52:00 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: google/edgar: add new board as variant of cyan baseboard
by build bot (Jenkins) (Code Review) 21 Aug '17

21 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21127 ) Change subject: google/edgar: add new board as variant of cyan baseboard ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58987/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14334/ : SUCCESS -- To view, visit https://review.coreboot.org/21127 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659 Gerrit-Change-Number: 21127 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 05:49:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/reks: add new board as variant of cyan baseboard
by Matt DeVillier (Code Review) 21 Aug '17

21 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21128 Change subject: google/reks: add new board as variant of cyan baseboard ...................................................................... google/reks: add new board as variant of cyan baseboard Add support for google/reks (Lenovo Chromebook N22/N42) as a variant of the cyan Braswell basebaseboard. Add new I2C device and SPD files to the baseboard for potential reuse for other variants. Sourced from Chromium branch firmware-reks-7287.133.B, commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/Kconfig M src/mainboard/google/cyan/Kconfig.name A src/mainboard/google/cyan/acpi/touchscreen_melfas.asl A src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.hex A src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.hex A src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.hex A src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.hex A src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.hex A src/mainboard/google/cyan/variants/reks/Makefile.inc A src/mainboard/google/cyan/variants/reks/board_info.txt A src/mainboard/google/cyan/variants/reks/devicetree.cb A src/mainboard/google/cyan/variants/reks/gpio.c A src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl A src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl A src/mainboard/google/cyan/variants/reks/include/variant/onboard.h A src/mainboard/google/cyan/variants/reks/spd.c 16 files changed, 1,060 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/21128/1 diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index 71cde58..8395a13 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -38,11 +38,14 @@ string default "cyan" if BOARD_GOOGLE_CYAN default "edgar" if BOARD_GOOGLE_EDGAR + default "reks" if BOARD_GOOGLE_REKS config MAINBOARD_PART_NUMBER string default "Cyan" if BOARD_GOOGLE_CYAN default "Edgar" if BOARD_GOOGLE_EDGAR + default "Reks" if BOARD_GOOGLE_REKS + config MAINBOARD_VENDOR string @@ -52,6 +55,7 @@ string default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN default "variants/edgar/devicetree.cb" if BOARD_GOOGLE_EDGAR + default "variants/reks/devicetree.cb" if BOARD_GOOGLE_REKS config VGA_BIOS_FILE string @@ -75,5 +79,6 @@ depends on CHROMEOS default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN default "EDGAR TEST A-A 1829" if BOARD_GOOGLE_EDGAR + default "REKS TEST A-A 1829" if BOARD_GOOGLE_REKS endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name index 50f9c58..8c70a9c 100644 --- a/src/mainboard/google/cyan/Kconfig.name +++ b/src/mainboard/google/cyan/Kconfig.name @@ -5,3 +5,7 @@ config BOARD_GOOGLE_EDGAR bool "Edgar" select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_REKS + bool "Reks" + select BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl new file mode 100644 index 0000000..8d36649 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/touchscreen_melfas.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C1) +{ + Device (MTSA) + { + Name (_HID, "MLFS0000") + Name (_DDN, "Melfas Touchscreen ") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Method(_CRS, 0x0, NotSerialized) + { + Name (BUF0, ResourceTemplate () + { + I2cSerialBus( + 0x34, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCH_IRQ + } + }) + Return (BUF0) + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.hex new file mode 100644 index 0000000..c35a85f --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.hex @@ -0,0 +1,32 @@ +92 20 F1 03 05 19 05 03 +03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 +90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 +00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 +00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 +47 54 4D 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.hex b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.hex new file mode 100644 index 0000000..5b54610 --- /dev/null +++ b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.hex @@ -0,0 +1,32 @@ +92 20 F1 03 04 11 05 0B +03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 +10 04 3C 3C 01 90 00 00 +00 21 CA FA 00 00 00 A8 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 +00 00 00 00 00 00 00 00 +45 44 46 38 31 33 32 41 +33 4D 41 2D 4A 44 2D 46 +20 20 00 00 80 2C 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.hex b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.hex new file mode 100644 index 0000000..4fa1782 --- /dev/null +++ b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.hex @@ -0,0 +1,32 @@ +92 20 F1 03 04 11 05 0B +03 11 01 08 09 00 00 05 +78 78 90 50 90 11 50 E0 +10 04 3C 3C 01 90 00 00 +00 21 CA FA 00 00 00 A8 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2C 00 +00 00 00 00 00 00 00 00 +4D 54 35 32 4C 32 35 36 +4D 33 32 44 31 50 46 31 +30 37 00 00 80 2C 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.hex b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.hex new file mode 100644 index 0000000..244515e --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.hex @@ -0,0 +1,32 @@ +92 20 F1 03 04 11 05 0B +03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 +10 04 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 30 34 +45 45 2D 45 47 43 46 20 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.hex b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.hex new file mode 100644 index 0000000..d1d9e59 --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.hex @@ -0,0 +1,32 @@ +92 20 F1 03 04 11 05 0B +03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 +10 04 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 32 34 +45 42 2D 45 47 43 46 20 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc new file mode 100644 index 0000000..e406f67 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE +SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD +SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCE +SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF +SPD_SOURCES += empty +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/reks/board_info.txt b/src/mainboard/google/cyan/variants/reks/board_info.txt new file mode 100644 index 0000000..967aad1 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Reks +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cyan/variants/reks/devicetree.cb b/src/mainboard/google/cyan/variants/reks/devicetree.cb new file mode 100644 index 0000000..53239b5 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/devicetree.cb @@ -0,0 +1,141 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "1" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + register "PcdSdcardMode" = "PCH_ACPI_MODE" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "1" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "1" + register "PcdEnableI2C5" = "1" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "SVID_PMIC_CONFIG" + register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "7" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "3" + register "Usb2Port3IUsbTxEmphasisEn" = "2" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "3" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "1" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "1" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 off end # 8086 2290 - SPI 2 + device pci 1e.7 off end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/google/cyan/variants/reks/gpio.c b/src/mainboard/google/cyan/variants/reks/gpio.c new file mode 100644 index 0000000..e7b2adf --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/gpio.c @@ -0,0 +1,261 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard/google/cyan/irqroute.h> +#include <soc/gpio.h> +#include <stdlib.h> + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ + NATIVE_PU20K(2), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPIO_NC, + /* 76 GPI SATA_GP1 */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN-> EC_IN_RW */ + GPIO_NC, /* 80 SATA_GP3 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + Native_M1, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2c93061 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_PMIC" +#define DPTF_TSR0_PASSIVE 49 +#define DPTF_TSR0_CRITICAL 70 + + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Charger" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_Vcore" +#define DPTF_TSR2_PASSIVE 48 +#define DPTF_TSR2_CRITICAL 70 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 2600, /* PowerLimitMinimum */ + 5000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..76f6ab8 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/include/variant/acpi/mainboard.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Melfas touchscreen */ +#include <mainboard/google/cyan/acpi/touchscreen_melfas.asl> + +/* Elan touchscreen */ +#include <mainboard/google/cyan/acpi/touchscreen_elan.asl> + +/* Elan trackpad */ +#include <mainboard/google/cyan/acpi/trackpad_elan.asl> + +/* Realtek audio codec */ +#include <mainboard/google/cyan/acpi/codec_realtek.asl> diff --git a/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h b/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h new file mode 100644 index 0000000..078fa2f --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/include/variant/onboard.h @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/cyan/irqroute.h> + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* + * gpio based irq for kbd, 17th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 18 + */ +/* ToDo: change kbd irq to gpio bank index */ +#define BOARD_I8042_IRQ 182 + +#define BOARD_TOUCH_IRQ 184 + +/* DPTF */ +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 + +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 95 +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define BOARD_TRACKPAD_GPIO_INDEX 18 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5650" +#define AUDIO_CODEC_CID "10EC5650" +#define AUDIO_CODEC_DDN "RTEK Codec Controller " +#define AUDIO_CODEC_I2C_ADDR 0x1A +#define BCRD2_PMIC_I2C_BUS 0x01 + +/* I2C data hold time */ +#define BOARD_I2C1_DATA_HOLD_TIME 0x1E +#define BOARD_I2C6_DATA_HOLD_TIME 0x1E + +#endif diff --git a/src/mainboard/google/cyan/variants/reks/spd.c b/src/mainboard/google/cyan/variants/reks/spd.c new file mode 100644 index 0000000..49d35b0 --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/spd.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <gpio.h> +#include <lib.h> +#include <spd.h> +#include <memory_info.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> +#include <mainboard_spd.h> + +/* We use RAM_ID3 to indicate dual channel config. + * + * 0b0000 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCF 1600MHz + * 0b0001 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8GTMLAR-NUD 1600MHz + * 0b0010 - 2GiB total - 1 x 2GiB micron MT52L256M32D1PF-107 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF 1600MHz + * 0b0100 - 2GiB total - 1 x 2GiB Micron EDF8132A3MA-JD-F 1600MHz + * + * 0b1000 - 4GiB total - 2 x 2GiB Samsung K4E8E304EE-EGCF 1600MHz + * 0b1001 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8GTMLAR-NUD 1600MHz + * 0b1010 - 4GiB total - 2 x 2GiB micron MT52L256M32D1PF-107 1600MHz + * 0b1011 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF 1600MHz + * 0b1100 - 4GiB total - 2 x 2GiB Micron EDF8132A3MA-JD-F 1600MHz + * + */ + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + + gpio_t spd_gpios[] = { + GP_SW_80, /* SATA_GP3,RAMID0 */ + GP_SW_67, /* I2C3_SCL,RAMID1 */ + GP_SE_02, /* MF_PLT_CLK1, RAMID2 */ + GP_SW_64, /* I2C3_SDA RAMID3 */ + }; + + ram_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + int spd_index = ram_id & 0x7; + + /* + * Use 0 in case over total spds + */ + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + + if (spd_index >= total_spds) + spd_index = 0; + + /* channel configs */ + *dual = !!(ram_id & (1<<3)); + + printk(BIOS_DEBUG, "channel_config=%d\n", *dual); + + return &spd_file_content[SPD_LEN * spd_index]; +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + char *spd_file; + size_t spd_file_len; + void *spd_content; + int dual_channel = 0; + + /* Find the SPD data in CBFS. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(spd_file, + spd_file_len / SPD_LEN, + &dual_channel); + if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_LEN); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + ps->spd_data_ch0 = spd_content; + ps->spd_ch0_config = 1; + if (dual_channel) { + ps->spd_data_ch1 = spd_content; + ps->spd_ch1_config = 1; + } else { + ps->spd_ch1_config = 2; + } + } +} + +static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) +{ + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + uint16_t clock_frequency; + + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Parse the SPD data to determine the DIMM information */ + dimm->ddr_type = MEMORY_DEVICE_LPDDR3; + dimm->dimm_size = capmb / 8 * busw / devw * ranks; /* MiB */ + clock_frequency = 1000 * spd[11] / (spd[10] * spd[12]); /* MHz */ + dimm->ddr_frequency = 2 * clock_frequency; /* Double Data Rate */ + dimm->mod_type = spd[3] & 0xf; + memcpy((char *)&dimm->module_part_number[0], &spd[0x80], + sizeof(dimm->module_part_number) - 1); + dimm->mod_id = *(uint16_t *)&spd[0x94]; + + switch (busw) { + default: + case 8: + dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + + case 16: + dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + + case 32: + dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + + case 64: + dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + } +} + +void mainboard_save_dimm_info(struct romstage_params *params) +{ + struct dimm_info *dimm; + struct memory_info *mem_info; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first channel memory */ + dimm = &mem_info->dimm[0]; + set_dimm_info(params->pei_data->spd_data_ch0, dimm); + mem_info->dimm_cnt = 1; + + /* Describe the second channel memory */ + if (params->pei_data->spd_ch1_config == 1) { + dimm = &mem_info->dimm[1]; + set_dimm_info(params->pei_data->spd_data_ch1, dimm); + dimm->channel_num = 1; + mem_info->dimm_cnt = 2; + } +} -- To view, visit https://review.coreboot.org/21128 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385 Gerrit-Change-Number: 21128 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/edgar: add new board as variant of cyan baseboard
by Matt DeVillier (Code Review) 21 Aug '17

21 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21127 Change subject: google/edgar: add new board as variant of cyan baseboard ...................................................................... google/edgar: add new board as variant of cyan baseboard Add support for google/edgar (Acer Chromebook 14 CB3-431) as a variant of the cyan Braswell basebaseboard. Add common code to the baseboard and selectively apply it on a per-variant basis. Sourced from Chromium branch firmware-edgar-7287.167.B, commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/Kconfig M src/mainboard/google/cyan/Kconfig.name M src/mainboard/google/cyan/Makefile.inc A src/mainboard/google/cyan/acpi/codec_realtek.asl M src/mainboard/google/cyan/acpi_tables.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/cyan/romstage.c M src/mainboard/google/cyan/smihandler.c A src/mainboard/google/cyan/spd/empty.spd.hex A src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex A src/mainboard/google/cyan/spd/mainboard_spd.h A src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex A src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex A src/mainboard/google/cyan/variants/edgar/Makefile.inc A src/mainboard/google/cyan/variants/edgar/board_info.txt A src/mainboard/google/cyan/variants/edgar/devicetree.cb A src/mainboard/google/cyan/variants/edgar/gpio.c A src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl A src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl A src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h A src/mainboard/google/cyan/variants/edgar/spd.c 21 files changed, 1,060 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/21127/1 diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index ea8047f..71cde58 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -37,10 +37,12 @@ config VARIANT_DIR string default "cyan" if BOARD_GOOGLE_CYAN + default "edgar" if BOARD_GOOGLE_EDGAR config MAINBOARD_PART_NUMBER string default "Cyan" if BOARD_GOOGLE_CYAN + default "Edgar" if BOARD_GOOGLE_EDGAR config MAINBOARD_VENDOR string @@ -49,6 +51,7 @@ config DEVICETREE string default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN + default "variants/edgar/devicetree.cb" if BOARD_GOOGLE_EDGAR config VGA_BIOS_FILE string @@ -71,5 +74,6 @@ string depends on CHROMEOS default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN + default "EDGAR TEST A-A 1829" if BOARD_GOOGLE_EDGAR endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name index 91e10c9..50f9c58 100644 --- a/src/mainboard/google/cyan/Kconfig.name +++ b/src/mainboard/google/cyan/Kconfig.name @@ -1,3 +1,7 @@ config BOARD_GOOGLE_CYAN bool "Cyan" select BOARD_GOOGLE_BASEBOARD_CYAN + +config BOARD_GOOGLE_EDGAR + bool "Edgar" + select BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 274e9f0..da7ac8c 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -32,3 +32,4 @@ subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/spd diff --git a/src/mainboard/google/cyan/acpi/codec_realtek.asl b/src/mainboard/google/cyan/acpi/codec_realtek.asl new file mode 100644 index 0000000..d3fa84e --- /dev/null +++ b/src/mainboard/google/cyan/acpi/codec_realtek.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C5) +{ + /* Realtek Audio Codec */ + Device (RTEK) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.PCI0.I2C5", /* ResourceSource: I2C bus controller name */ + ) + + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + } +} + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } + }) +} diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c index d4271e5..47ddc0b 100644 --- a/src/mainboard/google/cyan/acpi_tables.c +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -43,6 +43,9 @@ /* Enable DPTF */ gnvs->dpte = 1; + + /* PMIC is configured in I2C1, hidden it from OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c index 8aac84f..5bf8380 100644 --- a/src/mainboard/google/cyan/chromeos.c +++ b/src/mainboard/google/cyan/chromeos.c @@ -24,6 +24,8 @@ #define WP_STATUS_PAD_CFG0 0x4838 #define WP_STATUS_PAD_CFG1 0x483C +#define WP_GPIO GP_E_22 + #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> @@ -52,15 +54,23 @@ * in the reading. */ #if ENV_ROMSTAGE - write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0), - (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); - write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1), - PAD_CONFIG1_DEFAULT0); + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { + write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0), + (PAD_PULL_UP_20K | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); + write32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG1), + PAD_CONFIG1_DEFAULT0); + } else { + gpio_input_pullup(WP_GPIO); + } #endif /* WP is enabled when the pin is reading high. */ - return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) - & PAD_VAL_HIGH); + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { + return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0)) + & PAD_VAL_HIGH); + } else { + return !!gpio_get(WP_GPIO); + } } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 61ebde9..c3fce62 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -22,6 +22,7 @@ #include <soc/romstage.h> #include <string.h> + /* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) { diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 75c1890..f31f68f 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -152,6 +152,12 @@ /* Clear pending events that may trigger immediate wake */ while (google_chromeec_get_event() != 0) ; + + /* Set LPC lines to low power in S3/S5. */ + if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN) && + ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))) { + lpc_set_low_power(); + } #endif } diff --git a/src/mainboard/google/cyan/spd/empty.spd.hex b/src/mainboard/google/cyan/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/cyan/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex b/src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex new file mode 100644 index 0000000..a8e0c26 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 11 05 0B 03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 4A 54 42 4C 41 52 2D 4E +55 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/mainboard_spd.h b/src/mainboard/google/cyan/spd/mainboard_spd.h new file mode 100644 index 0000000..ca3e30a --- /dev/null +++ b/src/mainboard/google/cyan/spd/mainboard_spd.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_SPD_H_ +#define _MAINBOARD_SPD_H_ + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +#endif /* _MAINBOARD_SPD_H_ */ diff --git a/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex b/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex new file mode 100644 index 0000000..056dc25 --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex @@ -0,0 +1,32 @@ +91 20 F1 03 04 11 05 0B +03 11 01 08 0A 00 40 01 +78 78 90 50 90 11 50 E0 +10 04 3C 3C 01 90 00 00 +00 00 00 00 00 00 00 A8 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 30 34 +45 45 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex b/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex new file mode 100644 index 0000000..6d9ae52 --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex @@ -0,0 +1,32 @@ +91 20 F1 03 05 19 05 03 +03 11 01 08 09 00 40 05 +78 78 90 50 90 11 50 E0 +90 06 3C 3C 01 90 00 00 +00 00 CA FA 00 00 00 A8 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 32 34 +45 42 2D 45 47 43 46 20 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc new file mode 100644 index 0000000..e406f67 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE +SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD +SPD_SOURCES += samsung_dimm_K4E8E304EE-EGCE +SPD_SOURCES += hynix_dimm_H9CCNNN8JTBLAR-NUD +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF +SPD_SOURCES += empty +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/cyan/variants/edgar/board_info.txt b/src/mainboard/google/cyan/variants/edgar/board_info.txt new file mode 100644 index 0000000..e50ba0b --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Edgar +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cyan/variants/edgar/devicetree.cb b/src/mainboard/google/cyan/variants/edgar/devicetree.cb new file mode 100644 index 0000000..2033f9e --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/devicetree.cb @@ -0,0 +1,144 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "1" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "1" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "0" + register "PcdEnableI2C1" = "0" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "1" + register "PcdEnableI2C5" = "1" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "SVID_PMIC_CONFIG" + register "PcdEmmcMode" = "PCH_ACPI_MODE" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "0" # Disable SATA + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "5" + register "Usb2Port0IUsbTxEmphasisEn" = "2" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "3" + register "Usb2Port1IUsbTxEmphasisEn" = "2" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "3" + register "Usb2Port2IUsbTxEmphasisEn" = "2" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "0" + register "Usb2Port4IUsbTxEmphasisEn" = "2" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbHsicPort" = "0" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "1" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 off end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 off end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 off end # 8086 2290 - SPI 2 + device pci 1e.7 off end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/google/cyan/variants/edgar/gpio.c b/src/mainboard/google/cyan/variants/edgar/gpio.c new file mode 100644 index 0000000..6e81c23 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/gpio.c @@ -0,0 +1,257 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard/google/cyan/irqroute.h> +#include <soc/gpio.h> +#include <stdlib.h> + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + GPIO_NC, /* 30 SDMMC3_D1 */ + GPIO_NC, /* 31 SDMMC3_CLK */ + GPIO_NC, /* 32 SDMMC3_D3 */ + GPIO_NC, /* 33 SDMMC3_D2 */ + GPIO_NC, /* 34 SDMMC3_CMD */ + GPIO_NC, /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + GPIO_NC, /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_NC, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPIO_NC, /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPIO_NC, /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + GPIO_NC, /* 61 I2C0_SDA */ + GPIO_NC, /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + GPIO_NC, /* 65 I2C0_SCL */ + GPIO_NC, /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPIO_NC, + /* 76 GPI SATA_GP1 */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERTB */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + GPIO_INPUT_PU_20K, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPIO_NC, /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + GPIO_NC, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..287b4b4 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 45 +#define DPTF_TSR0_CRITICAL 75 + + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "R4303_CPU" +#define DPTF_TSR1_PASSIVE 49 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 1 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 49 +#define DPTF_TSR2_CRITICAL 70 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 300, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 2000, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..8e7868e --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/acpi/mainboard.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan trackpad */ +#include <mainboard/google/cyan/acpi/trackpad_elan.asl> + +/* Realtek audio codec */ +#include <mainboard/google/cyan/acpi/codec_realtek.asl> diff --git a/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h new file mode 100644 index 0000000..796ddb0 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/include/variant/onboard.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include <mainboard/google/cyan/irqroute.h> + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* + * gpio based irq for kbd, 17th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 18 + */ +/* ToDo: change kbd irq to gpio bank index */ +#define BOARD_I8042_IRQ 182 + +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 95 +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define BOARD_TRACKPAD_GPIO_INDEX 18 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5650" +#define AUDIO_CODEC_CID "10EC5650" +#define AUDIO_CODEC_DDN "RTEK Codec Controller " +#define AUDIO_CODEC_I2C_ADDR 0x1A +#define BCRD2_PMIC_I2C_BUS 0x01 + +/* I2C data hold time */ +#define BOARD_I2C6_DATA_HOLD_TIME 0x2F + +#define DPTF_CPU_PASSIVE 88 +#define DPTF_CPU_CRITICAL 90 + +#endif \ No newline at end of file diff --git a/src/mainboard/google/cyan/variants/edgar/spd.c b/src/mainboard/google/cyan/variants/edgar/spd.c new file mode 100644 index 0000000..0bb16f4 --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/spd.c @@ -0,0 +1,221 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <gpio.h> +#include <lib.h> +#include <spd.h> +#include <memory_info.h> +#include <smbios.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> +#include <mainboard_spd.h> + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4E8E304EE-EGCE + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H9CCNNN8JTBLAR-NUD + * 0b0010 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCE + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H9CCNNN8JTBLAR-NUD + * 0b0100 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF + * 0b0101 - TBD + * 0b0110 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF + */ +static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 4); + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + + gpio_t spd_gpios[] = { + GP_SW_80, /* SATA_GP3, RAMID0 */ + GP_SW_67, /* I2C3_SCL, RAMID1 */ + GP_SE_02, /* MF_PLT_CLK1, RAMID2 */ + GP_SW_64, /* I2C3_SDA, RAMID3 */ + }; + + ram_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + if (ram_id >= total_spds) + return NULL; + + /* Determine if this is a single or dual channel memory system */ + if (dual_channel_config & (1 << ram_id)) + *dual = 1; + + /* Display the RAM type */ + switch (ram_id) { + case 0: + printk(BIOS_DEBUG, "4GiB Samsung K4E8E304EE-EGCE\n"); + break; + case 1: + printk(BIOS_DEBUG, "4GiB Hynix H9CCNNN8JTBLAR-NUD\n"); + break; + case 2: + printk(BIOS_DEBUG, "2GiB Samsung K4E8E304EE-EGCE\n"); + break; + case 3: + printk(BIOS_DEBUG, "2GiB Hynix H9CCNNN8JTBLAR-NUD\n"); + break; + case 4: + printk(BIOS_DEBUG, "4GiB Samsung K4E8E324EB-EGCF\n"); + break; + case 5: + printk(BIOS_DEBUG, "empty\n"); + break; + case 6: + printk(BIOS_DEBUG, "2GiB Samsung K4E8E324EB-EGCF\n"); + break; + } + + /* Return the serial product data for the RAM */ + return &spd_file_content[SPD_LEN * ram_id]; +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + char *spd_file; + size_t spd_file_len; + void *spd_content; + int dual_channel = 0; + + /* Find the SPD data in CBFS. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(spd_file, + spd_file_len / SPD_LEN, + &dual_channel); + if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_LEN); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + ps->spd_data_ch0 = spd_content; + ps->spd_ch0_config = 1; + if (dual_channel) { + ps->spd_data_ch1 = spd_content; + ps->spd_ch1_config = 1; + } else { + ps->spd_ch1_config = 2; + } + } +} + +static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) +{ + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + void *hob_list_ptr; + EFI_HOB_GUID_TYPE *hob_ptr; + FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + hob_list_ptr = fsp_get_hob_list(); + hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); + if (hob_ptr != NULL) { + memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); + dimm->ddr_frequency = memory_info_hob->MemoryFrequencyInMHz; + } else { + printk(BIOS_ERR, "Can't get memory info hob pointer\n"); + dimm->ddr_frequency = 0; + } + + /* Parse the SPD data to determine the DIMM information */ + dimm->ddr_type = MEMORY_DEVICE_LPDDR3; + dimm->dimm_size = capmb / 8 * busw / devw * ranks; /* MiB */ + dimm->mod_type = spd[3] & 0xf; + memcpy((char *)&dimm->module_part_number[0], &spd[0x80], + sizeof(dimm->module_part_number) - 1); + dimm->mod_id = *(uint16_t *)&spd[0x94]; + + switch (busw) { + default: + case 8: + dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + + case 16: + dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + + case 32: + dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + + case 64: + dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + } +} + +void mainboard_save_dimm_info(struct romstage_params *params) +{ + struct dimm_info *dimm; + struct memory_info *mem_info; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first channel memory */ + dimm = &mem_info->dimm[0]; + set_dimm_info(params->pei_data->spd_data_ch0, dimm); + mem_info->dimm_cnt = 1; + + /* Describe the second channel memory */ + if (params->pei_data->spd_ch1_config == 1) { + dimm = &mem_info->dimm[1]; + set_dimm_info(params->pei_data->spd_data_ch1, dimm); + dimm->channel_num = 1; + mem_info->dimm_cnt = 2; + } +} -- To view, visit https://review.coreboot.org/21127 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659 Gerrit-Change-Number: 21127 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/cyan: convert to variant configuration
by Matt DeVillier (Code Review) 21 Aug '17

21 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21126 Change subject: google/cyan: convert to variant configuration ...................................................................... google/cyan: convert to variant configuration Setup cyan to be the baseboard for other Google Braswell boards, to be added in subsequent commits. This commit keeps code common to all Google Braswell boards in the cyan baseboard, separates out the board-specific bits into the new cyan variant, and defines the I2C ACPI devices such that they can be easily reused for other variants. It also switches the trackpad/touchscreen interrupts from edge to level, for better performance/compatibility as was done with all previous Google boards. Additionally, a few hardcoded values were replaced with variables, and a few typos/formatting errors were corrected. Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/Kconfig M src/mainboard/google/cyan/Kconfig.name M src/mainboard/google/cyan/Makefile.inc A src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/dptf.asl M src/mainboard/google/cyan/acpi/mainboard.asl M src/mainboard/google/cyan/acpi/superio.asl A src/mainboard/google/cyan/acpi/touchscreen_elan.asl A src/mainboard/google/cyan/acpi/trackpad_elan.asl M src/mainboard/google/cyan/board_info.txt M src/mainboard/google/cyan/boardid.c M src/mainboard/google/cyan/ramstage.c M src/mainboard/google/cyan/smihandler.c R src/mainboard/google/cyan/variants/cyan/Makefile.inc A src/mainboard/google/cyan/variants/cyan/board_info.txt R src/mainboard/google/cyan/variants/cyan/devicetree.cb R src/mainboard/google/cyan/variants/cyan/gpio.c A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl R src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h R src/mainboard/google/cyan/variants/cyan/spd.c 21 files changed, 380 insertions(+), 267 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/21126/1 diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index fdeac63..ea8047f 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -1,7 +1,5 @@ -if BOARD_GOOGLE_CYAN - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_GOOGLE_BASEBOARD_CYAN + def_bool n select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC @@ -14,6 +12,8 @@ select SOC_INTEL_BRASWELL select HAVE_ACPI_RESUME select PCIEXP_L1_SUB_STATE + +if BOARD_GOOGLE_BASEBOARD_CYAN config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES @@ -34,13 +34,21 @@ string default google/cyan +config VARIANT_DIR + string + default "cyan" if BOARD_GOOGLE_CYAN + config MAINBOARD_PART_NUMBER string - default "Cyan" + default "Cyan" if BOARD_GOOGLE_CYAN config MAINBOARD_VENDOR string default "Google" + +config DEVICETREE + string + default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN config VGA_BIOS_FILE string @@ -62,5 +70,6 @@ config GBB_HWID string depends on CHROMEOS - default "CYAN TEST A-A 1829" -endif # BOARD_GOOGLE_CYAN + default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN + +endif # BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name index a4562d3..91e10c9 100644 --- a/src/mainboard/google/cyan/Kconfig.name +++ b/src/mainboard/google/cyan/Kconfig.name @@ -1,2 +1,3 @@ config BOARD_GOOGLE_CYAN bool "Cyan" + select BOARD_GOOGLE_BASEBOARD_CYAN diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 43e3c95..274e9f0 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -16,15 +16,19 @@ subdirs-y += spd -romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += boardid.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c -ramstage-y += boardid.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +subdirs-y += variants/$(VARIANT_DIR) + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/google/cyan/acpi/codec_maxim.asl b/src/mainboard/google/cyan/acpi/codec_maxim.asl new file mode 100644 index 0000000..9abc91e --- /dev/null +++ b/src/mainboard/google/cyan/acpi/codec_maxim.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C2) +{ + /* Maxim Audio Codec */ + Device (MAXM) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + /* Add DT style bindings with _DSD */ + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + /* set maxim micbias to 2.8v */ + Package () { "maxim,micbias", 3 }, + } + }) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } + Device (TISW) /* TI Switch driver I2C */ + { + Name (_ADR, 0) + Name (_HID, TI_SWITCH_HID) + Name (_CID, TI_SWITCH_CID) + Name (_DDN, TI_SWITCH_DDN) + Name (_UID, 1) + + /* Add DT style bindings with _DSD */ + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + /* set ti micbias to 2.8v */ + Package () { "ti,micbias", 7 }, + } + }) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } + + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + } +} + + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } + }) +} diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 95b6951..6407a56 100644 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -14,63 +14,8 @@ * GNU General Public License for more details. */ -#define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 49 -#define DPTF_TSR0_CRITICAL 75 +/* Include Variant DPTF */ +#include <variant/acpi/dptf.asl> -#define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 85 - -#define DPTF_TSR2_SENSOR_ID 2 -#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 49 -#define DPTF_TSR2_CRITICAL 75 - -#define DPTF_ENABLE_CHARGER - -/* Charger performance states, board-specific values from charger and EC */ -Name (CHPS, Package () { - Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */ - Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */ - Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ - Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */ - Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ -}) - -/* Mainboard specific _PDL is 1GHz */ -Name (MPDL, 8) - -Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, -}) - -Name (MPPC, Package () -{ - 0x2, /* Revision */ - Package () { /* Power Limit 1 */ - 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 2000, /* PowerLimitMinimum */ - 6200, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ - }, - Package () { /* Power Limit 2 */ - 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ - 1000, /* TimeWindowMinimum */ - 1000, /* TimeWindowMaximum */ - 1000 /* StepSize */ - } -}) - -/* Include DPTF */ +/* Include SoC DPTF */ #include <acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index 7a4b0ea..3228a31 100644 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#include <onboard.h> +#include <variant/onboard.h> Scope (\_SB) { @@ -24,189 +24,6 @@ Name (_HID, EisaId ("PNP0C0C")) Name (_UID, 1) } -} - -Scope (\_SB.PCI0.I2C1) -{ - Device (ETSA) - { - Name (_HID, "ELAN0001") - Name (_DDN, "Elan Touchscreen ") - Name (_UID, 5) - Name (ISTP, 0) /* TouchScreen */ - - Method(_CRS, 0x0, NotSerialized) - { - Name(BUF0,ResourceTemplate () - { - I2CSerialBus( - 0x10, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C1", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCH_IRQ - } - - } ) - Return (BUF0) - } - - Method (_STA) - { - If (LEqual (\S1EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - -Scope (\_SB.PCI0.I2C2) -{ - /* Maxim Audio Codec */ - Device (MAXM) /* Audio Codec driver I2C */ - { - Name (_ADR, 0) - Name (_HID, AUDIO_CODEC_HID) - Name (_CID, AUDIO_CODEC_CID) - Name (_DDN, AUDIO_CODEC_DDN) - Name (_UID, 1) - - /* Add DT style bindings with _DSD */ - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* set maxim micbias to 2.8v */ - Package () { "maxim,micbias", 3 }, - } - }) - - Method(_CRS, 0x0, NotSerialized) - { - Name(SBUF,ResourceTemplate () - { - I2CSerialBus( - AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ - ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ - 400000, /* ConnectionSpeed: in Hz */ - AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ - "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ - ) - - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } - } ) - Return (SBUF) - } - - Method (_STA) - { - If (LEqual (\S2EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - } - Device (TISW) /* TI Switch driver I2C */ - { - Name (_ADR, 0) - Name (_HID, TI_SWITCH_HID) - Name (_CID, TI_SWITCH_CID) - Name (_DDN, TI_SWITCH_DDN) - Name (_UID, 1) - - /* Add DT style bindings with _DSD */ - Name (_DSD, Package () { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - /* set ti micbias to 2.8v */ - Package () { "ti,micbias", 7 }, - } - }) - - Method(_CRS, 0x0, NotSerialized) - { - Name(SBUF,ResourceTemplate () - { - I2CSerialBus( - TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ - ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ - 400000, /* ConnectionSpeed: in Hz */ - AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ - "\\_SB.PCI0.I2C2", /* ResourceSource: I2C bus controller name */ - ) - - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSW") { BOARD_JACK_TI_GPIO_INDEX } - - } ) - Return (SBUF) - } - - Method (_STA) - { - Return (0xF) - } - } -} - -Scope (\_SB.PCI0.I2C6) -{ - Device (ETPA) - { - Name (_HID, "ELAN0000") - Name (_DDN, "Elan Touchpad") - Name (_UID, 3) - Name (ISTP, 1) /* Touchpad */ - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - 0x15, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C6", /* ResourceSource */ - ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } - }) - - Method (_STA) - { - If (LEqual (\S6EN, 1)) { - Return (0xF) - } Else { - Return (0x0) - } - } - - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) - - /* Allow device to power off in S0 */ - Name (_S0W, 4) - } -} - -Scope (\_SB.PCI0.LPEA) -{ - Name (GBUF, ResourceTemplate () - { - /* Jack Detect (index 0) */ - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSE") { BOARD_JACK_MAXIM_GPIO_INDEX } - }) } Scope (\_SB.GPNC) @@ -225,3 +42,6 @@ { } } + +/* Variant-specific I2C devices */ +#include <variant/acpi/mainboard.asl> diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl index 34ae348..1962f22 100644 --- a/src/mainboard/google/cyan/acpi/superio.asl +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -16,7 +16,7 @@ /* mainboard configuration */ #include <ec.h> -#include <onboard.h> +#include <variant/onboard.h> #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ diff --git a/src/mainboard/google/cyan/acpi/touchscreen_elan.asl b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl new file mode 100644 index 0000000..7100120 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/touchscreen_elan.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C1) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen ") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Method(_CRS, 0x0, NotSerialized) + { + Name(BUF0,ResourceTemplate () + { + I2CSerialBus( + 0x10, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C1", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_TOUCH_IRQ + } + + } ) + Return (BUF0) + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/cyan/acpi/trackpad_elan.asl b/src/mainboard/google/cyan/acpi/trackpad_elan.asl new file mode 100644 index 0000000..f89e1bc --- /dev/null +++ b/src/mainboard/google/cyan/acpi/trackpad_elan.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.PCI0.I2C6", /* ResourceSource */ + ) + GpioInt (Level, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_TRACKPAD_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} diff --git a/src/mainboard/google/cyan/board_info.txt b/src/mainboard/google/cyan/board_info.txt index 8815b36..98f3d76 100644 --- a/src/mainboard/google/cyan/board_info.txt +++ b/src/mainboard/google/cyan/board_info.txt @@ -1,5 +1,5 @@ Vendor name: Google -Board name: Cyan Braswell reference board +Board name: Cyan Braswell baseboard Category: laptop ROM protocol: SPI ROM socketed: n diff --git a/src/mainboard/google/cyan/boardid.c b/src/mainboard/google/cyan/boardid.c index 15d26dc..0d47c43 100644 --- a/src/mainboard/google/cyan/boardid.c +++ b/src/mainboard/google/cyan/boardid.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright(C) 2013 Google Inc. + * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c index e247c98..026a68d 100644 --- a/src/mainboard/google/cyan/ramstage.c +++ b/src/mainboard/google/cyan/ramstage.c @@ -15,7 +15,7 @@ #include <soc/ramstage.h> #include <boardid.h> -#include "onboard.h" +#include <variant/onboard.h> void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 98e4873..75c1890 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -25,7 +25,7 @@ #include <soc/pm.h> #include <soc/gpio.h> -#include "onboard.h" +#include <variant/onboard.h> /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc similarity index 100% rename from src/mainboard/google/cyan/spd/Makefile.inc rename to src/mainboard/google/cyan/variants/cyan/Makefile.inc diff --git a/src/mainboard/google/cyan/variants/cyan/board_info.txt b/src/mainboard/google/cyan/variants/cyan/board_info.txt new file mode 100644 index 0000000..b1138ca --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cyan +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/variants/cyan/devicetree.cb similarity index 100% rename from src/mainboard/google/cyan/devicetree.cb rename to src/mainboard/google/cyan/variants/cyan/devicetree.cb diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/variants/cyan/gpio.c similarity index 99% rename from src/mainboard/google/cyan/gpio.c rename to src/mainboard/google/cyan/variants/cyan/gpio.c index 9f9a3ae..bb7a148 100644 --- a/src/mainboard/google/cyan/gpio.c +++ b/src/mainboard/google/cyan/variants/cyan/gpio.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include "irqroute.h" +#include <mainboard/google/cyan/irqroute.h> #include <soc/gpio.h> #include <stdlib.h> diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..f0550ee --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/dptf.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 49 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 85 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 49 +#define DPTF_TSR2_CRITICAL 75 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x400, "mA", 0 }, /* 1.0A (MAX) */ + Package () { 0, 0, 0, 0, 12, 0x300, "mA", 0 }, /* 0.77A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 4, 0x100, "mA", 0 }, /* 0.25A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 2000, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..194a4a1 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/acpi/mainboard.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Matt DeVillier + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Elan touchscreen */ +#include <mainboard/google/cyan/acpi/touchscreen_elan.asl> + +/* Elan trackpad */ +#include <mainboard/google/cyan/acpi/trackpad_elan.asl> + +/* Maxim audio codec */ +#include <mainboard/google/cyan/acpi/codec_maxim.asl> diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h similarity index 89% rename from src/mainboard/google/cyan/onboard.h rename to src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h index 5338b0c..ee826b9 100644 --- a/src/mainboard/google/cyan/onboard.h +++ b/src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h @@ -17,7 +17,7 @@ #ifndef ONBOARD_H #define ONBOARD_H -#include "irqroute.h" +#include <mainboard/google/cyan/irqroute.h> /* * Calculation of gpio based irq. @@ -57,7 +57,7 @@ #define BOARD_TOUCHSCREEN_NAME "touchscreen" #define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) #define BOARD_TOUCHSCREEN_I2C_BUS 0 -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10 /* SD CARD gpio */ @@ -68,12 +68,12 @@ #define AUDIO_CODEC_DDN "Maxim 98090 Codec " #define AUDIO_CODEC_I2C_ADDR 0x10 -#define TI_SWITCH_HID "104C227E" -#define TI_SWITCH_CID "104C227E" -#define TI_SWITCH_DDN "TI SWITCH " +#define TI_SWITCH_HID "104C227E" +#define TI_SWITCH_CID "104C227E" +#define TI_SWITCH_DDN "TI SWITCH " #define TI_SWITCH_I2C_ADDR 0x3B - -#endif #define DPTF_CPU_PASSIVE 88 #define DPTF_CPU_CRITICAL 90 + +#endif diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/variants/cyan/spd.c similarity index 100% rename from src/mainboard/google/cyan/spd/spd.c rename to src/mainboard/google/cyan/variants/cyan/spd.c -- To view, visit https://review.coreboot.org/21126 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Gerrit-Change-Number: 21126 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: soc/intel/braswell: select GENERIC_GPIO_LIB
by Matt DeVillier (Code Review) 21 Aug '17

21 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21125 Change subject: soc/intel/braswell: select GENERIC_GPIO_LIB ...................................................................... soc/intel/braswell: select GENERIC_GPIO_LIB Needed for to-be-added Google Braswell boards which make use of common GPIO library function to determine installed RAM type. Change-Id: Ie9b0c6513f10b252bf0a5014bd038d24879421be Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/21125/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index cc537e7..3decbc7 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -47,6 +47,7 @@ select HAVE_INTEL_FIRMWARE select HAVE_SPI_CONSOLE_SUPPORT select HAVE_FSP_GOP + select GENERIC_GPIO_LIB config VBOOT select VBOOT_STARTS_IN_ROMSTAGE -- To view, visit https://review.coreboot.org/21125 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie9b0c6513f10b252bf0a5014bd038d24879421be Gerrit-Change-Number: 21125 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/cyan: Increase RO coreboot size on flash
by Matt DeVillier (Code Review) 21 Aug '17

21 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21124 Change subject: google/cyan: Increase RO coreboot size on flash ...................................................................... google/cyan: Increase RO coreboot size on flash Commit 05627831826cab096789bd19f004b33a4cd70c0e applied this change to other Google boards, but cyan was left out. Bring cyan in line with other Google boards. Change-Id: Id86bea538a7b82367ea6ddbd3fe3efb1b1c0078d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/21124/1 diff --git a/src/mainboard/google/cyan/chromeos.fmd b/src/mainboard/google/cyan/chromeos.fmd index 113fba6..0c05ce9 100644 --- a/src/mainboard/google/cyan/chromeos.fmd +++ b/src/mainboard/google/cyan/chromeos.fmd @@ -30,8 +30,8 @@ FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x100000 + GBB@0x1000 0x6f000 + COREBOOT(CBFS)@0x70000 0x180000 } } } -- To view, visit https://review.coreboot.org/21124 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id86bea538a7b82367ea6ddbd3fe3efb1b1c0078d Gerrit-Change-Number: 21124 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/cyan: Remove support for pre-EVT board
by Matt DeVillier (Code Review) 21 Aug '17

21 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21123 Change subject: google/cyan: Remove support for pre-EVT board ...................................................................... google/cyan: Remove support for pre-EVT board Cleaning up code to remove support for pre-EVT rev of cyan board. Analogous to what was done for intel/strago in commit 103f00d. Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/mainboard.asl M src/mainboard/google/cyan/gpio.c D src/mainboard/google/cyan/gpio.h D src/mainboard/google/cyan/gpio_pre_evt.c M src/mainboard/google/cyan/onboard.h M src/mainboard/google/cyan/ramstage.c M src/mainboard/google/cyan/smihandler.c 8 files changed, 4 insertions(+), 334 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/21123/1 diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 35e0bb4..43e3c95 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_pre_evt.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index 9d68065..7a4b0ea 100644 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -48,30 +48,11 @@ ) Interrupt (ResourceConsumer, Edge, ActiveLow) { - BOARD_PRE_EVT_TOUCH_IRQ - } - - } ) - Name(BUF1,ResourceTemplate () - { - I2CSerialBus( - 0x10, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C1", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { BOARD_TOUCH_IRQ } } ) - If (LEqual (\BDID, BOARD_EVT)) { - Return (BUF1) - } Else { - Return (BUF0) - } + Return (BUF0) } Method (_STA) diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c index 66c7c2a..9f9a3ae 100644 --- a/src/mainboard/google/cyan/gpio.c +++ b/src/mainboard/google/cyan/gpio.c @@ -17,7 +17,6 @@ #include "irqroute.h" #include <soc/gpio.h> #include <stdlib.h> -#include "gpio.h" /* South East Community */ static const struct soc_gpio_map gpse_gpio_map[] = { @@ -251,7 +250,6 @@ static struct soc_gpio_config gpio_config = { /* BSW */ - /* gpio configuration for EVT board */ .north = gpn_gpio_map, .southeast = gpse_gpio_map, .southwest = gpsw_gpio_map, @@ -260,11 +258,5 @@ struct soc_gpio_config *mainboard_get_gpios(void) { - return get_override_gpios(&gpio_config); -} - -__attribute__((weak)) struct soc_gpio_config *get_override_gpios( - struct soc_gpio_config *config) -{ - return config; + return &gpio_config; } diff --git a/src/mainboard/google/cyan/gpio.h b/src/mainboard/google/cyan/gpio.h deleted file mode 100644 index ab6f9b2..0000000 --- a/src/mainboard/google/cyan/gpio.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef _BOARD_GPIO_H_ -#define _BOARD_GPIO_H_ - -struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config); -#endif diff --git a/src/mainboard/google/cyan/gpio_pre_evt.c b/src/mainboard/google/cyan/gpio_pre_evt.c deleted file mode 100644 index 2aec685..0000000 --- a/src/mainboard/google/cyan/gpio_pre_evt.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" -#include <soc/gpio.h> -#include <stdlib.h> -#include <boardid.h> -#include "onboard.h" -#include "gpio.h" - - -/* South East Community */ -static const struct soc_gpio_map gpse_gpio_map[] = { - Native_M1,/* MF_PLT_CLK0 */ - GPIO_NC, /* 01 PWM1 */ - GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ - GPIO_NC, /* 03 MF_PLT_CLK4 */ - GPIO_NC, /* 04 MF_PLT_CLK3 */ - GPIO_NC, /* PWM0 05 */ - GPIO_NC, /* 06 MF_PLT_CLK5 */ - GPIO_NC, /* 07 MF_PLT_CLK2 */ - GPIO_NC, /* 15 SDMMC2_D3_CD_B */ - Native_M1, /* 16 SDMMC1_CLK */ - NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ - GPIO_NC, /* 18 SDMMC2_D1 */ - GPIO_NC, /* 19 SDMMC2_CLK */ - NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ - GPIO_NC, /* 21 SDMMC2_D2 */ - GPIO_NC, /* 22 SDMMC2_CMD */ - NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ - NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ - GPIO_NC, /* 25 SDMMC2_D0 */ - NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ - NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ - Native_M1, /* 31 SDMMC3_CLK */ - NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ - NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ - NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ - NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ - NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ - Native_M1, /* 46 LPC_CLKRUNB */ - NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ - Native_M1, /* 48 LPC_FRAMEB */ - Native_M1, /* 49 MF_LPC_CLKOUT1 */ - NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ - Native_M1, /* 51 MF_LPC_CLKOUT0 */ - NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ - Native_M1,/* SPI1_MISO */ - Native_M1, /* 61 SPI1_CS0_B */ - Native_M1, /* SPI1_CLK */ - NATIVE_PU20K(1), /* 63 MMC1_D6 */ - Native_M1, /* 62 SPI1_MOSI */ - NATIVE_PU20K(1), /* 65 MMC1_D5 */ - GPIO_NC, /* SPI1_CS1_B 66 */ - NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ - NATIVE_PU20K(1), /* 68 MMC1_D7 */ - GPIO_NC, /* 69 MMC1_RCLK */ - Native_M1, /* 75 GPO USB_OC1_B */ - Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), - /* GPIO_ALERT 77 */ - Native_M1, /* 78 SDMMC3_PWR_EN_B */ - GPIO_NC, /* 79 GPI ILB_SERIRQ */ - Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ - GPIO_NC, /* 82 spkr asummed gpio number */ - Native_M1, /* 83 SUSPWRDNACK */ - SPARE_PIN,/* 84 spare pin */ - Native_M1, /* 85 SDMMC3_1P8_EN */ - GPIO_END -}; - -/* South West Community */ -static const struct soc_gpio_map gpsw_gpio_map[] = { - GPIO_NC, /* 00 FST_SPI_D2 */ - Native_M1, /* 01 FST_SPI_D0 */ - Native_M1, /* 02 FST_SPI_CLK */ - GPIO_NC, /* 03 FST_SPI_D3 */ - GPIO_NC, /* GPO FST_SPI_CS1_B */ - Native_M1, /* 05 FST_SPI_D1 */ - Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_NC, /* 07 FST_SPI_CS2_B */ - GPIO_NC, /* 15 UART1_RTS_B */ - Native_M2, /* 16 UART1_RXD */ - GPIO_NC, /* 17 UART2_RXD */ - GPIO_NC, /* 18 UART1_CTS_B */ - GPIO_NC, /* 19 UART2_RTS_B */ - Native_M2, /* 20 UART1_TXD */ - GPIO_NC, /* 21 UART2_TXD */ - GPIO_NC, /* 22 UART2_CTS_B */ - GPIO_NC, /* 30 MF_HDA_CLK */ - GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ - GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ - GPIO_NC, /* 33 MF_HDA_SDO */ - GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 34 MF_HDA_DOCKRSTB */ - GPIO_NC, /* 35 MF_HDA_SYNC */ - GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ - NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ - GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ - GPIO_NC, /* 52 I2C_NFC_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ - GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ - NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ - GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ - GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), - /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ - GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ - Native_M1, /* 79 MF_SMB_ALERTB */ - GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ - /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ - Native_M1, /* 90 PCIE_CLKREQ0B */ - GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ - Native_M1, /* 92 GP_SSP_2_CLK */ - NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ - Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ - Native_M1, /* 96 GP_SSP_2_FS */ - NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ - GPIO_END -}; - - -/* North Community */ -static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , - UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ - GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), - /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ - GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ - GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ - GPIO_NC, /* 22 GPIO_SUS4 */ - GPIO_NC, - /* 23 SEC_GPIO_SUS8 */ - Native_M6, /* 24 GPIO_SUS2 */ - GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ - Native_M1, /* 26 CX_PREQ_B */ - GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */ - Native_M1, /* 30 TRST_B */ - Native_M1, /* 31 TCK */ - GPIO_SKIP, /* 32 PROCHOT_B */ - GPIO_SKIP, /* 33 SVID0_DATA */ - Native_M1, /* 34 TMS */ - GPIO_NC, /* 35 CX_PRDY_B_2 */ - GPIO_NC, /* 36 TDO_2 */ - Native_M1, /* 37 CX_PRDY_B */ - GPIO_SKIP, /* 38 SVID0_ALERT_B */ - Native_M1, /* 39 TDO */ - GPIO_SKIP, /* 40 SVID0_CLK */ - Native_M1, /* 41 TDI */ - Native_M2, /* 45 GP_CAMERASB05 */ - Native_M2, /* 46 GP_CAMERASB02 */ - Native_M2, /* 47 GP_CAMERASB08 */ - Native_M2, /* 48 GP_CAMERASB00 */ - Native_M2, /* 49 GP_CAMERASBO6 */ - GPIO_NC, /* 50 GP_CAMERASB10 */ - Native_M2, /* 51 GP_CAMERASB03 */ - GPIO_NC, /* 52 GP_CAMERASB09 */ - Native_M2, /* 53 GP_CAMERASB01 */ - Native_M2, /* 54 GP_CAMERASB07 */ - GPIO_NC, /* 55 GP_CAMERASB11 */ - Native_M2, /* 56 GP_CAMERASB04 */ - GPIO_NC, /* 60 PANEL0_BKLTEN */ - GPIO_NC, /* 61 HV_DDI0_HPD */ - NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ - Native_M1, /* 63 PANEL1_BKLTCTL */ - NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ - GPIO_NC, /* 65 PANEL0_BKLTCTL */ - GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ - NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ - NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ - Native_M1, /* 69 PANEL1_VDDEN */ - Native_M1, /* 70 PANEL1_BKLTEN */ - GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ - GPIO_NC, /* 72 PANEL0_VDDEN */ - GPIO_END -}; - -/* East Community */ -static const struct soc_gpio_map gpe_gpio_map[] = { - Native_M1, /* 00 PMU_SLP_S3_B */ - GPIO_NC, /* 01 PMU_BATLOW_B */ - Native_M1, /* 02 SUS_STAT_B */ - Native_M1, /* 03 PMU_SLP_S0IX_B */ - Native_M1, /* 04 PMU_AC_PRESENT */ - Native_M1, /* 05 PMU_PLTRST_B */ - Native_M1, /* 06 PMU_SUSCLK */ - GPIO_NC, /* 07 PMU_SLP_LAN_B */ - Native_M1, /* 08 PMU_PWRBTN_B */ - Native_M1, /* 09 PMU_SLP_S4_B */ - NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ - GPIO_NC, /* 11 PMU_WAKE_LAN_B */ - GPIO_NC, /* 15 MF_GPIO_3 */ - GPIO_NC, /* 16 MF_GPIO_7 */ - GPIO_NC, /* 17 MF_I2C1_SCL */ - GPIO_NC, /* 18 MF_GPIO_1 */ - GPIO_NC, /* 19 MF_GPIO_5 */ - GPIO_NC, /* 20 MF_GPIO_9 */ - GPIO_NC, /* 21 MF_GPIO_0 */ - GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ - GPIO_NC, /* 23 MF_GPIO_8 */ - GPIO_NC, /* 24 MF_GPIO_2 */ - GPIO_NC, /* 25 MF_GPIO_6 */ - GPIO_NC, /* 26 MF_I2C1_SDA */ - GPIO_END -}; - -static struct soc_gpio_config gpio_config = { - /* BSW */ - /* gpio configuration for pre-evt board */ - .north = gpn_gpio_map, - .southeast = gpse_gpio_map, - .southwest = gpsw_gpio_map, - .east = gpe_gpio_map -}; - -struct soc_gpio_config *get_override_gpios(struct soc_gpio_config *config) -{ - if (board_id() == BOARD_PRE_EVT) - return &gpio_config; - - return config; -} diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h index 1347d41..5338b0c 100644 --- a/src/mainboard/google/cyan/onboard.h +++ b/src/mainboard/google/cyan/onboard.h @@ -37,17 +37,13 @@ /* ToDO: change kbd irq to gpio bank index */ #define BOARD_I8042_IRQ 182 #define BOARD_TOUCH_IRQ 184 -#define BOARD_PRE_EVT_TOUCH_IRQ 156 - /* SCI: Gpio index in N bank */ #define BOARD_SCI_GPIO_INDEX 15 /* Trackpad: Gpio index in N bank */ #define BOARD_TRACKPAD_GPIO_INDEX 18 -/* Touch: Gpio index in SW bank */ -#define BOARD_TOUCH_GPIO_INDEX 76 -/* EVT Touch: Gpio index in N bank */ -#define BOARD_EVT_TOUCH_GPIO_INDEX 19 +/* Touch: Gpio index in N bank */ +#define BOARD_TOUCH_GPIO_INDEX 19 /* TI Audio: Gpio index in SW bank */ #define BOARD_JACK_TI_GPIO_INDEX 34 /* MAXIM Audio: Gpio index in SE bank */ @@ -77,8 +73,6 @@ #define TI_SWITCH_DDN "TI SWITCH " #define TI_SWITCH_I2C_ADDR 0x3B -#define BOARD_PRE_EVT 0x01 -#define BOARD_EVT 0x02 #endif #define DPTF_CPU_PASSIVE 88 diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c index 65e78f5..e247c98 100644 --- a/src/mainboard/google/cyan/ramstage.c +++ b/src/mainboard/google/cyan/ramstage.c @@ -19,6 +19,4 @@ void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { - if (board_id() == BOARD_PRE_EVT) - params->ChvSvidConfig = SVID_CONFIG3; } diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 1a0fcee..98e4873 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -152,13 +152,6 @@ /* Clear pending events that may trigger immediate wake */ while (google_chromeec_get_event() != 0) ; - - if (smm_get_gnvs()->bdid == BOARD_PRE_EVT) { - /* Set LPC lines to low power in S3/S5. */ - if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5)) - lpc_set_low_power(); - } - #endif } -- To view, visit https://review.coreboot.org/21123 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f Gerrit-Change-Number: 21123 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/cyan: Fix Touchscreen Interrupt
by Matt DeVillier (Code Review) 21 Aug '17

21 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21122 Change subject: google/cyan: Fix Touchscreen Interrupt ...................................................................... google/cyan: Fix Touchscreen Interrupt Cherry-pick from Chromium commit 1138727. Elan touchscreen driver expects the first gpio resource in asl to be the reset line. The driver considers the gpio based irq line as reset gpio resource and changes the direction to output. This will cause irq registration to fail. Solution is to pass Interrupt resource for touchscreen irq instead of GpioInt. Original-Change-Id: Ia72d4ad80117f3c0014098113c9027416026e65e Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/acpi/mainboard.asl M src/mainboard/google/cyan/onboard.h 2 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/21122/1 diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl index 31b9090..9d68065 100644 --- a/src/mainboard/google/cyan/acpi/mainboard.asl +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -46,8 +46,10 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPSW") { BOARD_TOUCH_GPIO_INDEX } + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_PRE_EVT_TOUCH_IRQ + } } ) Name(BUF1,ResourceTemplate () @@ -59,8 +61,10 @@ AddressingMode7Bit, /* AddressingMode */ "\\_SB.PCI0.I2C1", /* ResourceSource */ ) - GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, - "\\_SB.GPNC") { BOARD_EVT_TOUCH_GPIO_INDEX } + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TOUCH_IRQ + } } ) If (LEqual (\BDID, BOARD_EVT)) { diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h index f03f1df..1347d41 100644 --- a/src/mainboard/google/cyan/onboard.h +++ b/src/mainboard/google/cyan/onboard.h @@ -36,6 +36,8 @@ */ /* ToDO: change kbd irq to gpio bank index */ #define BOARD_I8042_IRQ 182 +#define BOARD_TOUCH_IRQ 184 +#define BOARD_PRE_EVT_TOUCH_IRQ 156 /* SCI: Gpio index in N bank */ -- To view, visit https://review.coreboot.org/21122 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e Gerrit-Change-Number: 21122 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com>

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Change in coreboot[master]: amd/padmelon: Fixes to enable power button
by build bot (Jenkins) (Code Review) 21 Aug '17

21 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21048 ) Change subject: amd/padmelon: Fixes to enable power button ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58982/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14329/ : SUCCESS -- To view, visit https://review.coreboot.org/21048 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b Gerrit-Change-Number: 21048 Gerrit-PatchSet: 8 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 03:48:43 +0000 Gerrit-HasComments: No

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