coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/common: Add functions into common system agent library
by Subrata Banik (Code Review) 21 Aug '17

21 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21133 Change subject: soc/intel/common: Add functions into common system agent library ...................................................................... soc/intel/common: Add functions into common system agent library This patch to add helper functions for memory layout design based on PCI Host Bridge/DRAM registers. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/systemagent/systemagent_def.h M src/soc/intel/common/block/systemagent/systemagent_early.c 4 files changed, 80 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/21133/1 diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 22a2b8d..5f04e36 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -73,7 +73,14 @@ void enable_pam_region(void); /* API to enable Power Aware Interrupt Routing through MCHBAR */ void enable_power_aware_intr(void); - +/* API to get TOLUD base address */ +uint32_t sa_get_tolud_base(void); +/* API to get DSM size */ +size_t sa_get_dsm_size(void); +/* API to get GSM size */ +size_t sa_get_gsm_size(void); +/* API to get DPR size */ +size_t sa_get_dpr_size(void); /* * SoC overrides * diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 206f4a0..cb7af41 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -100,26 +100,6 @@ } /* - * Get DPR size incase CONFIG_SA_ENABLE_DPR is selected by SoC. - */ -static size_t get_dpr_size(void) -{ - uintptr_t dpr_reg; - size_t size = 0; - /* - * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address - * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. - */ - dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); - if (dpr_reg & DPR_EPM) - size = (dpr_reg & DPR_SIZE_MASK) << 16; - - return size; -} - -/* * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable * - 0xc0000 -> top_of_ram : cacheable @@ -159,7 +139,7 @@ int index = *resource_count; if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) - dpr_size = get_dpr_size(); + dpr_size = sa_get_dpr_size(); top_of_ram = (uintptr_t)cbmem_top(); diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h index 29ce9ec..3243c85 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_def.h +++ b/src/soc/intel/common/block/systemagent/systemagent_def.h @@ -19,6 +19,11 @@ /* Device 0:0.0 PCI configuration space */ +#define GGC 0x50 /* GMCH Graphics Control */ +#define G_GMS_OFFSET 0x8 +#define G_GMS_MASK 0xff00 +#define G_GGMS_OFFSET 0x6 +#define G_GGMS_MASK 0xc0 /* DPR register incase CONFIG_SA_ENABLE_DPR is selected by SoC */ #define DPR 0x5c #define DPR_EPM (1 << 2) diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 7cf78e7..7db907a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -132,3 +132,69 @@ bios_reset_cpl |= 3; MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; } + +uint32_t sa_get_tolud_base(void) +{ + /* All regions concerned for have 1 MiB alignment. */ + return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TOLUD), 1*MiB); +} + +static uint16_t sa_get_gcc_reg(void) +{ + uint16_t ggc; + + ggc = pci_read_config32(SA_DEV_ROOT, GGC); + + return ggc; +} + +size_t sa_get_dsm_size(void) +{ + uint32_t dsm_size; + + dsm_size = ((sa_get_gcc_reg() & G_GMS_MASK) >> G_GMS_OFFSET) * 32*MiB; + + return dsm_size; +} + +size_t sa_get_gsm_size(void) +{ + uint32_t gsm_size; + + switch ((sa_get_gcc_reg() & G_GGMS_MASK) >> G_GGMS_OFFSET) { + case 1: + gsm_size = 2*MiB; + break; + case 2: + gsm_size = 4*MiB; + break; + case 3: + gsm_size = 8*MiB; + break; + default: + gsm_size = 0; + break; + } + + return gsm_size; +} + +/* + * Get DPR size incase CONFIG_SA_ENABLE_DPR is selected by SoC. + */ +size_t sa_get_dpr_size(void) +{ + uintptr_t dpr_reg; + size_t size = 0; + /* + * DMA Protected Range can be reserved below TSEG for PCODE patch + * or TXT/BootGuard related data. Rather than report a base address + * the DPR register reports the TOP of the region, which is the same + * as TSEG base. The region size is reported in MiB in bits 11:4. + */ + dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); + if (dpr_reg & DPR_EPM) + size = (dpr_reg & DPR_SIZE_MASK) << 16; + + return size; +} -- To view, visit https://review.coreboot.org/21133 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I95250ef493c9844b8c46528f1f7de8a42cba88a2 Gerrit-Change-Number: 21133 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: nb/intel/*/northbridge.c: add a final() to trigger finalize_smm() at ...
by Paul Menzel (Code Review) 21 Aug '17

21 Aug '17

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/21129 ) Change subject: nb/intel/*/northbridge.c: add a final() to trigger finalize_smm() at boot time ...................................................................... Patch Set 1: (2 comments) Could that method be moved to a generic location? https://review.coreboot.org/#/c/21129/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/21129/1//COMMIT_MSG@10 PS1, Line 10: do have *has* or *does have* https://review.coreboot.org/#/c/21129/1//COMMIT_MSG@20 PS1, Line 20: Only the change on sandybridge is well tested. > The change is only well tested on Sandy Bridge. Maybe add the board/device you used? -- To view, visit https://review.coreboot.org/21129 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 Gerrit-Change-Number: 21129 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 11:18:45 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: mb/asus/kcma-d8, kgde-d16: Don't select SPI_FLASH_WINBOND
by Paul Menzel (Code Review) 21 Aug '17

21 Aug '17

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/21132 ) Change subject: mb/asus/kcma-d8,kgde-d16: Don't select SPI_FLASH_WINBOND ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/21132 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib2de0f384a547240528b18f07327566354164699 Gerrit-Change-Number: 21132 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 11:16:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override
by build bot (Jenkins) (Code Review) 21 Aug '17

21 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21131 ) Change subject: mainboard/google/coral: Add USB2 phy setting override ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58996/ : SUCCESS -- To view, visit https://review.coreboot.org/21131 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I86182969217046361fe915fb4c940bfad69cbf45 Gerrit-Change-Number: 21131 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 11:09:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override
by Tim Chen (Code Review) 21 Aug '17

21 Aug '17

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21131 to look at the new patch set (#2). Change subject: mainboard/google/coral: Add USB2 phy setting override ...................................................................... mainboard/google/coral: Add USB2 phy setting override In order to pass type C USB2 eye diagram, USB2 port#1 PHY register needs to be overridden. port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 BUG=b:64880573 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I86182969217046361fe915fb4c940bfad69cbf45 Signed-off-by: Tim Chen <Tim-Chen(a)quantatw.com> --- M src/mainboard/google/reef/variants/coral/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/21131/2 -- To view, visit https://review.coreboot.org/21131 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I86182969217046361fe915fb4c940bfad69cbf45 Gerrit-Change-Number: 21131 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in libgfxinit[master]: gma: Clear "fence" registers during initialization
by Nico Huber (Code Review) 21 Aug '17

21 Aug '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/20601 ) Change subject: gma: Clear "fence" registers during initialization ...................................................................... gma: Clear "fence" registers during initialization These registers are used to mark certain GTT regions as tiled. Change-Id: Ic2cd61c0c1b42990ed955d7f77a428a2b9dbabd5 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/20601 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-registers.adb M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.adb 3 files changed, 18 insertions(+), 0 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb index 9e52c78..4a22564 100644 --- a/common/hw-gfx-gma-registers.adb +++ b/common/hw-gfx-gma-registers.adb @@ -61,6 +61,21 @@ ---------------------------------------------------------------------------- + procedure Clear_Fences + is + Fence_Regs_Base : constant := + (case Config.CPU is + when Ironlake => 16#00_3000#, + when Sandybridge .. Skylake => 16#10_0000#); + subtype Fence_Range is Registers_Range range 0 .. 63; + begin + for Idx in Fence_Range loop + Regs.Write (Fence_Regs_Base / Register_Width + Idx, 0); + end loop; + end Clear_Fences; + + ---------------------------------------------------------------------------- + procedure Write_GTT (GTT_Page : GTT_Range; Device_Address : GTT_Address_Type; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 63df8be..2a01aab 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -1529,6 +1529,8 @@ Mask_Unset : Word32; Mask_Set : Word32); + procedure Clear_Fences; + pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *"); procedure Write_GTT (GTT_Page : GTT_Range; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 387d6bd..94f3ceb 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -401,6 +401,7 @@ Connectors.Post_All_Off; PLLs.All_Off; Power_And_Clocks.Post_All_Off; + Registers.Clear_Fences; else -- According to PRMs, VGA plane is the only thing -- that's enabled by default after reset. -- To view, visit https://review.coreboot.org/20601 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ic2cd61c0c1b42990ed955d7f77a428a2b9dbabd5 Gerrit-Change-Number: 20601 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>

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Change in libgfxinit[master]: gma: Add a HW.PCI.Dev for dynamic MMIO setup
by Nico Huber (Code Review) 21 Aug '17

21 Aug '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/20600 ) Change subject: gma: Add a HW.PCI.Dev for dynamic MMIO setup ...................................................................... gma: Add a HW.PCI.Dev for dynamic MMIO setup Remove `MMIO_Base` option from Initialize() and try to derive it using libhwbase' PCI mechanism instead. Change-Id: Iacd4d098954bb96c1c6b40fdfb2636191d9517c7 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/20600 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.adb M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads M gfxtest/hw-gfx-gma-gfx_test.adb 6 files changed, 53 insertions(+), 27 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index dea26b8..b4e52f6 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -35,6 +35,8 @@ ---------------------------------------------------------------------------- + Default_MMIO_Base_Set : constant Boolean := Default_MMIO_Base /= 0; + Has_Internal_Display : constant Boolean := Internal_Display /= None; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Has_Presence_Straps : constant Boolean := CPU /= Broxton; diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb index e240152..9e52c78 100644 --- a/common/hw-gfx-gma-registers.adb +++ b/common/hw-gfx-gma-registers.adb @@ -290,11 +290,15 @@ ---------------------------------------------------------------------------- - procedure Set_Register_Base (Base : Word64) + procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0) is begin Regs.Set_Base_Address (Base); - GTT.Set_Base_Address (Base + Config.GTT_Offset); + if GTT_Base = 0 then + GTT.Set_Base_Address (Base + Config.GTT_Offset); + else + GTT.Set_Base_Address (GTT_Base); + end if; end Set_Register_Base; end HW.GFX.GMA.Registers; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index e526417..63df8be 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -1541,10 +1541,10 @@ Post => True; pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *"); - procedure Set_Register_Base (Base : Word64) + procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0) with Global => (Output => Address_State), - Depends => (Address_State => Base), + Depends => (Address_State => (Base, GTT_Base)), Pre => True, Post => True; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 1aecfab..387d6bd 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -1,5 +1,6 @@ -- -- Copyright (C) 2014-2017 secunet Security Networks AG +-- Copyright (C) 2017 Nico Huber <nico.h(a)gmx.de> -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -12,6 +13,11 @@ -- GNU General Public License for more details. -- +with HW.MMIO_Range; +pragma Elaborate_All (HW.MMIO_Range); +with HW.PCI.Dev; +pragma Elaborate_All (HW.PCI.Dev); + with HW.GFX.GMA.Config; with HW.GFX.GMA.Config_Helpers; with HW.GFX.GMA.Registers; @@ -23,8 +29,6 @@ with HW.GFX.GMA.Connector_Info; with HW.GFX.GMA.Pipe_Setup; -with System; - with HW.Debug; with GNAT.Source_Info; @@ -33,15 +37,17 @@ package body HW.GFX.GMA with Refined_State => (State => - (Registers.Address_State, + (Dev.Address_State, + Registers.Address_State, PLLs.State, Panel.Panel_State, Cur_Configs, Allocated_PLLs, HPD_Delay, Wait_For_HPD), Init_State => Initialized, Config_State => Config.Valid_Port_GPU, Device_State => - (Registers.Register_State, Registers.GTT_State)) + (Dev.PCI_State, Registers.Register_State, Registers.GTT_State)) is + pragma Disable_Atomic_Synchronization; subtype Port_Name is String (1 .. 8); type Port_Name_Array is array (Port_Type) of Port_Name; @@ -55,6 +61,8 @@ HDMI2 => "HDMI2 ", HDMI3 => "HDMI3 ", Analog => "Analog "); + + package Dev is new HW.PCI.Dev (PCI.Address'(0, 2, 0)); package Display_Controller renames Pipe_Setup; @@ -287,8 +295,7 @@ ---------------------------------------------------------------------------- procedure Initialize - (MMIO_Base : in Word64 := 0; - Write_Delay : in Word64 := 0; + (Write_Delay : in Word64 := 0; Clean_State : in Boolean := False; Success : out Boolean) with @@ -299,12 +306,15 @@ Input => (Time.State), Output => - (Registers.Address_State, + (Dev.Address_State, + Registers.Address_State, PLLs.State, Panel.Panel_State, Cur_Configs, Allocated_PLLs, HPD_Delay, Wait_For_HPD, Initialized)) is use type HW.Word64; + + PCI_MMIO_Base, PCI_GTT_Base : Word64; Now : constant Time.T := Time.Now; @@ -345,14 +355,32 @@ (Port => Disabled, Framebuffer => HW.GFX.Default_FB, Mode => HW.GFX.Invalid_Mode)); - Registers.Set_Register_Base - (if MMIO_Base /= 0 then - MMIO_Base - else - Config.Default_MMIO_Base); PLLs.Initialize; - Check_Platform (Success); + Dev.Initialize (Success); + + if Success then + Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => Config.GTT_Offset); + Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => Config.GTT_Offset); + if PCI_MMIO_Base /= 0 and PCI_GTT_Base /= 0 then + Registers.Set_Register_Base (PCI_MMIO_Base, PCI_GTT_Base); + else + pragma Debug (Debug.Put_Line + ("ERROR: Couldn't map resoure0.")); + Registers.Set_Register_Base (Config.Default_MMIO_Base); + Success := Config.Default_MMIO_Base_Set; + end if; + else + pragma Debug (Debug.Put_Line + ("WARNING: Couldn't initialize PCI dev.")); + Registers.Set_Register_Base (Config.Default_MMIO_Base); + Success := Config.Default_MMIO_Base_Set; + end if; + + if Success then + Check_Platform (Success); + end if; + if not Success then pragma Debug (Debug.Put_Line ("ERROR: Incompatible CPU or PCH.")); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index c8fc398..8285dcb 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -62,8 +62,7 @@ VGA_PLANE_FRAMEBUFFER_OFFSET : constant := 16#ffff_ffff#; procedure Initialize - (MMIO_Base : in Word64 := 0; - Write_Delay : in Word64 := 0; + (Write_Delay : in Word64 := 0; Clean_State : in Boolean := False; Success : out Boolean) with diff --git a/gfxtest/hw-gfx-gma-gfx_test.adb b/gfxtest/hw-gfx-gma-gfx_test.adb index b7060ec..ad396fd 100644 --- a/gfxtest/hw-gfx-gma-gfx_test.adb +++ b/gfxtest/hw-gfx-gma-gfx_test.adb @@ -165,15 +165,8 @@ end if; Screen.Set_Base_Address (Res_Addr); - Dev.Map (Res_Addr, PCI.Res0); - if Res_Addr = 0 then - Debug.Put_Line ("Failed to map PCI resource0."); - return; - end if; - GMA.Initialize - (MMIO_Base => Res_Addr, - Clean_State => True, + (Clean_State => True, Success => Initialized); if Initialized then -- To view, visit https://review.coreboot.org/20600 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iacd4d098954bb96c1c6b40fdfb2636191d9517c7 Gerrit-Change-Number: 20600 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>

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Change in libgfxinit[master]: gma: Move GTT constants into GMA.Config
by Nico Huber (Code Review) 21 Aug '17

21 Aug '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/20599 ) Change subject: gma: Move GTT constants into GMA.Config ...................................................................... gma: Move GTT constants into GMA.Config Change-Id: Ie4b017f26b658c1818f90701089ce5d3171e4953 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/20599 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.adb M common/hw-gfx-gma-registers.ads 3 files changed, 22 insertions(+), 23 deletions(-) Approvals: Nico Huber: Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index f40054c..dea26b8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -268,4 +268,20 @@ HDMI_Max_Clock_24bpp : constant Frequency_Type := (if CPU >= Haswell then 300_000_000 else 225_000_000); + ---------------------------------------------------------------------------- + + GTT_Offset : constant := (case CPU is + when Ironlake .. Haswell => 16#0020_0000#, + when Broadwell .. Skylake => 16#0080_0000#); + + GTT_Size : constant := (case CPU is + when Ironlake .. Haswell => 16#0020_0000#, + -- Limit Broadwell to 4MiB to have a stable + -- interface (i.e. same number of entries): + when Broadwell .. Skylake => 16#0040_0000#); + + GTT_PTE_Size : constant := (case CPU is + when Ironlake .. Haswell => 4, + when Broadwell .. Skylake => 8); + end HW.GFX.GMA.Config; diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb index 3c4ad57..e240152 100644 --- a/common/hw-gfx-gma-registers.adb +++ b/common/hw-gfx-gma-registers.adb @@ -12,16 +12,15 @@ -- GNU General Public License for more details. -- -with System.Storage_Elements; - with HW.Time; with HW.MMIO_Range; pragma Elaborate_All (HW.MMIO_Range); +with HW.GFX.GMA.Config; + with HW.Debug; with GNAT.Source_Info; -use type System.Address; use type HW.Word64; package body HW.GFX.GMA.Registers @@ -47,28 +46,13 @@ ---------------------------------------------------------------------------- - GTT_Offset : constant := (case Config.CPU is - when Ironlake .. Haswell => 16#0020_0000#, - when Broadwell .. Skylake => 16#0080_0000#); - - GTT_Size : constant := (case Config.CPU is - when Ironlake .. Haswell => 16#0020_0000#, - -- Limit Broadwell to 4MiB to have a stable - -- interface (i.e. same number of entries): - when Broadwell .. Skylake => 16#0040_0000#); - - GTT_PTE_Size : constant := (case Config.CPU is - when Ironlake .. Haswell => 4, - when Broadwell .. Skylake => 8); - - - type GTT_PTE_Type is mod 2 ** (GTT_PTE_Size * 8); + type GTT_PTE_Type is mod 2 ** (Config.GTT_PTE_Size * 8); type GTT_Registers_Type is array (GTT_Range) of GTT_PTE_Type with Volatile_Components, - Size => GTT_Size * 8; + Size => Config.GTT_Size * 8; package GTT is new MMIO_Range - (Base_Addr => Config.Default_MMIO_Base + GTT_Offset, + (Base_Addr => Config.Default_MMIO_Base + Config.GTT_Offset, Element_T => GTT_PTE_Type, Index_T => GTT_Range, Array_T => GTT_Registers_Type); @@ -310,7 +294,7 @@ is begin Regs.Set_Base_Address (Base); - GTT.Set_Base_Address (Base + GTT_Offset); + GTT.Set_Base_Address (Base + Config.GTT_Offset); end Set_Register_Base; end HW.GFX.GMA.Registers; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index f3825ea..e526417 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -14,7 +14,6 @@ with System; with HW.GFX.GMA; -with HW.GFX.GMA.Config; private package HW.GFX.GMA.Registers with -- To view, visit https://review.coreboot.org/20599 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie4b017f26b658c1818f90701089ce5d3171e4953 Gerrit-Change-Number: 20599 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>

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Change in libgfxinit[master]: gfx_test: Update to use *libhwbase* new PCI interface
by Nico Huber (Code Review) 21 Aug '17

21 Aug '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/20598 ) Change subject: gfx_test: Update to use *libhwbase* new PCI interface ...................................................................... gfx_test: Update to use *libhwbase* new PCI interface Thereby, move `gfx_test` into HW.GFX.GMA to make package dependencies easier to handle. Change-Id: Ie8a1251354b4fff57eef8c4bada8b49aa04ef382 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/20598 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M README.md M gfxtest/Makefile.inc D gfxtest/gfx_test.ads M gfxtest/gfx_test_main.adb R gfxtest/hw-gfx-gma-gfx_test.adb A gfxtest/hw-gfx-gma-gfx_test.ads 6 files changed, 58 insertions(+), 78 deletions(-) Approvals: Nico Huber: Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/README.md b/README.md index 998b8cc..7bfb504 100644 --- a/README.md +++ b/README.md @@ -40,16 +40,16 @@ You can either write your own `.config`, link one of the shipped files in `configs/`, e.g.: - $ ln -s configs/posix libhwbase/.config + $ ln -s configs/linux libhwbase/.config or overwrite the config filename by specifying `cnf=<configfile>` on the make command line. -Let's install *libhwbase*. We'll need `configs/posix` to build regular +Let's install *libhwbase*. We'll need `configs/linux` to build regular Linux executables: $ cd libhwbase - $ make cnf=configs/posix install + $ make cnf=configs/linux install By default this installs into a new subdirectory `dest`. You can however overwrite this decision by specifying `DESTDIR=`. @@ -80,11 +80,12 @@ command line or with *i915* blacklisted). After running *i915* it only works by chance. -When running `gfx_test` (as root), it will ask for a single argument: -The path to a sysfs PCI-device node, where it will find the graphics -hardware. Usually this is PCI device 00:02.0: +When running `gfx_test` (as root), it will access the graphics hard- +ware through the sysfs PCI interface. The path is - $ sudo build/gfx_test /sys/devices/pci0000:00/0000:00:02.0/ + /sys/devices/pci0000:00/0000:00:02.0/ + +for all supported platforms. If you chose the right config above, you should be presented with a nice test image. However, `gfx_test` is one-way only: The graphics diff --git a/gfxtest/Makefile.inc b/gfxtest/Makefile.inc index 158665a..ff7fa8e 100644 --- a/gfxtest/Makefile.inc +++ b/gfxtest/Makefile.inc @@ -1,4 +1,4 @@ -gfxinit-y += gfx_test.adb -gfxinit-y += gfx_test.ads +gfxinit-y += hw-gfx-gma-gfx_test.adb +gfxinit-y += hw-gfx-gma-gfx_test.ads gfxinit-main-y = gfx_test_main.adb diff --git a/gfxtest/gfx_test.ads b/gfxtest/gfx_test.ads deleted file mode 100644 index 52e268e..0000000 --- a/gfxtest/gfx_test.ads +++ /dev/null @@ -1,5 +0,0 @@ -package GFX_Test is - - procedure Main; - -end GFX_Test; diff --git a/gfxtest/gfx_test_main.adb b/gfxtest/gfx_test_main.adb index d3666c9..2e1d5da 100644 --- a/gfxtest/gfx_test_main.adb +++ b/gfxtest/gfx_test_main.adb @@ -1,6 +1,6 @@ -with GFX_Test; +with HW.GFX.GMA.GFX_Test; procedure GFX_Test_Main is begin - GFX_Test.Main; + HW.GFX.GMA.GFX_Test.Main; end GFX_Test_Main; diff --git a/gfxtest/gfx_test.adb b/gfxtest/hw-gfx-gma-gfx_test.adb similarity index 69% rename from gfxtest/gfx_test.adb rename to gfxtest/hw-gfx-gma-gfx_test.adb index e7fb80c..b7060ec 100644 --- a/gfxtest/gfx_test.adb +++ b/gfxtest/hw-gfx-gma-gfx_test.adb @@ -1,24 +1,18 @@ -with System.Storage_Elements; +with Ada.Unchecked_Conversion; with Ada.Command_Line; with Interfaces.C; -with HW.File; with HW.Debug; +with HW.PCI.Dev; +with HW.MMIO_Range; with HW.GFX.GMA; with HW.GFX.GMA.Display_Probing; -use HW; -use HW.GFX; +package body HW.GFX.GMA.GFX_Test +is + pragma Disable_Atomic_Synchronization; -package body GFX_Test is - - MMIO_Size : constant := 2 * 1024 * 1024; - subtype MMIO_Range is Natural range 0 .. MMIO_Size - 1; - subtype MMIO_Buffer is Buffer (MMIO_Range); - MMIO_Dummy : MMIO_Buffer - with - Alignment => 16#1000#, - Volatile; + package Dev is new PCI.Dev (PCI.Address'(0, 2, 0)); type Pixel_Type is record Red : Byte; @@ -34,16 +28,23 @@ Alpha at 3 range 0 .. 7; end record; + function Pixel_To_Word (P : Pixel_Type) return Word32 + with + SPARK_Mode => Off + is + function To_Word is new Ada.Unchecked_Conversion (Pixel_Type, Word32); + begin + return To_Word (P); + end Pixel_To_Word; + Max_W : constant := 4096; Max_H : constant := 2160; FB_Align : constant := 16#0004_0000#; - type Screen_Type is - array (0 .. 3 * (Max_W * Max_H + FB_Align / 4) - 1) of Pixel_Type; + subtype Screen_Index is Natural range + 0 .. 3 * (Max_W * Max_H + FB_Align / 4) - 1; + type Screen_Type is array (Screen_Index) of Word32; - Screen : Screen_Type - with - Alignment => 16#1000#, - Volatile; + package Screen is new MMIO_Range (0, Word32, Screen_Index, Screen_Type); Pipes : GMA.Pipe_Configs; @@ -76,7 +77,6 @@ (Framebuffer : Framebuffer_Type; Pipe : GMA.Pipe_Index) is - use type HW.Word32; P : Pixel_Type; -- We have pixel offset wheras the framebuffer has a byte offset Offset_Y : Natural := Natural (Framebuffer.Offset / 4); @@ -90,7 +90,7 @@ else P := Fill (X, Y, Framebuffer, Pipe); end if; - Screen (Offset) := P; + Screen.Write (Offset, Pixel_To_Word (P)); Offset := Offset + 1; end loop; Offset_Y := Offset_Y + Natural (Framebuffer.Stride); @@ -102,8 +102,6 @@ Mode : in Mode_Type; Offset : in out Word32) is - use type HW.Int32; - use type HW.Word32; begin Offset := (Offset + FB_Align - 1) and not (FB_Align - 1); FB := @@ -119,7 +117,7 @@ is use type HW.GFX.GMA.Port_Type; - Offset : HW.Word32 := 0; + Offset : Word32 := 0; begin GMA.Display_Probing.Scan_Ports (Pipes); @@ -135,65 +133,46 @@ GMA.Dump_Configs (Pipes); end Prepare_Configs; - procedure Print_Usage is - begin - Debug.Put_Line - ("Usage: " & Ada.Command_Line.Command_Name & " <sysfs-pci-path>"); - Debug.New_Line; - end Print_Usage; - procedure Main is - use System.Storage_Elements; - use type HW.GFX.GMA.Port_Type; + use type HW.Word64; use type Interfaces.C.int; - MMIO_Mapped, - Screen_Mapped, + Res_Addr : Word64; + + Dev_Init, Initialized : Boolean; function iopl (level : Interfaces.C.int) return Interfaces.C.int; pragma Import (C, iopl, "iopl"); begin - if Ada.Command_Line.Argument_Count /= 1 then - Print_Usage; - return; - end if; - if iopl (3) /= 0 then Debug.Put_Line ("Failed to change i/o privilege level."); return; end if; - File.Map - (Path => Ada.Command_Line.Argument (1) & "/resource0", - Addr => Word64 (To_Integer (MMIO_Dummy'Address)), - Len => MMIO_Dummy'Size / 8, - Readable => True, - Writable => True, - Success => MMIO_Mapped); - if not MMIO_Mapped then - Debug.Put_Line - ("Failed to map '" & Ada.Command_Line.Argument (1) & "/resource0'."); + Dev.Initialize (Dev_Init); + if not Dev_Init then + Debug.Put_Line ("Failed to map PCI config."); return; end if; - File.Map - (Path => Ada.Command_Line.Argument (1) & "/resource2", - Addr => Word64 (To_Integer (Screen'Address)), - Len => Screen'Size / 8, - Readable => True, - Writable => True, - Success => Screen_Mapped); - if not Screen_Mapped then - Debug.Put_Line - ("Failed to map '" & Ada.Command_Line.Argument (1) & "/resource2'."); + Dev.Map (Res_Addr, PCI.Res2, WC => True); + if Res_Addr = 0 then + Debug.Put_Line ("Failed to map PCI resource2."); + return; + end if; + Screen.Set_Base_Address (Res_Addr); + + Dev.Map (Res_Addr, PCI.Res0); + if Res_Addr = 0 then + Debug.Put_Line ("Failed to map PCI resource0."); return; end if; GMA.Initialize - (MMIO_Base => Word64 (To_Integer (MMIO_Dummy'Address)), + (MMIO_Base => Res_Addr, Clean_State => True, Success => Initialized); @@ -212,4 +191,4 @@ end if; end Main; -end GFX_Test; +end HW.GFX.GMA.GFX_Test; diff --git a/gfxtest/hw-gfx-gma-gfx_test.ads b/gfxtest/hw-gfx-gma-gfx_test.ads new file mode 100644 index 0000000..71da057 --- /dev/null +++ b/gfxtest/hw-gfx-gma-gfx_test.ads @@ -0,0 +1,5 @@ +package HW.GFX.GMA.GFX_Test is + + procedure Main; + +end HW.GFX.GMA.GFX_Test; -- To view, visit https://review.coreboot.org/20598 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie8a1251354b4fff57eef8c4bada8b49aa04ef382 Gerrit-Change-Number: 20598 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>

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Change in coreboot[master]: soc/braswell/lpe: add resource allocation for BAR1
by Nico Huber (Code Review) 21 Aug '17

21 Aug '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/21103 ) Change subject: soc/braswell/lpe: add resource allocation for BAR1 ...................................................................... Patch Set 1: (2 comments) It would also be nice to know the state while the OS is running. No idea how to be sure that you read from HW under Windows, but we can check Linux at least. This should work: # lspci -x -s 15.0 or maybe # setpci 15.0 0x14.L # setpci 15.0 0x18.L (assuming 15.0 is this dev) https://review.coreboot.org/#/c/21103/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/21103/1//COMMIT_MSG@15 PS1, Line 15: TEST: boot google/cyan, observe MMIO values at BAR1 match > I used RW Everything on Windows; it showed that the VID/SID, BAR0 address, No idea about RW Everything. I want to be sure that the hardware also knows about the configured MMIO range. Best option is to dump the register late in coreboot. https://review.coreboot.org/#/c/21103/1/src/soc/intel/braswell/lpe.c File src/soc/intel/braswell/lpe.c: https://review.coreboot.org/#/c/21103/1/src/soc/intel/braswell/lpe.c@162 PS1, Line 162: lpe_enable_acpi_mode(dev); maybe dump BAR1/BAR2 here, e.g. printk(BIOS_DEBUG, "lpe BAR1 0x%08x\n", pci_read_config32(dev, PCI_BASE_ADDRESS_1)); printk(BIOS_DEBUG, "lpe BAR2 0x%08x\n", pci_read_config32(dev, PCI_BASE_ADDRESS_2)); -- To view, visit https://review.coreboot.org/21103 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaa68319da5fb999fe8d73792eaee692cce60c8a2 Gerrit-Change-Number: 21103 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 10:52:09 +0000 Gerrit-HasComments: Yes

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coreboot-gerrit August 2017