coreboot-gerrit August 2017

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Change in coreboot[master]: Boards w/ Winbond superios: Use common config entry code
by Martin Roth (Code Review) 21 Aug '17

21 Aug '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/20989 ) Change subject: Boards w/ Winbond superios: Use common config entry code ...................................................................... Boards w/ Winbond superios: Use common config entry code Six mainboards with Winbond superios directly configure them in romstage.c. All use the common Winbond romstage code. Change them to use the common config entry code to allow for code refactoring such as [1]. Build tested. [1] https://review.coreboot.org/20988 Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562 Signed-off-by: Keith Hui <buurin(a)gmail.com> Reviewed-on: https://review.coreboot.org/20989 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c 6 files changed, 20 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 87fec55..2ead963 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -94,7 +94,7 @@ { u8 reg; - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); @@ -104,9 +104,9 @@ /* We have all RESTOUT and even some reserved bits, too. */ reg = pnp_read_config(SERIAL_DEV, 0x2c); pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); - pnp_enter_ext_func_mode(ACPI_DEV); + pnp_enter_conf_state(ACPI_DEV); pnp_set_logical_device(ACPI_DEV); /* * Set the delay rising time from PWROK_LP to PWROK_ST to @@ -117,9 +117,9 @@ /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ reg = pnp_read_config(ACPI_DEV, 0xe4); pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); + pnp_exit_conf_state(ACPI_DEV); - pnp_enter_ext_func_mode(GPIO_DEV); + pnp_enter_conf_state(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ @@ -129,7 +129,7 @@ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + pnp_exit_conf_state(GPIO_DEV); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index adcf381..d893cf5 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -94,7 +94,7 @@ { u8 reg; - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); @@ -104,9 +104,9 @@ /* We have all RESTOUT and even some reserved bits, too. */ reg = pnp_read_config(SERIAL_DEV, 0x2c); pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); - pnp_enter_ext_func_mode(ACPI_DEV); + pnp_enter_conf_state(ACPI_DEV); pnp_set_logical_device(ACPI_DEV); /* * Set the delay rising time from PWROK_LP to PWROK_ST to @@ -117,9 +117,9 @@ /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ reg = pnp_read_config(ACPI_DEV, 0xe4); pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); + pnp_exit_conf_state(ACPI_DEV); - pnp_enter_ext_func_mode(GPIO_DEV); + pnp_enter_conf_state(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ @@ -129,7 +129,7 @@ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + pnp_exit_conf_state(GPIO_DEV); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 7088f1d..43c5677 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -62,7 +62,7 @@ pnp_devfn_t dev; dev = DUMMY_DEV; - pnp_enter_ext_func_mode(dev); + pnp_enter_conf_state(dev); pnp_write_config(dev, 0x24, 0xc4); // PNPCSV @@ -121,7 +121,7 @@ pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_state(dev); } static void rcba_config(void) diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 878a79e..8ddfdd6 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -126,11 +126,11 @@ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); setup_mb_resource_map(); console_init(); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 11e9bc0..ec11dd6 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -129,11 +129,11 @@ post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d8076f0..c2fd798 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -124,9 +124,9 @@ if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); setup_mb_resource_map(); -- To view, visit https://review.coreboot.org/20989 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562 Gerrit-Change-Number: 20989 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/asrock: add ASRock B75 Pro3-M
by Martin Roth (Code Review) 21 Aug '17

21 Aug '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/20227 ) Change subject: mainboard/asrock: add ASRock B75 Pro3-M ...................................................................... mainboard/asrock: add ASRock B75 Pro3-M Tested: - i5-3550 and DIMM configurations: 2+0+2+2, 0+2+2+2, 2+2+2+2, 4+2+4+2 - debug output from serial port, EHCI debug port not found - Arch Linux (Linux 4.11.5) loaded from SeaBIOS, GRUB2, and Linux payload - all PCI and PCI Express slots Issues: - sometimes the machine fails to boot, with serial debug output it can be seen it stucks after SMM initialization, and more likely to fail to boot when serial cable is attached - no S3 resume (not tested in vendor firmware) Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/20227 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/b75pro3-m/Kconfig A src/mainboard/asrock/b75pro3-m/Kconfig.name A src/mainboard/asrock/b75pro3-m/Makefile.inc A src/mainboard/asrock/b75pro3-m/acpi/ec.asl A src/mainboard/asrock/b75pro3-m/acpi/pci.asl A src/mainboard/asrock/b75pro3-m/acpi/platform.asl A src/mainboard/asrock/b75pro3-m/acpi/superio.asl A src/mainboard/asrock/b75pro3-m/acpi_tables.c A src/mainboard/asrock/b75pro3-m/board_info.txt A src/mainboard/asrock/b75pro3-m/devicetree.cb A src/mainboard/asrock/b75pro3-m/dsdt.asl A src/mainboard/asrock/b75pro3-m/gma-mainboard.ads A src/mainboard/asrock/b75pro3-m/gpio.c A src/mainboard/asrock/b75pro3-m/hda_verb.c A src/mainboard/asrock/b75pro3-m/mainboard.c A src/mainboard/asrock/b75pro3-m/romstage.c 16 files changed, 834 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig b/src/mainboard/asrock/b75pro3-m/Kconfig new file mode 100644 index 0000000..010de97 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/Kconfig @@ -0,0 +1,60 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASROCK_B75PRO3_M + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_SOCKET_RPGA989 + select SUPERIO_NUVOTON_NCT6776 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default asrock/b75pro3-m + +config MAINBOARD_PART_NUMBER + string + default "B75 Pro3-M" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1e49 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1849 + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asrock/b75pro3-m/Kconfig.name b/src/mainboard/asrock/b75pro3-m/Kconfig.name new file mode 100644 index 0000000..82ecff2 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_B75PRO3_M + bool "B75 Pro3-M" diff --git a/src/mainboard/asrock/b75pro3-m/Makefile.inc b/src/mainboard/asrock/b75pro3-m/Makefile.inc new file mode 100644 index 0000000..017967b --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/b75pro3-m/acpi/ec.asl b/src/mainboard/asrock/b75pro3-m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/acpi/ec.asl diff --git a/src/mainboard/asrock/b75pro3-m/acpi/pci.asl b/src/mainboard/asrock/b75pro3-m/acpi/pci.asl new file mode 100644 index 0000000..b40a573 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/acpi/pci.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (P0P1) +{ + Name (_ADR, 0x001E0000) + + Method (_PRT, 0) + { + If (PICM) { + Return (Package () { + Package () {0x0001FFFF, 0, 0, 0x14}, + Package () {0x0001FFFF, 1, 0, 0x15}, + Package () {0x0001FFFF, 2, 0, 0x16}, + Package () {0x0001FFFF, 3, 0, 0x17}, + + Package () {0x0002FFFF, 0, 0, 0x17}, + Package () {0x0002FFFF, 1, 0, 0x14}, + Package () {0x0002FFFF, 2, 0, 0x15}, + Package () {0x0002FFFF, 3, 0, 0x16} + }) + } Else { + Return (Package () { + Package () {0x0001FFFF, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package () {0x0001FFFF, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package () {0x0001FFFF, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package () {0x0001FFFF, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package () {0x0002FFFF, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package () {0x0002FFFF, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package () {0x0002FFFF, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package () {0x0002FFFF, 3, \_SB.PCI0.LPCB.LNKG, 0} + }) + } + } +} diff --git a/src/mainboard/asrock/b75pro3-m/acpi/platform.asl b/src/mainboard/asrock/b75pro3-m/acpi/platform.asl new file mode 100644 index 0000000..f7e56ea --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asrock/b75pro3-m/acpi/superio.asl b/src/mainboard/asrock/b75pro3-m/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/acpi/superio.asl diff --git a/src/mainboard/asrock/b75pro3-m/acpi_tables.c b/src/mainboard/asrock/b75pro3-m/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asrock/b75pro3-m/board_info.txt b/src/mainboard/asrock/b75pro3-m/board_info.txt new file mode 100644 index 0000000..8b5546c --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: http://www.asrock.com/mb/Intel/B75%20Pro3-M/ +ROM protocol: SPI +Flashrom support: n +ROM package: DIP-8 +ROM socketed: y +Release year: 2012 diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb new file mode 100644 index 0000000..70b65aa --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -0,0 +1,180 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + device pci 00.0 on + subsystemid 0x1849 0x0150 + end + device pci 01.0 on + subsystemid 0x1849 0x0151 + end + device pci 02.0 on + subsystemid 0x1849 0x0152 + end + chip southbridge/intel/bd82x6x + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "0" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1849 0x1e31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x1e3a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 on # Management Engine KT + subsystemid 0x1849 0x1e3d + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x1e2d + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1849 0x8892 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1849 0x1e10 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5, ASMedia ASM1062 SATA Controller + subsystemid 0x1849 0x1e18 + end + register "pcie_aspm_f4" = "0x80" # Disable ASPM for ASMedia SATA controller + device pci 1c.5 on # PCIe Port #6, Realtek PCIe GbE Controller + subsystemid 0x1849 0x1e1a + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x1e26 + end + device pci 1e.0 on # PCI bridge + subsystemid 0x1849 0x244e + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1e49 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + irq 0x1c = 0x80 + irq 0x27 = 0xc0 + irq 0x2a = 0x62 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe0 = 0x01 + irq 0xe3 = 0x14 + irq 0xe6 = 0x4c + irq 0xe9 = 0x02 + irq 0xf0 = 0x20 + end + device pnp 2e.b off end # HWM, front pannel LED + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f on end # GPIO Push-Pull or Open-drain + device pnp 2e.14 on end # SVID + device pnp 2e.16 on end # Deep Sleep + device pnp 2e.17 on end # GPIOA + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1849 0x1e02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x1e22 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl new file mode 100644 index 0000000..454ee3d --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + #include "acpi/pci.asl" + } + } +} diff --git a/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads b/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads new file mode 100644 index 0000000..504d3b4 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/b75pro3-m/gpio.c b/src/mainboard/asrock/b75pro3-m/gpio.c new file mode 100644 index 0000000..9775f71 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/gpio.c @@ -0,0 +1,190 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c new file mode 100644 index 0000000..cae9137 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x18498892, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x18498892), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x01011012), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19950), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214120), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x01452130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/b75pro3-m/mainboard.c b/src/mainboard/asrock/b75pro3-m/mainboard.c new file mode 100644 index 0000000..f0d0cf7 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c new file mode 100644 index 0000000..f556443 --- /dev/null +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "northbridge/intel/sandybridge/raminit_native.h" +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/common/nuvoton.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000); +} + +void rcba_config(void) +{ + RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0; +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + /* Set GPIOs on superio, enable UART */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_set_logical_device(SERIAL_DEV); + + pnp_write_config(SERIAL_DEV, 0x1c, 0x80); + pnp_write_config(SERIAL_DEV, 0x27, 0x80); + pnp_write_config(SERIAL_DEV, 0x2a, 0x60); + + nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/20227 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6 Gerrit-Change-Number: 20227 Gerrit-PatchSet: 12 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: libpayload: add time()
by Martin Roth (Code Review) 21 Aug '17

21 Aug '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/21011 ) Change subject: libpayload: add time() ...................................................................... libpayload: add time() Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e Signed-off-by: Nicola Corna <nicola(a)corna.info> Reviewed-on: https://review.coreboot.org/21011 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M payloads/libpayload/include/time.h M payloads/libpayload/libc/time.c 2 files changed, 21 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/payloads/libpayload/include/time.h b/payloads/libpayload/include/time.h index 25f476c..42be725 100644 --- a/payloads/libpayload/include/time.h +++ b/payloads/libpayload/include/time.h @@ -44,6 +44,7 @@ suseconds_t tv_usec; /**< Microseconds */ }; +time_t time(time_t *tp); int gettimeofday(struct timeval *tv, void *tz); /** @} */ diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 4ed788f..46306bb 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -121,13 +121,12 @@ #endif /** - * Return the current time broken into a timeval structure. + * Return the current time expressed as seconds from 00:00:00 UTC, 1 Jan 1970. * - * @param tv A pointer to a timeval structure. - * @param tz Added for compatability - not used. - * @return 0 for success (this function cannot return non-zero currently). + * @param tp When not NULL, set this to the current time in seconds. + * @return The current time in seconds. */ -int gettimeofday(struct timeval *tv, void *tz) +time_t time(time_t *tp) { /* * Call the gtod init when we need it - this keeps the code from @@ -138,7 +137,22 @@ update_clock(); - tv->tv_sec = clock.secs; + if (tp) + *tp = clock.secs; + + return clock.secs; +} + +/** + * Return the current time broken into a timeval structure. + * + * @param tv A pointer to a timeval structure. + * @param tz Added for compatibility - not used. + * @return 0 for success (this function cannot return non-zero currently). + */ +int gettimeofday(struct timeval *tv, void *tz) +{ + tv->tv_sec = time(NULL); tv->tv_usec = clock.usecs; return 0; -- To view, visit https://review.coreboot.org/21011 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e Gerrit-Change-Number: 21011 Gerrit-PatchSet: 6 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: ec/lenovo/h8: Add panic method
by Martin Roth (Code Review) 21 Aug '17

21 Aug '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19695 ) Change subject: ec/lenovo/h8: Add panic method ...................................................................... ec/lenovo/h8: Add panic method Add two additional LED IDs. Add Kconfig menu entries to allow selecting the action to execute on death. Overwrite weak die_notify method to notify user on death. Flash all LEDs and play beep code 10 depending on Kconfig options. Successfully tested on: Tested on Lenovo T500. Tested on Lenovo X200. Tested on Lenovo T430, but only LEDs are flashing. Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org Reviewed-on: https://review.coreboot.org/19695 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/Makefile.inc M src/ec/lenovo/h8/h8.h A src/ec/lenovo/h8/panic.c 4 files changed, 70 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Objections: Nico Huber: I would prefer that you didn't submit this diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index 98e8e30..190f4a9 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -9,6 +9,18 @@ depends on PAYLOAD_SEABIOS default 3000 +config H8_BEEP_ON_DEATH + bool "Beep on fatal error" + default y + help + Beep when encountered a fatal error. + +config H8_FLASH_LEDS_ON_DEATH + bool "Flash LEDs on fatal error" + default y + help + Flash all LEDs when encountered a fatal error. + endif config H8_DOCK_EARLY_INIT diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index da9cee1..c37a6e1 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1,5 +1,10 @@ ifeq ($(CONFIG_EC_LENOVO_H8),y) +ifneq ($(filter y,$(CONFIG_H8_BEEP_ON_DEATH) $(CONFIG_H8_FLASH_LEDS_ON_DEATH)),) +romstage-y += panic.c +ramstage-y += panic.c +endif + ramstage-y += h8.c smm-y += smm.c diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index 42d279f..9d4b186 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -71,6 +71,8 @@ #define H8_LED_CONTROL_SUSPEND_LED 0x07 #define H8_LED_CONTROL_DOCK_LED1 0x08 #define H8_LED_CONTROL_DOCK_LED2 0x09 +#define H8_LED_CONTROL_ACDC_LED 0x0c +#define H8_LED_CONTROL_MUTE_LED 0x0e #define H8_USB_ALWAYS_ON 0x0d #define H8_USB_ALWAYS_ON_ENABLE 0x01 diff --git a/src/ec/lenovo/h8/panic.c b/src/ec/lenovo/h8/panic.c new file mode 100644 index 0000000..fbe0dc0 --- /dev/null +++ b/src/ec/lenovo/h8/panic.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <ec/acpi/ec.h> + +#include "h8.h" + +static void h8_panic(void) +{ + if (IS_ENABLED(CONFIG_H8_FLASH_LEDS_ON_DEATH)) { + static const u8 leds[] = { + H8_LED_CONTROL_POWER_LED, + H8_LED_CONTROL_BAT0_LED, + H8_LED_CONTROL_BAT1_LED, + H8_LED_CONTROL_UBAY_LED, + H8_LED_CONTROL_SUSPEND_LED, + H8_LED_CONTROL_DOCK_LED1, + H8_LED_CONTROL_DOCK_LED2, + H8_LED_CONTROL_ACDC_LED, + H8_LED_CONTROL_MUTE_LED + }; + + /* Flash all LEDs */ + for (size_t i = 0; i < ARRAY_SIZE(leds); i++) + ec_write(H8_LED_CONTROL, + H8_LED_CONTROL_BLINK | leds[i]); + } + if (IS_ENABLED(CONFIG_H8_BEEP_ON_DEATH)) { + /* Beep 4 Sec. 1250 Hz */ + ec_write(H8_SOUND_ENABLE1, 4); + ec_write(H8_SOUND_REPEAT, 1); + ec_write(H8_SOUND_REG, 10); + } +} + +void die_notify(void) +{ + h8_panic(); +} -- To view, visit https://review.coreboot.org/19695 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8 Gerrit-Change-Number: 19695 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: ec/lenovo/h8: Add panic method
by Martin Roth (Code Review) 21 Aug '17

21 Aug '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19695 ) Change subject: ec/lenovo/h8: Add panic method ...................................................................... Patch Set 10: There haven't been any additional comments in a week, so I'm going to merge this as it is. It's easy enough to change if people find that the default is too annoying. -- To view, visit https://review.coreboot.org/19695 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8 Gerrit-Change-Number: 19695 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 16:51:08 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Enable common PMC code for CNL
by Lijian Zhao (Code Review) 21 Aug '17

21 Aug '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21062 Change subject: soc/intel/cannonlake: Enable common PMC code for CNL ...................................................................... soc/intel/cannonlake: Enable common PMC code for CNL This update changes Cannonlake to use the new common PMC code. This will help to reduce code duplication and streamline code bring up. Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/include/soc/gpe.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/include/soc/pmc.h M src/soc/intel/cannonlake/include/soc/smbus.h A src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/cannonlake/romstage/romstage.c 11 files changed, 580 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/21062/13 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 1b6759c..1407b14 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -7,6 +7,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_BOOTBLOCK_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 @@ -34,6 +35,7 @@ select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMBUS diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a83eb0..10d444b 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c +bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c bootblock-y += gspi.c @@ -18,6 +19,7 @@ romstage-y += gspi.c romstage-y += memmap.c +romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c romstage-$(CONFIG_UART_DEBUG) += uart.c @@ -25,12 +27,14 @@ ramstage-y += chip.c ramstage-y += gspi.c ramstage-y += memmap.c +ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c postcar-y += memmap.c +postcar-y += pmutil.c postcar-y += spi.c postcar-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 21a06e4..0062c0d 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -26,7 +26,7 @@ #include <soc/p2sb.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/smbus.h> #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1400 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 67be85d..38f9a1f 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -24,6 +24,13 @@ struct soc_intel_cannonlake_config { /* GSPI */ struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form GPP_[A:G] or GPD. */ + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/include/soc/gpe.h b/src/soc/intel/cannonlake/include/soc/gpe.h new file mode 100644 index 0000000..521d523 --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/gpe.h @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* GPE_31_0 */ +#define GPE0_DW0_00 0 +#define GPE0_DW0_01 1 +#define GPE0_DW0_02 2 +#define GPE0_DW0_03 3 +#define GPE0_DW0_04 4 +#define GPE0_DW0_05 5 +#define GPE0_DW0_06 6 +#define GPE0_DW0_07 7 +#define GPE0_DW0_08 8 +#define GPE0_DW0_09 9 +#define GPE0_DW0_10 10 +#define GPE0_DW0_11 11 +#define GPE0_DW0_12 12 +#define GPE0_DW0_13 13 +#define GPE0_DW0_14 14 +#define GPE0_DW0_15 15 +#define GPE0_DW0_16 16 +#define GPE0_DW0_17 17 +#define GPE0_DW0_18 18 +#define GPE0_DW0_19 19 +#define GPE0_DW0_20 20 +#define GPE0_DW0_21 21 +#define GPE0_DW0_22 22 +#define GPE0_DW0_23 23 +#define GPE0_DW0_24 24 +#define GPE0_DW0_25 25 +#define GPE0_DW0_26 26 +#define GPE0_DW0_27 27 +#define GPE0_DW0_28 28 +#define GPE0_DW0_29 29 +#define GPE0_DW0_30 30 +#define GPE0_DW0_31 31 +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_STD */ +#define GPE0_HOT_PLUG 97 +#define GPE0_SWGPE 98 +#define GPE0_TCOSCI 102 +#define GPE0_SMB_WAK 103 +#define GPE0_PCI_EXP 105 +#define GPE0_BATLOW 106 +#define GPE0_PME 107 +#define GPE0_ME_SCI 108 +#define GPE0_PME_B0 109 +#define GPE0_ESPI 110 +#define GPE0_GPIO_T2 111 +#define GPE0_LAN_WAK 112 +#define GPE0_WADT 114 + +#define GPE_MAX GPE0_WADT +#endif /* _SOC_GPE_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 6654122..abf7db9 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -18,22 +18,124 @@ #define _SOC_PM_H_ #include <arch/acpi.h> +#include <arch/io.h> +#include <soc/gpe.h> +#include <soc/iomap.h> +#include <soc/smbus.h> #include <soc/pmc.h> +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) #define PWRBTN_EN (1 << 8) #define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 #define SMI_EN 0x30 +#define XHCI_SMI_EN (1 << 31) +#define ME_SMI_EN (1 << 30) #define ESPI_SMI_EN (1 << 28) +#define GPIO_UNLOCK_SMI_EN (1 << 27) +#define INTEL_USB2_EN (1 << 18) +#define LEGACY_USB2_EN (1 << 17) +#define PERIODIC_EN (1 << 14) +#define TCO_SMI_EN (1 << 13) +#define MCSMI_EN (1 << 11) +#define BIOS_RLS (1 << 7) +#define SWSMI_TMR_EN (1 << 6) #define APMC_EN (1 << 5) #define SLP_SMI_EN (1 << 4) +#define LEGACY_USB_EN (1 << 3) +#define BIOS_EN (1 << 2) #define EOS (1 << 1) #define GBL_SMI_EN (1 << 0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL (1 << 1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50 - +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define WADT_STS (1 << 18) +#define GPIO_T2_STS (1 << 15) +#define ESPI_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define ME_SCI_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_EN(x) (0x70 + ((x) * 4)) -#define PME_B0_EN (1 << 13) +#define WADT_EN (1 << 18) +#define GPIO_T2_EN (1 << 15) +#define ESPI_EN (1 << 14) +#define PME_B0_EN (1 << 13) +#define ME_SCI_EN (1 << 12) +#define PME_EN (1 << 11) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define TCOSCI_EN (1 << 6) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) +#define EN_BLOCK 3 + +/* + * Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * - on eSPI events (does nothing on LPC systems) + * No SMIs: + * - on microcontroller writes (io 0x62/0x66) + * - on TCO events + */ #define ENABLE_SMI_PARAMS \ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) @@ -51,6 +153,16 @@ uint32_t prev_sleep_state; } __attribute__ ((packed)); -struct chipset_power_state *fill_power_state(void); +/* Return the selected ACPI SCI IRQ */ +int acpi_sci_irq(void); + +/* Get base address PMC memory mapped registers. */ +uint8_t *pmc_mmio_regs(void); + +/* Get base address of TCO I/O registers. */ +uint16_t smbus_tco_regs(void); + +/* Set the DISB after DRAM init */ +void pmc_set_disb(void); #endif diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 0bca332..b8e49c2 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -71,9 +71,9 @@ #define SMI_LOCK (1 << 4) #define RTC_BATTERY_DEAD (1 << 2) -#define ETR3 0x1048 -#define ETR3_CF9LOCK (1 << 31) -#define ETR3_CF9GR (1 << 20) +#define ETR 0x1048 +#define CF9_LOCK (1 << 31) +#define CF9_GLB_RST (1 << 20) #define SSML 0x104C #define SSML_SSL_DS (0 << 0) @@ -84,6 +84,8 @@ #define SSMD 0x1054 #define SSMD_SSD_MASK (0xffff << 0) + +#define PRSTS 0x1810 #define S3_PWRGATE_POL 0x1828 #define S3DC_GATE_SUS (1 << 1) @@ -109,11 +111,9 @@ #define PCH2CPU_TT_EN (1 << 26) #define PCH_PWRM_ACPI_TMR_CTL 0x18FC -#define GPIO_CFG 0x1920 -#define GPE0_DWX_MASK 0xf -#define GPE0_DW0_SHIFT 0 -#define GPE0_DW1_SHIFT 4 -#define GPE0_DW2_SHIFT 8 +#define GPIO_GPE_CFG 0x1920 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW_SHIFT(x) (4*(x)) #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) diff --git a/src/soc/intel/cannonlake/include/soc/smbus.h b/src/soc/intel/cannonlake/include/soc/smbus.h index 9de6981..9f1cf34 100644 --- a/src/soc/intel/cannonlake/include/soc/smbus.h +++ b/src/soc/intel/cannonlake/include/soc/smbus.h @@ -30,9 +30,9 @@ /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) #define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO 0x02 -#define TCO2_STS_BOOT 0x04 +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x08 #define TCO_LOCK (1 << 12) #define TCO_TMR_HLT (1 << 11) diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c new file mode 100644 index 0000000..455c969 --- /dev/null +++ b/src/soc/intel/cannonlake/pmutil.c @@ -0,0 +1,217 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Helper functions for dealing with power management registers + * and the differences between PCH variants. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <intelblocks/pmclib.h> +#include <halt.h> +#include <rules.h> +#include <stdlib.h> +#include <soc/gpe.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/smbus.h> +#include <timer.h> +#include "chip.h" + +/* + * SMI + */ + +const char *const *soc_smi_sts_array(size_t *a) +{ + static const char *const smi_sts_bits[] = { + [BIOS_STS_BIT] = "BIOS", + [LEGACY_USB_STS_BIT] = "LEGACY_USB", + [SMI_ON_SLP_EN_STS_BIT] = "SLP_SMI", + [APM_STS_BIT] = "APM", + [SWSMI_TMR_STS_BIT] = "SWSMI_TMR", + [PM1_STS_BIT] = "PM1", + [GPE0_STS_BIT] = "GPE0", + [GPIO_STS_BIT] = "GPI", + [MCSMI_STS_BIT] = "MCSMI", + [DEVMON_STS_BIT] = "DEVMON", + [TCO_STS_BIT] = "TCO", + [PERIODIC_STS_BIT] = "PERIODIC", + [SERIRQ_SMI_STS_BIT] = "SERIRQ_SMI", + [SMBUS_SMI_STS_BIT] = "SMBUS_SMI", + [PCI_EXP_SMI_STS_BIT] = "PCI_EXP_SMI", + [MONITOR_STS_BIT] = "MONITOR", + [SPI_SMI_STS_BIT] = "SPI", + [GPIO_UNLOCK_SMI_STS_BIT] = "GPIO_UNLOCK", + [ESPI_SMI_STS_BIT] = "ESPI_SMI", + }; + + *a = ARRAY_SIZE(smi_sts_bits); + return smi_sts_bits; +} + +/* + * TCO + */ + +const char *const *soc_tco_sts_array(size_t *a) +{ + static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", + [3] = "TIMEOUT", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", + [16] = "INTRD_DET", + [17] = "SECOND_TO", + [18] = "BOOT", + [20] = "SMLINK_SLV" + }; + + *a = ARRAY_SIZE(tco_sts_bits); + return tco_sts_bits; +} + +/* + * GPE0 + */ + +const char *const *soc_gpe_sts_array(size_t *a) +{ + static const char *const gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [6] = "TCO_SCI", + [7] = "SMB_WAK", + [9] = "PCI_EXP", + [10] = "BATLOW", + [11] = "PME", + [12] = "ME", + [13] = "PME_B0", + [14] = "eSPI", + [15] = "GPIO Tier-2", + [16] = "LAN_WAKE", + [18] = "WADT" + }; + + *a = ARRAY_SIZE(gpe_sts_bits); + return gpe_sts_bits; +} + +int acpi_sci_irq(void) +{ + int scis = pci_read_config32(PCH_DEV_PMC, ACTL) & SCI_IRQ_SEL; + int sci_irq = 9; + + /* Determine how SCI is routed. */ + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; +} + +uint8_t *pmc_mmio_regs(void) +{ + uint32_t reg32; + + reg32 = pci_read_config32(PCH_DEV_PMC, PWRMBASE); + + return (void *)(uintptr_t)ALIGN_DOWN(reg32, 4 * KiB); +} + +uint16_t smbus_tco_regs(void) +{ + uint16_t reg16; + + reg16 = pci_read_config16(PCH_DEV_SMBUS, TCOBASE); + + return ALIGN_DOWN(reg16, 0x20); +} + +uint32_t soc_reset_tco_status(void) +{ + u16 tco1_sts; + u16 tco2_sts; + u16 tcobase; + + tcobase = smbus_tco_regs(); + + /* TCO Status 2 register */ + tco2_sts = inw(tcobase + TCO2_STS); + tco2_sts |= TCO2_STS_SECOND_TO; + outw(tco2_sts, tcobase + TCO2_STS); + + /* TCO Status 1 register */ + tco1_sts = inw(tcobase + TCO1_STS); + + /* Clear SECOND_TO_STS bit */ + if (tco2_sts & TCO2_STS_SECOND_TO) + outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS); + + return (tco2_sts << 16) | tco1_sts; +} + +uintptr_t soc_read_pmc_base(void) +{ + return (uintptr_t)pmc_mmio_regs(); +} + +void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) +{ + DEVTREE_CONST struct soc_intel_cannonlake_config *config; + + /* Look up the device in devicetree */ + DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC); + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + } + config = dev->chip_info; + + /* Assign to out variable */ + *dw0 = config->gpe0_dw0; + *dw1 = config->gpe0_dw1; + *dw2 = config->gpe0_dw2; +} diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c index 2c45ad9..46048db 100644 --- a/src/soc/intel/cannonlake/romstage/power_state.c +++ b/src/soc/intel/cannonlake/romstage/power_state.c @@ -18,14 +18,94 @@ #include <arch/io.h> #include <cbmem.h> #include <console/console.h> +#include <device/device.h> +#include <intelblocks/pmclib.h> +#include <string.h> +#include <soc/pci_devs.h> #include <soc/pm.h> static struct chipset_power_state power_state CAR_GLOBAL; -/* Fill power state structure from ACPI PM registers */ -struct chipset_power_state *fill_power_state(void) +static void migrate_power_state(int is_recovery) { - struct chipset_power_state *ps = car_get_var_ptr(&power_state); + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; - return ps; + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} + +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_b & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint16_t tcobase; + uint8_t *pmc; + + tcobase = smbus_tco_regs(); + + ps->tco1_sts = inw(tcobase + TCO1_STS); + ps->tco2_sts = inw(tcobase + TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 2f8617e..ab0e19b 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -14,30 +14,33 @@ */ #include <arch/io.h> +#include <arch/early_variables.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> +#include <intelblocks/pmclib.h> #include <memory_info.h> #include <soc/pm.h> #include <soc/romstage.h> #include <timestamp.h> + +static struct chipset_power_state power_state CAR_GLOBAL; asmlinkage void car_stage_entry(void) { bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); console_init(); /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - ps = fill_power_state(); timestamp_add_now(TS_START_ROMSTAGE); - s3wake = ps->prev_sleep_state == ACPI_S3; + s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1 * KiB)) die("Unable to initialize postcar frame.\n"); -- To view, visit https://review.coreboot.org/21062 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac Gerrit-Change-Number: 21062 Gerrit-PatchSet: 13 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payloads/external/iPXE: Add more Kconfig options
by build bot (Jenkins) (Code Review) 21 Aug '17

21 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20782 ) Change subject: payloads/external/iPXE: Add more Kconfig options ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59004/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14347/ : SUCCESS -- To view, visit https://review.coreboot.org/20782 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e Gerrit-Change-Number: 20782 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 16:04:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/amd/mct_ddr3/mct_d.c: Break out of allow_config_restore loop
by Arthur Heymans (Code Review) 21 Aug '17

21 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20971 ) Change subject: nb/amd/mct_ddr3/mct_d.c: Break out of allow_config_restore loop ...................................................................... Patch Set 3: So remove the -1,verified when a +2 happens and quickly merge it? -- To view, visit https://review.coreboot.org/20971 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie669d1bc38411e40ab95c28b17ee8818874dc741 Gerrit-Change-Number: 20971 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 15:59:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: payloads/external/iPXE: Add more Kconfig options
by Patrick Rudolph (Code Review) 21 Aug '17

21 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20782 to look at the new patch set (#2). Change subject: payloads/external/iPXE: Add more Kconfig options ...................................................................... payloads/external/iPXE: Add more Kconfig options Add two now options: * Disable the promt "Press Ctrl+B for the iPXE command line..." Add a boolean that disable the initial 2 second timeout. * Include a script that is executed instead of showing a shell Allows to add a script that will be included into the iPXE ROM. Tested on Lenovo T500. Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M payloads/external/Makefile.inc M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile 3 files changed, 54 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/20782/2 -- To view, visit https://review.coreboot.org/20782 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie1083d8571d9d1f1c7c71659fb6ff0de2eecad0e Gerrit-Change-Number: 20782 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Keep PMC XRAM access disabled
by build bot (Jenkins) (Code Review) 21 Aug '17

21 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21135 ) Change subject: soc/intel/skylake: Keep PMC XRAM access disabled ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59003/ : SUCCESS -- To view, visit https://review.coreboot.org/21135 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I69a7972bf083a2e376115c6a6a9eb11dd971188f Gerrit-Change-Number: 21135 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 21 Aug 2017 14:55:12 +0000 Gerrit-HasComments: No

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