coreboot-gerrit August 2017

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Change in coreboot[master]: ec/lenovo/h8/acpi/thermal: Don't hardcode limits
by Patrick Rudolph (Code Review) 23 Aug '17

23 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/21159 Change subject: ec/lenovo/h8/acpi/thermal: Don't hardcode limits ...................................................................... ec/lenovo/h8/acpi/thermal: Don't hardcode limits Add support for board specific critical and passive limits using GNVS table. Use default values if no board specific limit exists. * Add ACPI methods _TZP, _TSP and _PSV. * Update ACPI method _CRT to use board specific if available. Tested on Lenovo T500. Change-Id: If438a909f4415f50cd7a764fb5fba7ec29599606 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/ec/lenovo/h8/acpi/thermal.asl 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/21159/1 diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 2e95b69..84e23f9 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -34,9 +34,28 @@ ThermalZone(THM0) { + /* Thermal zone polling frequency: 10 seconds */ + Name (_TZP, 100) + + /* Thermal sampling period for passive cooling: 10 seconds */ + Name (_TSP, 100) + Method(_CRT, 0, NotSerialized) { + Store (\TCRT, Local0) + if (LGreater(Local0, Zero)) { + Return (C2K(Local0)) + } Return (C2K(127)) } + + Method(_PSV, 0, NotSerialized) { + Store (\TPSV, Local0) + if (LGreater(Local0, Zero)) { + Return (C2K(Local0)) + } + Return (C2K(95)) + } + Method(_TMP) { #if defined (EC_LENOVO_H8_ME_WORKAROUND) /* Avoid tripping alarm if ME isn't booted at all yet */ @@ -51,6 +70,12 @@ ThermalZone(THM1) { + /* Thermal zone polling frequency: 10 seconds */ + Name (_TZP, 100) + + /* Thermal sampling period for passive cooling: 10 seconds */ + Name (_TSP, 100) + Method(_CRT, 0, NotSerialized) { Return (C2K(99)) } -- To view, visit https://review.coreboot.org/21159 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If438a909f4415f50cd7a764fb5fba7ec29599606 Gerrit-Change-Number: 21159 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: sb/intel/*/nvs: Rename register
by Patrick Rudolph (Code Review) 23 Aug '17

23 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/21158 Change subject: sb/intel/*/nvs: Rename register ...................................................................... sb/intel/*/nvs: Rename register Rename register to match recent intel models. Required for Lenovo H8 to operate on all generations. Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/nvs.h 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/21158/1 diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index fdd120e..9df2252 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -50,11 +50,11 @@ /* Thermal policy */ Offset (0x14), ACTT, 8, // 0x14 - active trip point - PSVT, 8, // 0x15 - passive trip point + TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 TC2V, 8, // 0x17 - passive trip point TC2 TSPV, 8, // 0x18 - passive trip point TSP - CRTT, 8, // 0x19 - critical trip point + TCRT, 8, // 0x19 - critical trip point DTSE, 8, // 0x1a - Digital Thermal Sensor enable DTS1, 8, // 0x1b - DT sensor 1 DTS2, 8, // 0x1c - DT sensor 2 diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h index c3a3920..decea53 100644 --- a/src/southbridge/intel/i82801gx/nvs.h +++ b/src/southbridge/intel/i82801gx/nvs.h @@ -35,11 +35,11 @@ u8 dckn; /* 0x13 - PCIe docking state */ /* Thermal policy */ u8 actt; /* 0x14 - active trip point */ - u8 psvt; /* 0x15 - passive trip point */ + u8 tpsv; /* 0x15 - passive trip point */ u8 tc1v; /* 0x16 - passive trip point TC1 */ u8 tc2v; /* 0x17 - passive trip point TC2 */ u8 tspv; /* 0x18 - passive trip point TSP */ - u8 crtt; /* 0x19 - critical trip point */ + u8 tcrt; /* 0x19 - critical trip point */ u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ u8 dts1; /* 0x1b - DT sensor 1 */ u8 dts2; /* 0x1c - DT sensor 2 */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index df83064..97d9fa9 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -51,11 +51,11 @@ /* Thermal policy */ Offset (0x14), ACTT, 8, // 0x14 - active trip point - PSVT, 8, // 0x15 - passive trip point + TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 TC2V, 8, // 0x17 - passive trip point TC2 TSPV, 8, // 0x18 - passive trip point TSP - CRTT, 8, // 0x19 - critical trip point + TCRT, 8, // 0x19 - critical trip point DTSE, 8, // 0x1a - Digital Thermal Sensor enable DTS1, 8, // 0x1b - DT sensor 1 DTS2, 8, // 0x1c - DT sensor 2 diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h index c3a3920..decea53 100644 --- a/src/southbridge/intel/i82801ix/nvs.h +++ b/src/southbridge/intel/i82801ix/nvs.h @@ -35,11 +35,11 @@ u8 dckn; /* 0x13 - PCIe docking state */ /* Thermal policy */ u8 actt; /* 0x14 - active trip point */ - u8 psvt; /* 0x15 - passive trip point */ + u8 tpsv; /* 0x15 - passive trip point */ u8 tc1v; /* 0x16 - passive trip point TC1 */ u8 tc2v; /* 0x17 - passive trip point TC2 */ u8 tspv; /* 0x18 - passive trip point TSP */ - u8 crtt; /* 0x19 - critical trip point */ + u8 tcrt; /* 0x19 - critical trip point */ u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ u8 dts1; /* 0x1b - DT sensor 1 */ u8 dts2; /* 0x1c - DT sensor 2 */ -- To view, visit https://review.coreboot.org/21158 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a Gerrit-Change-Number: 21158 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: soc/intel/skylake: Move PMC lock down config after resource allocation
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21029 ) Change subject: soc/intel/skylake: Move PMC lock down config after resource allocation ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59164/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14495/ : SUCCESS -- To view, visit https://review.coreboot.org/21029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Gerrit-Change-Number: 21029 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 23 Aug 2017 15:36:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move LPC lock down config after resource allocation
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21000 ) Change subject: soc/intel/skylake: Move LPC lock down config after resource allocation ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59163/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14494/ : SUCCESS -- To view, visit https://review.coreboot.org/21000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Gerrit-Change-Number: 21000 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 23 Aug 2017 15:33:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Move update_mrc_cache after BS_DEV_ENUMERATE
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21028 ) Change subject: soc/intel/common: Move update_mrc_cache after BS_DEV_ENUMERATE ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59161/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14493/ : SUCCESS -- To view, visit https://review.coreboot.org/21028 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0 Gerrit-Change-Number: 21028 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 23 Aug 2017 15:26:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Add LPC and SPI lock down config option
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21068 ) Change subject: soc/intel/skylake: Add LPC and SPI lock down config option ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59162/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14492/ : SUCCESS -- To view, visit https://review.coreboot.org/21068 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Gerrit-Change-Number: 21068 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 23 Aug 2017 15:24:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/*: add options to trigger finalize_smm() on normal boot
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21129 ) Change subject: sb/intel/*: add options to trigger finalize_smm() on normal boot ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59160/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14491/ : SUCCESS -- To view, visit https://review.coreboot.org/21129 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 Gerrit-Change-Number: 21129 Gerrit-PatchSet: 11 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Aug 2017 15:09:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/padmelon: Fixes to enable power button
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21048 ) Change subject: amd/padmelon: Fixes to enable power button ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59157/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14489/ : SUCCESS -- To view, visit https://review.coreboot.org/21048 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b Gerrit-Change-Number: 21048 Gerrit-PatchSet: 9 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Aug 2017 13:47:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Early system agent library access in postcar stage
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21149 ) Change subject: soc/intel/common: Early system agent library access in postcar stage ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59158/ : SUCCESS -- To view, visit https://review.coreboot.org/21149 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie5558cdb7acacc34451e1cf63a3e4239e7901c67 Gerrit-Change-Number: 21149 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 23 Aug 2017 13:46:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Usable dram top calculation based on HW registers
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21150 ) Change subject: soc/intel/skylake: Usable dram top calculation based on HW registers ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59159/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14490/ : SUCCESS -- To view, visit https://review.coreboot.org/21150 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Gerrit-Change-Number: 21150 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 23 Aug 2017 13:43:55 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017