coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/braswell: Populate NVS SCC BAR1
by Matt DeVillier (Code Review) 23 Aug '17

23 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21172 Change subject: soc/intel/braswell: Populate NVS SCC BAR1 ...................................................................... soc/intel/braswell: Populate NVS SCC BAR1 Cherry-pick from Chromium commit f92d7be. This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put SD controller in D3 Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9 Original-Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie(a)google.com> Original-Tested-by: Aseda Aboagye <aaboagye(a)chromium.org> Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/braswell/scc.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21172/1 diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 3172b73..6538c5c 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -42,7 +42,10 @@ /* Save BAR0 and BAR1 to ACPI NVS */ bar = find_resource(dev, PCI_BASE_ADDRESS_0); if (bar) - gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; + gnvs->dev.scc_bar0[nvs_index] = bar->base; + bar = find_resource(dev, PCI_BASE_ADDRESS_2); + if (bar) + gnvs->dev.scc_bar1[nvs_index] = bar->base; /* Device is enabled in ACPI mode */ gnvs->dev.scc_en[nvs_index] = 1; -- To view, visit https://review.coreboot.org/21172 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab Gerrit-Change-Number: 21172 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com>

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Change in coreboot[master]: google/cyan: Add 2nd source memory 2-channel 4G (Micro/Samsung)
by Matt DeVillier (Code Review) 23 Aug '17

23 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21171 Change subject: google/cyan: Add 2nd source memory 2-channel 4G (Micro/Samsung) ...................................................................... google/cyan: Add 2nd source memory 2-channel 4G (Micro/Samsung) Cherry-pick from Chromium commit 7f0cdf0. Cyan board add 4G DDR3L 2nd source memory (Micro/Samsung) Original-Change-Id: I12f82082d8227e61a97ce0a001d7d2b1f6613e06 Original-Signed-off-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Change-Id: Ieca7201346414d7a962f9619dbe846c67c0f02d6 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/spd/Makefile.inc M src/mainboard/google/cyan/spd/spd.c 2 files changed, 12 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21171/1 diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc index 543ac73..f596086 100644 --- a/src/mainboard/google/cyan/spd/Makefile.inc +++ b/src/mainboard/google/cyan/spd/Makefile.inc @@ -22,8 +22,8 @@ SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR -SPD_SOURCES += empty -SPD_SOURCES += empty +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 5b7dc73..cbe8ceb 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -33,10 +33,13 @@ * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz * 0b0010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0100 - 4GiB total - 2 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b0101 - 4GiB total - 2 x 2GiB Micro MT41K256M16TW-107 1600MHz * 0b0110 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz * 0b0111 - 2GiB total - 1 x 2GiB Micro MT41K256M16TW-107 1600MHz */ -static const uint32_t dual_channel_config = (1 << 0) | (1 << 1); +static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) + | (1 << 4) | (1 << 5); static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { @@ -72,6 +75,12 @@ case 3: printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); break; + case 4: + printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); + break; + case 5: + printk(BIOS_DEBUG, "4GiB Micro MT41K256M16TW-107 1600MHz\n"); + break; case 6: printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); break; -- To view, visit https://review.coreboot.org/21171 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ieca7201346414d7a962f9619dbe846c67c0f02d6 Gerrit-Change-Number: 21171 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: T.H. Lin <T.H_Lin(a)quantatw.com>

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Change in coreboot[master]: google/cyan: Add 2nd source memory (Micro/Samsung)
by Matt DeVillier (Code Review) 23 Aug '17

23 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21170 Change subject: google/cyan: Add 2nd source memory (Micro/Samsung) ...................................................................... google/cyan: Add 2nd source memory (Micro/Samsung) Cherry-pick from Chromium commit 3b578ef. Cyan board use new 2nd source memory (Micro/Samsung) Original-Change-Id: I6f4e8438faede7ac742776a622c265922e498898 Original-Signed-off-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Change-Id: Ie2febe4de57c00c269def15d57f2b5a6f0f378aa Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/spd/Makefile.inc A src/mainboard/google/cyan/spd/empty.spd.hex A src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex A src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex M src/mainboard/google/cyan/spd/spd.c 5 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21170/1 diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc index dd62025..543ac73 100644 --- a/src/mainboard/google/cyan/spd/Makefile.inc +++ b/src/mainboard/google/cyan/spd/Makefile.inc @@ -22,6 +22,10 @@ SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += empty +SPD_SOURCES += empty +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646E-BYK0 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16TW-107 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/cyan/spd/empty.spd.hex b/src/mainboard/google/cyan/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/cyan/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex new file mode 100644 index 0000000..91133b4 --- /dev/null +++ b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex @@ -0,0 +1,32 @@ +92 13 0b 03 04 19 02 02 +03 11 01 08 09 00 fe 02 +69 78 69 30 69 11 10 79 +20 08 3c 3c 01 18 83 05 +00 00 ca 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 45 1d +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 39 50 +31 20 50 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex new file mode 100644 index 0000000..841291b --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex @@ -0,0 +1,17 @@ +# Samsung K4B4G1646E-BYK0 +92 13 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 62 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 CA 0F +4D 34 37 31 42 35 36 37 34 45 42 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index a87aaae..5b7dc73 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -33,6 +33,8 @@ * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz * 0b0010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0110 - 2GiB total - 1 x 2GiB Samsung K4B4G1646E-BYK0 1600MHz + * 0b0111 - 2GiB total - 1 x 2GiB Micro MT41K256M16TW-107 1600MHz */ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1); @@ -70,6 +72,12 @@ case 3: printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); break; + case 6: + printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646E-BYK0 1600MHz\n"); + break; + case 7: + printk(BIOS_DEBUG, "2GiB Micro MT41K256M16TW-107 1600MHz\n"); + break; } /* Return the serial product data for the RAM */ -- To view, visit https://review.coreboot.org/21170 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie2febe4de57c00c269def15d57f2b5a6f0f378aa Gerrit-Change-Number: 21170 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: T.H. Lin <T.H_Lin(a)quantatw.com>

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Change in coreboot[master]: google/cyan: Enable CA Mirror
by Matt DeVillier (Code Review) 23 Aug '17

23 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21169 Change subject: google/cyan: Enable CA Mirror ...................................................................... google/cyan: Enable CA Mirror Cherry-pick from Chromium commit e49deb1. Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is board specific. Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/21169/1 diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 2f2b2df..0454650 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -13,6 +13,7 @@ register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "1" + register "PcdCaMirrorEn" = "0" ############################################################ # Set the parameters for SiliconInit -- To view, visit https://review.coreboot.org/21169 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5 Gerrit-Change-Number: 21169 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Shobhit Srivastava <shobhit.srivastava(a)intel.com>

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Change in coreboot[master]: google/cyan: Disable unused lines on Gpio North Bank
by Matt DeVillier (Code Review) 23 Aug '17

23 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21168 Change subject: google/cyan: Disable unused lines on Gpio North Bank ...................................................................... google/cyan: Disable unused lines on Gpio North Bank Cherry-pick from Chromium commit 1940eb6. The unused lines leads to spurious interrupts on few of the systems. Original-Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Original-Tested-by: Bernie Thompson <bhthompson(a)chromium.org> Change-Id: I6f4f7cec8ef11e781c66b6efff4188259469e41c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/gpio.c 1 file changed, 10 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21168/1 diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c index 66c7c2a..a3883391 100644 --- a/src/mainboard/google/cyan/gpio.c +++ b/src/mainboard/google/cyan/gpio.c @@ -149,16 +149,15 @@ /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ @@ -169,8 +168,7 @@ GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC, /* 23 SEC_GPIO_SUS8 */ -- To view, visit https://review.coreboot.org/21168 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6f4f7cec8ef11e781c66b6efff4188259469e41c Gerrit-Change-Number: 21168 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com>

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Change in coreboot[master]: google/cyan: Clean-up the devicetree
by Matt DeVillier (Code Review) 23 Aug '17

23 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21167 Change subject: google/cyan: Clean-up the devicetree ...................................................................... google/cyan: Clean-up the devicetree Cherry-pick from Chromium 2b51633. Disable unused PCI devices. Update PCI DeviceID. Original-Change-Id: I34fa6e25f9178de959aad30cc979d787cf76b8ad Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7a06a1d44ce933000cbfe2eb71823ee66cb46a34 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/devicetree.cb 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/21167/1 diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 9d14ba6..2f2b2df 100644 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -94,7 +94,7 @@ # EDS Table 24-4, Figure 24-5 device pci 00.0 on end # 8086 2280 - SoC transaction router device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display - device pci 03.0 on end # 8086 22b8 - Camera and Image Processor + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor device pci 0b.0 on end # 8086 22dc - ? device pci 10.0 on end # 8086 2294 - MMC Port device pci 11.0 off end # 8086 0F15 - SDIO Port @@ -111,20 +111,20 @@ device pci 18.5 off end # 8086 22c5 - I2C Port 5 device pci 18.6 on end # 8086 22c6 - I2C Port 6 device pci 18.7 off end # 8086 22c7 - I2C Port 7 - device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine - device pci 1b.0 on end # 8086 0F04 - HD Audio - device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 - device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 - device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4 device pci 1e.0 on end # 8086 2286 - SIO - DMA device pci 1e.1 off end # 8086 0F08 - PWM 1 device pci 1e.2 off end # 8086 0F09 - PWM 2 device pci 1e.3 on end # 8086 228a - HSUART 1 - device pci 1e.4 on end # 8086 228c - HSUART 2 + device pci 1e.4 off end # 8086 228c - HSUART 2 device pci 1e.5 on end # 8086 228e - SPI 1 - device pci 1e.6 on end # 8086 2290 - SPI 2 - device pci 1e.7 on end # 8086 22ac - SPI 3 + device pci 1e.6 off end # 8086 2290 - SPI 2 + device pci 1e.7 off end # 8086 22ac - SPI 3 device pci 1f.0 on # 8086 229c - LPC bridge chip drivers/pc80/tpm # Rising edge interrupt -- To view, visit https://review.coreboot.org/21167 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7a06a1d44ce933000cbfe2eb71823ee66cb46a34 Gerrit-Change-Number: 21167 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com>

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Change in coreboot[master]: google/cyan: Support reading Memory strap GPIOs to select SPD
by Matt DeVillier (Code Review) 23 Aug '17

23 Aug '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21166 Change subject: google/cyan: Support reading Memory strap GPIOs to select SPD ...................................................................... google/cyan: Support reading Memory strap GPIOs to select SPD Cherry-pick from Chromium commit 8f63720. SoC GPIO to read Memory strap not getting configured correctly causing incorrect RAMID read during ROMSTAGE TEST=Build and boot the platform with differnt Memory type and read RAMID correctly inside spd.c RAMID = 0 => 4GB Samsung Memory RAMID = 1 => 4GB Hynix Memory RAMID = 2 => 2GB Samsung Memory RAMID = 3 => 2GB Hynix Memory Original-Change-Id: Ide9d4b5f73565cddd74cedf7afe4b7d168dde74c Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/spd/spd.c 1 file changed, 14 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21166/1 diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index c2e9e79..a87aaae 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -17,6 +17,7 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <gpio.h> #include <lib.h> #include <memory_info.h> #include <smbios.h> @@ -26,10 +27,6 @@ #include <string.h> #define SPD_SIZE 256 -#define SATA_GP3_PAD_CFG0 0x5828 -#define I2C3_SCL_PAD_CFG0 0x5438 -#define MF_PLT_CLK1_PAD_CFG0 0x4410 -#define I2C3_SDA_PAD_CFG0 0x5420 /* * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz @@ -39,22 +36,18 @@ */ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1); -static void configure_ramid_gpios(void) -{ - write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + SATA_GP3_PAD_CFG0), - (PAD_PULL_DISABLE | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + MF_PLT_CLK1_PAD_CFG0), - (PAD_PULL_DISABLE | PAD_GPIO_ENABLE | PAD_CONFIG0_GPI_DEFAULT)); -} - static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { int ram_id = 0; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; - ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) - << 2; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; + + gpio_t spd_gpios[] = { + GP_SW_80, /* SATA_GP3,RAMID0 */ + GP_SW_67, /* I2C3_SCL,RAMID1 */ + GP_SE_02, /* MF_PLT_CLK1, RAMID2 */ + GP_SW_64, /* I2C3_SDA RAMID3 */ + }; + + ram_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); if (ram_id >= total_spds) return NULL; @@ -66,10 +59,14 @@ /* Display the RAM type */ switch (ram_id) { case 0: + printk(BIOS_DEBUG, "4GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); + break; case 2: printk(BIOS_DEBUG, "2GiB Samsung K4B4G1646Q-HYK0 1600MHz\n"); break; case 1: + printk(BIOS_DEBUG, "4GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); + break; case 3: printk(BIOS_DEBUG, "2GiB Hynix H5TC4G63CFR-PBA 1600MHz\n"); break; @@ -95,8 +92,6 @@ if (spd_file_len < SPD_SIZE) die("Missing SPD data."); - - configure_ramid_gpios(); /* * Both channels are always present in SPD data. Always use matched -- To view, visit https://review.coreboot.org/21166 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2ba9ec5be111b9c30360ffde41a2c644a69ecae Gerrit-Change-Number: 21166 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: amd/stoneyridge: Change ACPI _PR.CPxx to _PR.Pxxx
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21165 ) Change subject: amd/stoneyridge: Change ACPI _PR.CPxx to _PR.Pxxx ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59179/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14510/ : SUCCESS -- To view, visit https://review.coreboot.org/21165 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f Gerrit-Change-Number: 21165 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Aug 2017 22:59:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Change ACPI _PR.CPxx to _PR.Pxxx
by Marc Jones (Code Review) 23 Aug '17

23 Aug '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/21165 Change subject: amd/stoneyridge: Change ACPI _PR.CPxx to _PR.Pxxx ...................................................................... amd/stoneyridge: Change ACPI _PR.CPxx to _PR.Pxxx This is a bug introduced by this commit: stoneyridge: Fix CPU ASL \_PR table [commit I870f81] The following error is found in dmesg ACPI Error: [\_PR_.P000] Namespace lookup failure, AE_NOT_FOUND... ACPI Exception: AE_NOT_FOUND, During name lookup/catalog... ACPI Exception: AE_NOT_FOUND, (SSDT:AGESA ) while loading table... ACPI Error: 1 table load failures, 3 successful... ... acpi-cpufreq: overriding BIOS provided _PSD data And, "ls -la /sys/devices/system/cpu/cpufreq/" doesn't work The cause is that the Pstate SSDT table generated by AGESA expects CPU variables \_PR.Pxxx, not \_PR.CPxx as generated by coreboot. Use an AGESA specifc function to set Pxxx. BRANCH=none BUG=b:64885241 TEST= Check dmeg and ls -la /sys/devices/system/cpu/cpufreq/ Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi.c 1 file changed, 28 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/21165/1 diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 9788a91..ed84d32 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -232,6 +232,30 @@ header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); } + +/** + * The AMD AGESA SSDT Pstate table expects Processor devices labeled \_PR.Pxxx, + * not _PR.CPxx, as the generic write acpigen_write_processor() generates. + */ +static void agesa_acpigen_write_processor(u8 cpuindex, u32 pblock_addr, + u8 pblock_len) +{ +/* + Processor (\_PR.CPUcpuindex, cpuindex, pblock_addr, pblock_len) + { +*/ + char pscope[16]; + acpigen_emit_ext_op(PROCESSOR_OP); + acpigen_write_len_f(); + + snprintf(pscope, sizeof(pscope), + "\\_PR.P%03d", (unsigned int) cpuindex); + acpigen_emit_namestring(pscope); + acpigen_emit_byte(cpuindex); + acpigen_emit_dword(pblock_addr); + acpigen_emit_byte(pblock_len); +} + void generate_cpu_entries(device_t device) { int cores, cpu, plen = 6; @@ -245,15 +269,15 @@ printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); - /* Generate BSP \_PR.CPU0 */ - acpigen_write_processor(0, pcontrol_blk, plen); + /* Generate BSP \_PR.P000 */ + agesa_acpigen_write_processor(0, pcontrol_blk, plen); acpigen_pop_len(); - /* Generate AP \_PR.CPUx */ + /* Generate AP \_PR.Pxxx */ pcontrol_blk = 0; plen = 0; for (cpu = 1; cpu < cores; cpu++) { - acpigen_write_processor(cpu, pcontrol_blk, 0); + agesa_acpigen_write_processor(cpu, pcontrol_blk, 0); acpigen_pop_len(); } } -- To view, visit https://review.coreboot.org/21165 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f Gerrit-Change-Number: 21165 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: [WIP] payloads/external/GRUB2: Convert to use Makefile.git
by build bot (Jenkins) (Code Review) 23 Aug '17

23 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21164 ) Change subject: [WIP] payloads/external/GRUB2: Convert to use Makefile.git ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59176/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14507/ : SUCCESS -- To view, visit https://review.coreboot.org/21164 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I837a5e3b107eb82e14dcd0f21a954250f0e9b088 Gerrit-Change-Number: 21164 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Aug 2017 22:31:54 +0000 Gerrit-HasComments: No

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