coreboot-gerrit August 2017

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Change in coreboot[master]: google/gru: Support Nefario rev0
by build bot (Jenkins) (Code Review) 24 Aug '17

24 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21176 ) Change subject: google/gru: Support Nefario rev0 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59202/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14533/ : SUCCESS -- To view, visit https://review.coreboot.org/21176 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8 Gerrit-Change-Number: 21176 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Aug 2017 01:41:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]soc/intel/cannonlake: Init UPD params based on config
by build bot (Jenkins) (Code Review) 24 Aug '17

24 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21175 ) Change subject: [WIP]soc/intel/cannonlake: Init UPD params based on config ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59203/ : SUCCESS -- To view, visit https://review.coreboot.org/21175 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Gerrit-Change-Number: 21175 Gerrit-PatchSet: 3 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Aug 2017 01:35:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]soc/intel/cannonlake: Init UPD params based on config
by Pratikkumar V Prajapati (Code Review) 24 Aug '17

24 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21175 to look at the new patch set (#3). Change subject: [WIP]soc/intel/cannonlake: Init UPD params based on config ...................................................................... [WIP]soc/intel/cannonlake: Init UPD params based on config Initialize UPD params based upon config Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/romstage/romstage.c A src/soc/intel/cannonlake/vr_config.c 6 files changed, 146 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21175/3 -- To view, visit https://review.coreboot.org/21175 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Gerrit-Change-Number: 21175 Gerrit-PatchSet: 3 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/gru: Support Nefario rev0
by Philip Chen (Code Review) 24 Aug '17

24 Aug '17

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/21176 Change subject: google/gru: Support Nefario rev0 ...................................................................... google/gru: Support Nefario rev0 Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario. Also, remove DVS support for CENTERLOGIC. BUG=b:64702054, b:63537905 TEST=build coreboot Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8 Signed-off-by: Philip Chen <philipchen(a)google.com> --- M src/mainboard/google/gru/board.h M src/mainboard/google/gru/mainboard.c M src/mainboard/google/gru/pwm_regulator.c M src/mainboard/google/gru/romstage.c 4 files changed, 25 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/21176/1 diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index f240dcf..7c63c82 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -33,7 +33,6 @@ #define GPIO_P30V_EN dead_code_t(gpio_t, "PP3000 doesn't exist on Scarlet") #define GPIO_TP_RST_L dead_code_t(gpio_t, "don't need TP_RST_L on Scarlet") #define GPIO_TPM_IRQ GPIO(1, C, 1) -#define GPIO_WLAN_RST_L dead_code_t(gpio_t, "no WLAN reset on Scarlet in FW") #define GPIO_WP GPIO(0, B, 5) #else #define GPIO_BACKLIGHT GPIO(1, C, 1) @@ -44,10 +43,16 @@ #define GPIO_P30V_EN GPIO(0, B, 4) #define GPIO_TP_RST_L GPIO(3, B, 4) /* may also be an I2C pull-up enable */ #define GPIO_TPM_IRQ GPIO(0, A, 5) -#define GPIO_WLAN_RST_L GPIO(1, B, 3) #define GPIO_WP GPIO(1, C, 2) #endif +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET) ||\ + IS_ENABLED(CONFIG_BOARD_GOOGLE_NEFARIO) +#define GPIO_WLAN_RST_L dead_code_t(gpio_t, "no WLAN reset on Scarlet in FW") +#else +#define GPIO_WLAN_RST_L GPIO(1, B, 3) +#endif + void setup_chromeos_gpios(void); #endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_GRU_BOARD_H */ diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 240a549..4ebcd3c 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -44,7 +44,8 @@ /* * Wifi's PDN/RST line is pulled down by its (unpowered) voltage rails, but * this reset pin is pulled up by default. Let's drive it low as early as we - * can. Scarlet uses a different WiFi chip that doesn't have this pin anymore. + * can. Scarlet and Nefario use a different WiFi chip that doesn't have this + * pin anymore. */ static void assert_wifi_reset(void) { @@ -350,7 +351,9 @@ configure_display(); setup_usb(0); if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) { - assert_wifi_reset(); /* Scarlet: no WIFI_PD# line */ + /* Scarlet and Nefario: no WIFI_PD# line */ + if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_NEFARIO)) + assert_wifi_reset(); configure_touchpad(); /* Scarlet: works differently */ setup_usb(1); /* Scarlet: only one USB port */ register_gpio_suspend(); /* Scarlet: all EC-controlled */ diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 3ee74a4..329a757 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -40,12 +40,14 @@ [PWM_REGULATOR_CENTERLOG] = {8001, 10497} }; -/* Applies for Gru rev2+ and Bob. */ +/* Applies for Gru rev2+, Bob, and Nefario. */ int pwm_design_voltage[][2] = { [PWM_REGULATOR_GPU] = {7864, 12177}, [PWM_REGULATOR_BIG] = {8001, 13022}, [PWM_REGULATOR_LIT] = {7977, 13078}, +#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_NEFARIO) [PWM_REGULATOR_CENTERLOG] = {7994, 10499} +#endif }; /* Applies for Scarlet */ @@ -58,12 +60,17 @@ int pwm_enum_to_pwm_number[] = { [PWM_REGULATOR_GPU] = 0, [PWM_REGULATOR_LIT] = 2, +#if IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET) ||\ + IS_ENABLED(CONFIG_BOARD_GOOGLE_NEFARIO) + /* Fixed regulator on Nefario and Scarlet */ + [PWM_REGULATOR_CENTERLOG] = -1, +#else + [PWM_REGULATOR_CENTERLOG] = 3, +#endif #if IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET) [PWM_REGULATOR_BIG] = 3, - [PWM_REGULATOR_CENTERLOG] = -1, /* fixed regulator on Scarlet */ #else [PWM_REGULATOR_BIG] = 1, - [PWM_REGULATOR_CENTERLOG] = 3, #endif }; diff --git a/src/mainboard/google/gru/romstage.c b/src/mainboard/google/gru/romstage.c index bde61b2..5fb5330 100644 --- a/src/mainboard/google/gru/romstage.c +++ b/src/mainboard/google/gru/romstage.c @@ -42,10 +42,11 @@ pwm_regulator_configure(PWM_REGULATOR_BIG, 900); /* Kevin's logic rail has some ripple, so up the voltage a bit. Scarlet - uses a fixed 900mV regulator for centerlogic. */ + and Nefario use a fixed 900mV regulator for centerlogic. */ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN)) pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 925); - else if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) + else if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET) && + !IS_ENABLED(CONFIG_BOARD_GOOGLE_NEFARIO)) pwm_regulator_configure(PWM_REGULATOR_CENTERLOG, 900); /* Allow time for the regulators to settle */ -- To view, visit https://review.coreboot.org/21176 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8 Gerrit-Change-Number: 21176 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com>

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: set Max CPUs and Mainboard Family
by build bot (Jenkins) (Code Review) 24 Aug '17

24 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21152 ) Change subject: mainboard/intel/cannonlake_rvp: set Max CPUs and Mainboard Family ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59200/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14531/ : SUCCESS -- To view, visit https://review.coreboot.org/21152 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6ef7e4f247ac2d227bab3b53512c659c5e72da7 Gerrit-Change-Number: 21152 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Aug 2017 00:50:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Init UPD params based on config
by build bot (Jenkins) (Code Review) 24 Aug '17

24 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21175 ) Change subject: soc/intel/cannonlake: Init UPD params based on config ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59201/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14532/ : SUCCESS -- To view, visit https://review.coreboot.org/21175 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Gerrit-Change-Number: 21175 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Aug 2017 00:50:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add cpu.c and MP init support
by build bot (Jenkins) (Code Review) 24 Aug '17

24 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21081 ) Change subject: soc/intel/cannonlake: Add cpu.c and MP init support ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59198/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14529/ : SUCCESS -- To view, visit https://review.coreboot.org/21081 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Gerrit-Change-Number: 21081 Gerrit-PatchSet: 5 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Aug 2017 00:49:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Init UPD params based on config
by build bot (Jenkins) (Code Review) 24 Aug '17

24 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21175 ) Change subject: soc/intel/cannonlake: Init UPD params based on config ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/59199/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/14530/ : SUCCESS -- To view, visit https://review.coreboot.org/21175 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Gerrit-Change-Number: 21175 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 24 Aug 2017 00:45:21 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Init UPD params based on config
by Pratikkumar V Prajapati (Code Review) 24 Aug '17

24 Aug '17

Pratikkumar V Prajapati has uploaded a new patch set (#2). ( https://review.coreboot.org/21175 ) Change subject: soc/intel/cannonlake: Init UPD params based on config ...................................................................... soc/intel/cannonlake: Init UPD params based on config Initialize UPD params based upon config Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/romstage/romstage.c A src/soc/intel/cannonlake/vr_config.c 6 files changed, 146 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21175/2 -- To view, visit https://review.coreboot.org/21175 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Gerrit-Change-Number: 21175 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Init UPD params based on config
by Pratikkumar V Prajapati (Code Review) 24 Aug '17

24 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21175 Change subject: soc/intel/cannonlake: Init UPD params based on config ...................................................................... soc/intel/cannonlake: Init UPD params based on config Initialize UPD params based upon config Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/vr_config.h M src/soc/intel/cannonlake/romstage/romstage.c A src/soc/intel/cannonlake/vr_config.c 6 files changed, 146 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21175/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 435ce2d..0c05057 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c +ramstage-y += vr_config.c postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 62181a3..bee2517 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -20,6 +20,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <romstage_handoff.h> +#include <soc/pci_devs.h> #include <soc/ramstage.h> #include <string.h> @@ -68,6 +69,8 @@ { int i; FSP_S_CONFIG *params = &supd->FspsConfig; + const struct device *dev = SA_DEV_ROOT; + const config_t *config = dev->chip_info; /* Set USB OC pin to 0 first */ for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { @@ -79,6 +82,71 @@ } mainboard_silicon_init_params(params); + + /* SATA */ + params->SataEnable = config->SataEnable; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + + /* Lan */ + params->PchLanEnable = config->PchLanEnable; + + /* Audio */ + params->PchHdaDspEnable = config->PchHdaDspEnable; + params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; + + /* USB */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = + config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = + config->usb2_ports[i].ocpin; + params->Usb2AfePetxiset[i] = + config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = + config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = + config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = + config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + params->XdciEnable = config->XdciEnable; + + /* eMMC and SD */ + params->ScsEmmcEnabled = config->ScsEmmcEnabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsSdCardEnabled = config->ScsSdCardEnabled; + params->ScsUfsEnabled = config->ScsUfsEnabled; + + params->Heci3Enabled = config->Heci3Enabled; + params->Device4Enable = config->Device4Enable; + params->SkipMpInit = config->FspSkipMpInit; + + /* VrConfig Settings for 5 domains + * 0 = System Agent, 1 = IA Core, 2 = Ring, + * 3 = GT unsliced, 4 = GT sliced */ + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(params, i, &config->domain_vr_config[i]); } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index ea9f7d7..48305fe 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -165,7 +165,7 @@ CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ } chipset_lockdown; - uint8_t SkipMpInit; + uint8_t FspSkipMpInit; /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h index 47f659a..2cd7dd9 100644 --- a/src/soc/intel/cannonlake/include/soc/vr_config.h +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -66,4 +66,7 @@ NUM_VR_DOMAINS }; +void fill_vr_domain_config(void *params, + int domain, const struct vr_config *cfg); + #endif diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index ab0e19b..fdb13c5 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -15,12 +15,14 @@ #include <arch/io.h> #include <arch/early_variables.h> +#include <chip.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> #include <intelblocks/pmclib.h> #include <memory_info.h> +#include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> #include <timestamp.h> @@ -63,8 +65,27 @@ run_postcar_phase(&pcf); } +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const config_t *config) +{ + int i; + uint32_t mask = 0; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + const struct device *dev = SA_DEV_ROOT; + const config_t *config = dev->chip_info; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg, config); + mainboard_memory_init_params(mupd); } diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c new file mode 100644 index 0000000..9db71b2 --- /dev/null +++ b/src/soc/intel/cannonlake/vr_config.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <fsp/api.h> +#include <soc/ramstage.h> +#include <soc/vr_config.h> + +static const struct vr_config default_configs[NUM_VR_DOMAINS] = { + +}; + +void fill_vr_domain_config(void *params, + int domain, const struct vr_config *chip_cfg) +{ + FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params; + const struct vr_config *cfg; + + if (domain < 0 || domain >= NUM_VR_DOMAINS) + return; + + /* Use device tree override if requested. */ + if (chip_cfg->vr_config_enable) + cfg = chip_cfg; + else + cfg = &default_configs[domain]; + + vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; + vr_params->Psi1Threshold[domain] = cfg->psi1threshold; + vr_params->Psi2Threshold[domain] = cfg->psi2threshold; + vr_params->Psi3Threshold[domain] = cfg->psi3threshold; + vr_params->Psi3Enable[domain] = cfg->psi3enable; + vr_params->Psi4Enable[domain] = cfg->psi4enable; + vr_params->ImonSlope[domain] = cfg->imon_slope; + vr_params->ImonOffset[domain] = cfg->imon_offset; + vr_params->IccMax[domain] = cfg->icc_max; + vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; + vr_params->AcLoadline[domain] = cfg->ac_loadline; + vr_params->DcLoadline[domain] = cfg->dc_loadline; +} -- To view, visit https://review.coreboot.org/21175 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9 Gerrit-Change-Number: 21175 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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coreboot-gerrit August 2017