Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21178 )
Change subject: mb/lenovo/t430s: Fix expresscard's hotplug capability
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Patch Set 1:
(1 comment)
Nice catch.
The southbridge code should probably be improved to handle this instead having to work around it in devicetree.
https://review.coreboot.org/#/c/21178/1/src/mainboard/lenovo/t430s/devicetr…
File src/mainboard/lenovo/t430s/devicetree.cb:
https://review.coreboot.org/#/c/21178/1/src/mainboard/lenovo/t430s/devicetr…
PS1, Line 74: pcie_port_coalesce
Remapping happens due to this.
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Gerrit-Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Gerrit-Change-Number: 21178
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Bill XIE has uploaded this change for review. ( https://review.coreboot.org/21178
Change subject: mb/lenovo/t430s: Fix expresscard's hotplug capability
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mb/lenovo/t430s: Fix expresscard's hotplug capability
lspci(8) shows that if pci-e port 1c.0 is set to off, port 1c.1
will shifted to 1c.0, and rest ports could be reasoned by analogy,
so that the flag inside "pcie_hotplug_map" of devicetree.cb will
not applied to the expresscard slot.
In order to workaround this, we may modify "pcie_hotplug_map" to
affect the shifted 1c.1, or leave the original 1c.0 on.
Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
Signed-off-by: Bill XIE <persmule(a)gmail.com>
---
M 3rdparty/vboot
M src/mainboard/lenovo/t430s/devicetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/21178/1
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 8c4b828..8b71425 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 8c4b828502d8c6c7112286720dddfd30c92a968e
+Subproject commit 8b71425257d251858410de71efcf389df8b200d2
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index 6846879..d11ad60 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -64,7 +64,7 @@
register "gen2_dec" = "0x0c15e1"
register "gen4_dec" = "0x0c06a1"
- register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+ register "pcie_hotplug_map" = "{ 0, 1, 0, 0, 0, 0, 0, 0 }"
register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf"
--
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Gerrit-Change-Id: I28c4eaf82fb52fe793dfa2f824f14686b80951ad
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