coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/cannonlake: Use common mca_configure() API
by Pratikkumar V Prajapati (Code Review) 28 Aug '17

28 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21241 Change subject: soc/intel/cannonlake: Use common mca_configure() API ...................................................................... soc/intel/cannonlake: Use common mca_configure() API Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ib4943a7f7929775bd5e9945462e530ef68a398b8 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/cpu.c 1 file changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/21241/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ec979f0..2faadfd 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -129,29 +129,6 @@ wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); } -static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - msr.lo = msr.hi = 0; - /* - * TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. - */ - for (i = 0; i < num_banks; i++) { - /* Clear the machine check status */ - wrmsr(IA32_MC0_STATUS + (i * 4), msr); - /* Initialize machine checks */ - wrmsr(IA32_MC0_CTL + i * 4, - (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); - } -} - static void configure_c_states(void) { msr_t msr; @@ -194,7 +171,10 @@ void soc_core_init(device_t cpu) { /* Clear out pending MCEs */ - configure_mca(); + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_configure(); /* Enable the local CPU apics */ enable_lapic_tpr(); -- To view, visit https://review.coreboot.org/21241 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4943a7f7929775bd5e9945462e530ef68a398b8 Gerrit-Change-Number: 21241 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Use common mca_configure() API
by Pratikkumar V Prajapati (Code Review) 28 Aug '17

28 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21240 Change subject: soc/intel/skylake: Use common mca_configure() API ...................................................................... soc/intel/skylake: Use common mca_configure() API Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ia96cb82fff3def46dbecb09dee94de86f179abe6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/skylake/cpu.c 1 file changed, 4 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/21240/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 031a01d..0ad5dc9 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -324,29 +324,6 @@ printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy); } -static void configure_mca(void) -{ - msr_t msr; - int i; - int num_banks; - - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & 0xff; - msr.lo = msr.hi = 0; - /* - * TODO(adurbin): This should only be done on a cold boot. Also, some - * of these banks are core vs package scope. For now every CPU clears - * every bank. - */ - for (i = 0; i < num_banks; i++) { - /* Clear the machine check status */ - wrmsr(IA32_MC0_STATUS + (i * 4), msr); - /* Initialize machine checks */ - wrmsr(IA32_MC0_CTL + i * 4, - (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); - } -} - static void configure_c_states(void) { msr_t msr; @@ -410,7 +387,10 @@ void soc_core_init(device_t cpu) { /* Clear out pending MCEs */ - configure_mca(); + /* TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. */ + mca_configure(); /* Enable the local CPU apics */ enable_lapic_tpr(); -- To view, visit https://review.coreboot.org/21240 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia96cb82fff3def46dbecb09dee94de86f179abe6 Gerrit-Change-Number: 21240 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: intel/common/block: Add API to configure MCA
by Pratikkumar V Prajapati (Code Review) 28 Aug '17

28 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21239 Change subject: intel/common/block: Add API to configure MCA ...................................................................... intel/common/block: Add API to configure MCA Add mca_configure() API to configure Intel Machine Check Architecture (MCA). Change-Id: I5e88c7527ce350824e48892caa978b2b78f1de20 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/21239/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 2272e69..0d6dacc 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -296,3 +296,21 @@ msr = rdmsr(MSR_TURBO_RATIO_LIMIT); return msr.lo & 0xff; } + +void mca_configure(void) +{ + msr_t msr; + int i; + int num_banks; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & 0xff; + msr.lo = msr.hi = 0; + for (i = 0; i < num_banks; i++) { + /* Clear the machine check status */ + wrmsr(IA32_MC0_STATUS + (i * 4), msr); + /* Initialize machine checks */ + wrmsr(IA32_MC0_CTL + i * 4, + (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 3d40a92..551d89f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -156,4 +156,7 @@ */ uint32_t cpu_get_max_turbo_ratio(void); +/* Configure Machine Check Architecture support */ +void mca_configure(void) + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ -- To view, visit https://review.coreboot.org/21239 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5e88c7527ce350824e48892caa978b2b78f1de20 Gerrit-Change-Number: 21239 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in libhwbase[master]: direct pci: Always initialize Address_State
by Nico Huber (Code Review) 28 Aug '17

28 Aug '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/21205 ) Change subject: direct pci: Always initialize Address_State ...................................................................... direct pci: Always initialize Address_State Let Initialize() always initialize the Address_State. This is not only the expected behaviour but also necessary to share the contract with other implementations. Change-Id: I0454dfd6c36f7d4298edeec5b84d929e3160eb7b Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/21205 Reviewed-by: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> --- M common/direct/hw-pci-dev.adb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Nico Huber: Verified Adrian-Ken Rueegsegger: Looks good to me, approved diff --git a/common/direct/hw-pci-dev.adb b/common/direct/hw-pci-dev.adb index 9bd7d1d..3d76521 100644 --- a/common/direct/hw-pci-dev.adb +++ b/common/direct/hw-pci-dev.adb @@ -108,6 +108,8 @@ begin if MMConf_Base /= 0 then MM.Set_Base_Address (MMConf_Base); + else + MM.Set_Base_Address (Config.Default_MMConf_Base); end if; Success := MMConf_Base /= 0 or Config.Default_MMConf_Base_Set; end Initialize; -- To view, visit https://review.coreboot.org/21205 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I0454dfd6c36f7d4298edeec5b84d929e3160eb7b Gerrit-Change-Number: 21205 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>

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Change in libgfxinit[master]: gma: Fix refined contract of Initialize()
by Nico Huber (Code Review) 28 Aug '17

28 Aug '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/21207 ) Change subject: gma: Fix refined contract of Initialize() ...................................................................... gma: Fix refined contract of Initialize() To be compatible with HW.PCI.Dev implementations that do actual register accesses, we have to account for hardware state updates. Change-Id: I86e42163d7847f7011bcf9a0ef5c2c7f25b4b1be Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/21207 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> --- M common/hw-gfx-gma.adb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nico Huber: Verified Patrick Georgi: Looks good to me, approved Adrian-Ken Rueegsegger: Looks good to me, but someone else must approve diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 94f3ceb..101de18 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -301,7 +301,7 @@ with Refined_Global => (In_Out => - (Config.Valid_Port_GPU, + (Config.Valid_Port_GPU, Dev.PCI_State, Registers.Register_State, Port_IO.State), Input => (Time.State), -- To view, visit https://review.coreboot.org/21207 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I86e42163d7847f7011bcf9a0ef5c2c7f25b4b1be Gerrit-Change-Number: 21207 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>

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Change in coreboot[master]: mb/lenovo/t400/blc.c: Add B141EW05 V3 to whitelist
by Arthur Heymans (Code Review) 28 Aug '17

28 Aug '17

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/21230 ) Change subject: mb/lenovo/t400/blc.c: Add B141EW05 V3 to whitelist ...................................................................... mb/lenovo/t400/blc.c: Add B141EW05 V3 to whitelist TESTED on Lenovo T400 Change-Id: I365aeb7e997def225c23d3287558bdc4eefa4298 Signed-off-by: Kevin Keijzer <kevin(a)quietlife.nl> Reviewed-on: https://review.coreboot.org/21230 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t400/blc.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/lenovo/t400/blc.c b/src/mainboard/lenovo/t400/blc.c index 01f34c1..56f6738 100644 --- a/src/mainboard/lenovo/t400/blc.c +++ b/src/mainboard/lenovo/t400/blc.c @@ -21,6 +21,7 @@ /* Vendor BIOS seems to intend to set PWM freq at 220Hz */ /* T400 */ {"B141EW04 V7 ", 110}, + {"B141EW05 V3 ", 450}, {"LP141WX3-TLR1", 110}, {"LP141WX5-TLP2", 450}, {"LTN141AT12401", 450}, -- To view, visit https://review.coreboot.org/21230 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I365aeb7e997def225c23d3287558bdc4eefa4298 Gerrit-Change-Number: 21230 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Keijzer <kevin(a)quietlife.nl> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Kconfig: move Mainboard selection to the top level
by Alexander Couzens (Code Review) 28 Aug '17

28 Aug '17

Alexander Couzens has removed Martin Roth from this change. ( https://review.coreboot.org/21238 ) Change subject: Kconfig: move Mainboard selection to the top level ...................................................................... Removed reviewer Martin Roth. -- To view, visit https://review.coreboot.org/21238 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: deleteReviewer Gerrit-Change-Id: Ic21abc69a3430475c232d8050626d6bca98c5514 Gerrit-Change-Number: 21238 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/common/gpio: Add acpigen functions in common GPIO
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21231 ) Change subject: soc/common/gpio: Add acpigen functions in common GPIO ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/59416/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14725/ : SUCCESS -- To view, visit https://review.coreboot.org/21231 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e9ae9f37a4b524521c346f54b8281d1eb26c8d0 Gerrit-Change-Number: 21231 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 18:28:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/common/gpio: Add acpigen functions in common GPIO
by Shaunak Saha (Code Review) 28 Aug '17

28 Aug '17

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/21231 Change subject: soc/common/gpio: Add acpigen functions in common GPIO ...................................................................... soc/common/gpio: Add acpigen functions in common GPIO This patch adds acpigen functions to common gpio block as those are actually used to set/get gpio DW0/DW1 Rx/Tx bits. Change-Id: I4e9ae9f37a4b524521c346f54b8281d1eb26c8d0 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/common/block/gpio/gpio.c 2 files changed, 91 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/21231/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 1826b48..0fc1b03 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -277,92 +277,3 @@ { return ACPI_BASE_ADDRESS; } - -static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) -{ - /* - * Store (\_SB.GPC0 (addr), Local5) - * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in - * gpiolib.asl. - */ - acpigen_write_store(); - acpigen_emit_namestring("\\_SB.GPC0"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); -} - -static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) -{ - assert(gpio_num < TOTAL_PADS); - uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); - - acpigen_soc_get_dw0_in_local5(addr); - - /* If (And (Local5, mask)) */ - acpigen_write_if_and(LOCAL5_OP, mask); - - /* Store (One, Local0) */ - acpigen_write_store_ops(ONE_OP, LOCAL0_OP); - - acpigen_pop_len(); /* If */ - - /* Else */ - acpigen_write_else(); - - /* Store (Zero, Local0) */ - acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); - - acpigen_pop_len(); /* Else */ - - return 0; -} - -static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) -{ - assert(gpio_num < TOTAL_PADS); - uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); - - acpigen_soc_get_dw0_in_local5(addr); - - if (val) { - /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ - acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); - } else { - /* Not (PAD_CFG0_TX_STATE, Local6) */ - acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); - - /* And (Local5, Local6, Local5) */ - acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); - } - - /* - * \_SB.SPC0 (addr, Local5) - * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in - * gpiolib.asl. - */ - acpigen_emit_namestring("\\_SB.SPC0"); - acpigen_write_integer(addr); - acpigen_emit_byte(LOCAL5_OP); - - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_set_gpio_val(gpio_num, 1); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_set_gpio_val(gpio_num, 0); -} diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index f77f88f..2370f2b 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -13,6 +13,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include <arch/acpigen.h> #include <assert.h> #include <intelblocks/gpio.h> #include <gpio.h> @@ -483,3 +484,93 @@ const struct pad_community *comm = gpio_get_community(gpio_num); return comm->acpi_path; } + +static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) +{ + /* + * Store (\_SB.GPC0 (addr), Local5) + * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in + * gpiolib.asl. + */ + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.GPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); +} + +static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t bit_mask) +{ + assert(gpio_num < TOTAL_PADS); + uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); + + acpigen_soc_get_dw0_in_local5(addr); + + /* If (And (Local5, mask)) */ + acpigen_write_if_and(LOCAL5_OP, bit_mask); + + /* Store (One, Local0) */ + acpigen_write_store_ops(ONE_OP, LOCAL0_OP); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + + /* Store (Zero, Local0) */ + acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); + + acpigen_pop_len(); /* Else */ + + return 0; +} + +static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) +{ + assert(gpio_num < TOTAL_PADS); + uintptr_t addr = (uintptr_t) gpio_dwx_address(gpio_num); + + acpigen_soc_get_dw0_in_local5(addr); + + if (val) { + /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ + acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); + } else { + /* Not (PAD_CFG0_TX_STATE, Local6) */ + acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); + + /* And (Local5, Local6, Local5) */ + acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); + } + + /* + * \_SB.SPC0 (addr, Local5) + * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in + * gpiolib.asl. + */ + acpigen_emit_namestring("\\_SB.SPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 1); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 0); +} + -- To view, visit https://review.coreboot.org/21231 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4e9ae9f37a4b524521c346f54b8281d1eb26c8d0 Gerrit-Change-Number: 21231 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: Makefile: Keep list of exported variables
by Patrick Georgi (Code Review) 28 Aug '17

28 Aug '17

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/21162 ) Change subject: Makefile: Keep list of exported variables ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/21162 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ce9eff32d817ec190441550116376843abd1c11 Gerrit-Change-Number: 21162 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 17:33:13 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017