coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/skylake: Move UNCORE PRMRR base and mask defines.
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21247 ) Change subject: soc/intel/skylake: Move UNCORE PRMRR base and mask defines. ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59432/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14740/ : SUCCESS -- To view, visit https://review.coreboot.org/21247 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170 Gerrit-Change-Number: 21247 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 23:42:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/common/systemagent: Add APIs to get SOC specific PRMRR base and...
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21243 ) Change subject: intel/common/systemagent: Add APIs to get SOC specific PRMRR base and mask ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14736/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59428/ : SUCCESS -- To view, visit https://review.coreboot.org/21243 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e787a2603aaa475cb5c61558cc31ec0afcb4a8b Gerrit-Change-Number: 21243 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 23:41:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Implement PRMRR get base and mask APIs
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21245 ) Change subject: soc/intel/skylake: Implement PRMRR get base and mask APIs ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59429/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14738/ : SUCCESS -- To view, visit https://review.coreboot.org/21245 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I880d3d88138809cdf030507877079cbea52a0d97 Gerrit-Change-Number: 21245 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 23:40:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Move UNCORE PRMRR base and mask defines.
by Pratikkumar V Prajapati (Code Review) 28 Aug '17

28 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21247 Change subject: soc/intel/skylake: Move UNCORE PRMRR base and mask defines. ...................................................................... soc/intel/skylake: Move UNCORE PRMRR base and mask defines. UNCORE PRMRR BASE and MASK MSRs are not common, so move to SOC specific header file and rename the #define to start with MSR_* Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21247/1 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 55d0bfd..6236915 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -72,8 +72,6 @@ #define PRMRR_PHYS_MASK_VALID (1 << 11) #define MSR_POWER_CTL 0x1fc #define MSR_EVICT_CTL 0x2e0 -#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 -#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 #define MSR_SGX_OWNEREPOCH0 0x300 #define MSR_SGX_OWNEREPOCH1 0x301 #define IA32_MC0_CTL 0x400 diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4ff4ad2..0bd7f3c 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -32,6 +32,8 @@ #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 #define MSR_VR_CURRENT_CONFIG 0x601 #define MSR_VR_MISC_CONFIG 0x603 #define MSR_VR_MISC_CONFIG2 0x636 diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 482107b..dbe0c94 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -50,8 +50,8 @@ "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", relo_params->uncore_emrr_base.lo, relo_params->uncore_emrr_mask.lo); - wrmsr(UNCORE_PRMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base); - wrmsr(UNCORE_PRMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask); + wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_emrr_base); + wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_emrr_mask); } static void update_save_state(int cpu, uintptr_t curr_smbase, diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index c1733df..8e3276d 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -66,12 +66,12 @@ int soc_get_uncore_prmmr_base(msr_t *prmrr_base) { - *prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); + *prmrr_base = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE); return 1; } int soc_get_uncore_prmmr_mask(msr_t *prmrr_mask) { - *prmrr_mask = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR); + *prmrr_mask = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK); return 1; } -- To view, visit https://review.coreboot.org/21247 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170 Gerrit-Change-Number: 21247 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/common/sgx: use SOC specific APIs to get PRMRR base and mask
by Pratikkumar V Prajapati (Code Review) 28 Aug '17

28 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21246 Change subject: soc/intel/common/sgx: use SOC specific APIs to get PRMRR base and mask ...................................................................... soc/intel/common/sgx: use SOC specific APIs to get PRMRR base and mask Use soc_get_uncore_prmmr_base() and soc_get_uncore_prmmr_msk() to get PRMRR base and mask respectively Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/sgx/sgx.c 1 file changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/21246/1 diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index da84ea6..a199a83 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -21,6 +21,7 @@ #include <cpu/intel/microcode.h> #include <intelblocks/mp_init.h> #include <intelblocks/sgx.h> +#include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> @@ -48,13 +49,27 @@ /* PRMRR base and mask are read from the UNCORE PRMRR MSRs * that are already set in FSP-M. */ - prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); - prmrr_mask = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR); + if (soc_get_uncore_prmmr_base(&prmrr_base) < 0) { + printk(BIOS_ERR, "SGX: Failed to read UNCORE PRMRR base\n"); + return; + } + if (!prmrr_base.lo) { printk(BIOS_ERR, "SGX Error: Uncore PRMRR is not set!\n"); return; } + printk(BIOS_INFO, "SGX: prmrr_base.hi = 0x%x\n", prmrr_base.hi); + printk(BIOS_INFO, "SGX: prmrr_base.lo = 0x%x\n", prmrr_base.lo); + + if (soc_get_uncore_prmmr_mask(&prmrr_mask) < 0) { + printk(BIOS_ERR, "SGX: Failed to read UNCORE PRMRR mask\n"); + return; + } + + printk(BIOS_INFO, "SGX: prmrr_mask.hi = 0x%x\n", prmrr_mask.hi); + printk(BIOS_INFO, "SGX: prmrr_mask.lo = 0x%x\n", prmrr_mask.lo); + msr = rdmsr(PRMRR_PHYS_MASK_MSR); /* If it is locked don't attempt to write PRMRR MSRs. */ if (msr.lo & PRMRR_PHYS_MASK_LOCK) -- To view, visit https://review.coreboot.org/21246 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646 Gerrit-Change-Number: 21246 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Implement PRMRR get base and mask APIs
by Pratikkumar V Prajapati (Code Review) 28 Aug '17

28 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21245 Change subject: soc/intel/skylake: Implement PRMRR get base and mask APIs ...................................................................... soc/intel/skylake: Implement PRMRR get base and mask APIs Implement following APIs for SKL/KBL - soc_get_uncore_prmmr_base() - soc_get_uncore_prmmr_mask() Change-Id: I880d3d88138809cdf030507877079cbea52a0d97 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/skylake/systemagent.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/21245/1 diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 6149fa2..c1733df 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -21,6 +21,7 @@ #include <intelblocks/systemagent.h> #include <soc/cpu.h> #include <soc/iomap.h> +#include <soc/msr.h> #include <soc/systemagent.h> /* @@ -62,3 +63,15 @@ mdelay(1); set_power_limits(28); } + +int soc_get_uncore_prmmr_base(msr_t *prmrr_base) +{ + *prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); + return 1; +} + +int soc_get_uncore_prmmr_mask(msr_t *prmrr_mask) +{ + *prmrr_mask = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR); + return 1; +} -- To view, visit https://review.coreboot.org/21245 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I880d3d88138809cdf030507877079cbea52a0d97 Gerrit-Change-Number: 21245 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Implement PRMRR get base and mask APIs
by Pratikkumar V Prajapati (Code Review) 28 Aug '17

28 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21244 Change subject: soc/intel/apollolake: Implement PRMRR get base and mask APIs ...................................................................... soc/intel/apollolake: Implement PRMRR get base and mask APIs Implement following APIs for APL/GLK - soc_get_uncore_prmmr_base() - soc_get_uncore_prmmr_mask() Change-Id: I57df1f0e8ff984f32de4efdc6ebd68be501b4799 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/apollolake/systemagent.c 1 file changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/21244/1 diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c index 22d801e..88fc8ad 100644 --- a/src/soc/intel/apollolake/systemagent.c +++ b/src/soc/intel/apollolake/systemagent.c @@ -38,3 +38,57 @@ sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); } + +int soc_get_uncore_prmmr_base(msr_t *prmrr_base) +{ + const void *prmrr_base_hob; + size_t prmrr_base_hob_size = 0; + uint64_t temp = 0; + + const uint8_t prmrr_phys_base_guid[16] = { + 0x38, 0x3a, 0x81, 0x9f, 0xb0, 0x6f, 0xa7, 0x4f, + 0xaf, 0x79, 0x8a, 0x4e, 0x74, 0xdd, 0x48, 0x33 + }; + + prmrr_base_hob = fsp_find_extension_hob_by_guid(prmrr_phys_base_guid, + &prmrr_base_hob_size); + + if (!prmrr_base_hob) { + printk(BIOS_ERR, "Failed to locate PRMRR base hob\n"); + return -1; + } + + temp = *(uint64_t *) prmrr_base_hob; + prmrr_base->lo = (uint32_t) temp; + prmrr_base->hi = temp >> 32; + + return 0; +} + +int soc_get_uncore_prmmr_mask(msr_t *prmrr_mask) +{ + const void *prmrr_size_hob; + size_t prmrr_size_hob_size = 0; + uint64_t prmrr_size = 0; + const uint64_t PRMRR_HOB_MASK = 0x07FFFFFFFFF; + uint64_t temp; + const uint8_t prmrr_size_guid[16] = { + 0x44, 0xed, 0x0b, 0x99, 0x4e, 0x9b, 0x26, 0x42, + 0xa5, 0x97, 0x28, 0x36, 0x76, 0x6b, 0x5c, 0x41 + }; + + prmrr_size_hob = fsp_find_extension_hob_by_guid(prmrr_size_guid, + &prmrr_size_hob_size); + + if (!prmrr_size_hob) { + printk(BIOS_ERR, "Failed to locate PRMRR size hob\n"); + return -1; + } + + prmrr_size = *(uint64_t *) prmrr_size_hob; + temp = PRMRR_HOB_MASK & (~((uint64_t) (prmrr_size - 1))); + prmrr_mask->lo = (uint32_t) temp; + prmrr_mask->hi = temp >> 32; + + return 0; +} -- To view, visit https://review.coreboot.org/21244 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I57df1f0e8ff984f32de4efdc6ebd68be501b4799 Gerrit-Change-Number: 21244 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: intel/common/systemagent: Add APIs to get SOC specific PRMRR base and...
by Pratikkumar V Prajapati (Code Review) 28 Aug '17

28 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21243 Change subject: intel/common/systemagent: Add APIs to get SOC specific PRMRR base and mask ...................................................................... intel/common/systemagent: Add APIs to get SOC specific PRMRR base and mask Implement weak definitions and SOC specific code would implement actual definitions. Change-Id: I5e787a2603aaa475cb5c61558cc31ec0afcb4a8b Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/21243/1 diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h index 5f04e36..a1c551f 100644 --- a/src/soc/intel/common/block/include/intelblocks/systemagent.h +++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h @@ -16,6 +16,7 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SA_H #define SOC_INTEL_COMMON_BLOCK_SA_H +#include <cpu/x86/msr.h> #include <device/device.h> #include <soc/iomap.h> #include <stddef.h> @@ -96,4 +97,7 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *resource_cnt); +/* SoC specific APIs to get UNCORE PRMRR base and mask values */ +int soc_get_uncore_prmmr_base(msr_t *prmrr_base); +int soc_get_uncore_prmmr_mask(msr_t *prmrr_mask); #endif /* SOC_INTEL_COMMON_BLOCK_SA_H */ diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index cb7af41..188548a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -36,6 +36,18 @@ /* no-op */ } +__attribute__((weak)) int soc_get_uncore_prmmr_base(msr_t *prmrr_base) +{ + /* return failure for this dummy API */ + return -1; +} + +__attribute__((weak)) int soc_get_uncore_prmmr_mask(msr_t *prmrr_mask) +{ + /* return failure for this dummy API */ + return -1; +} + /* * Add all known fixed MMIO ranges that hang off the host bridge/memory * controller device. -- To view, visit https://review.coreboot.org/21243 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5e787a2603aaa475cb5c61558cc31ec0afcb4a8b Gerrit-Change-Number: 21243 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: intel/common/cpulib: Add API to configure MCA
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21239 ) Change subject: intel/common/cpulib: Add API to configure MCA ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59427/ : SUCCESS -- To view, visit https://review.coreboot.org/21239 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e88c7527ce350824e48892caa978b2b78f1de20 Gerrit-Change-Number: 21239 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 22:24:36 +0000 Gerrit-HasComments: No

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Change in libgfxinit[master]: dp training: Allow to adjust pre-emphasis during clock recovery
by Nico Huber (Code Review) 28 Aug '17

28 Aug '17

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/21216 ) Change subject: dp training: Allow to adjust pre-emphasis during clock recovery ...................................................................... dp training: Allow to adjust pre-emphasis during clock recovery That's not demanded by the spec but there are sinks in the wild that need it. Change-Id: Ibef5236ca771e0e02beb4e76650ffb6974657846 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/21216 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M common/hw-gfx-dp_training.adb 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: Felix Held: Looks good to me, approved Nico Huber: Verified diff --git a/common/hw-gfx-dp_training.adb b/common/hw-gfx-dp_training.adb index e7411d0..a2d00a7 100644 --- a/common/hw-gfx-dp_training.adb +++ b/common/hw-gfx-dp_training.adb @@ -257,8 +257,9 @@ -- According to DP spec, only change preemphasis during channel -- equalization. What to do if sink requests it during clock recovery? - -- Linux always accepts new values from the sink, we don't, for now. - if Success and then (CR_Was_Done and not EQ_Done) then + -- Linux always accepts new values from the sink, we too, now: There + -- are sinks in the wild that need this. + if Success and not EQ_Done then Train_Set.Pre_Emph := DP_Info.Max_Requested_Emph (Status, Link); if Train_Set.Pre_Emph > Max_Pre_Emph (Port, Train_Set) -- To view, visit https://review.coreboot.org/21216 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ibef5236ca771e0e02beb4e76650ffb6974657846 Gerrit-Change-Number: 21216 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit August 2017