coreboot-gerrit August 2017

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Change in coreboot[master]: src/mainboard/Kconfig: split out options into own file
by Alexander Couzens (Code Review) 28 Aug '17

28 Aug '17

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/21236 Change subject: src/mainboard/Kconfig: split out options into own file ...................................................................... src/mainboard/Kconfig: split out options into own file Having includes in one file and option in another file is cleaner. Also prepare to move mainboard vendor and board selection upwards. Change-Id: I732dad9758817b0c5a4ade314489bf4d5662e60b Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- M src/mainboard/Kconfig A src/mainboard/Kconfig.mainboard 2 files changed, 158 insertions(+), 157 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/21236/1 diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index bdaa9e7..7367367 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -10,160 +10,4 @@ source "src/mainboard/*/Kconfig" -config BOARD_ROMSIZE_KB_64 - bool -config BOARD_ROMSIZE_KB_128 - bool -config BOARD_ROMSIZE_KB_256 - bool -config BOARD_ROMSIZE_KB_512 - bool -config BOARD_ROMSIZE_KB_1024 - bool -config BOARD_ROMSIZE_KB_2048 - bool -config BOARD_ROMSIZE_KB_4096 - bool -config BOARD_ROMSIZE_KB_8192 - bool -config BOARD_ROMSIZE_KB_12288 - bool -config BOARD_ROMSIZE_KB_16384 - bool -config BOARD_ROMSIZE_KB_32768 - bool -config BOARD_ROMSIZE_KB_65536 - bool - -# TODO: No help text possible for choice fields? -choice - prompt "ROM chip size" - default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 - default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 - default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 - default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 - default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 - default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 - default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 - default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 - default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 - default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 - default COREBOOT_ROMSIZE_KB_32768 if BOARD_ROMSIZE_KB_32768 - default COREBOOT_ROMSIZE_KB_65536 if BOARD_ROMSIZE_KB_65536 - help - Select the size of the ROM chip you intend to flash coreboot on. - - The build system will take care of creating a coreboot.rom file - of the matching size. - -config COREBOOT_ROMSIZE_KB_64 - bool "64 KB" - help - Choose this option if you have a 64 KB ROM chip. - -config COREBOOT_ROMSIZE_KB_128 - bool "128 KB" - help - Choose this option if you have a 128 KB ROM chip. - -config COREBOOT_ROMSIZE_KB_256 - bool "256 KB" - help - Choose this option if you have a 256 KB ROM chip. - -config COREBOOT_ROMSIZE_KB_512 - bool "512 KB" - help - Choose this option if you have a 512 KB ROM chip. - -config COREBOOT_ROMSIZE_KB_1024 - bool "1024 KB (1 MB)" - help - Choose this option if you have a 1024 KB (1 MB) ROM chip. - -config COREBOOT_ROMSIZE_KB_2048 - bool "2048 KB (2 MB)" - help - Choose this option if you have a 2048 KB (2 MB) ROM chip. - -config COREBOOT_ROMSIZE_KB_4096 - bool "4096 KB (4 MB)" - help - Choose this option if you have a 4096 KB (4 MB) ROM chip. - -config COREBOOT_ROMSIZE_KB_8192 - bool "8192 KB (8 MB)" - help - Choose this option if you have a 8192 KB (8 MB) ROM chip. - -config COREBOOT_ROMSIZE_KB_12288 - bool "12288 KB (12 MB)" - help - Choose this option if you have a 12288 KB (12 MB) ROM chip. - -config COREBOOT_ROMSIZE_KB_16384 - bool "16384 KB (16 MB)" - help - Choose this option if you have a 16384 KB (16 MB) ROM chip. - -config COREBOOT_ROMSIZE_KB_32768 - bool "32768 KB (32 MB)" - help - Choose this option if you have a 32768 KB (32 MB) ROM chip. - -config COREBOOT_ROMSIZE_KB_65536 - bool "65536 KB (64 MB)" - help - Choose this option if you have a 65536 KB (64 MB) ROM chip. - -endchoice - -# Map the config names to an integer (KB). -config COREBOOT_ROMSIZE_KB - int - default 64 if COREBOOT_ROMSIZE_KB_64 - default 128 if COREBOOT_ROMSIZE_KB_128 - default 256 if COREBOOT_ROMSIZE_KB_256 - default 512 if COREBOOT_ROMSIZE_KB_512 - default 1024 if COREBOOT_ROMSIZE_KB_1024 - default 2048 if COREBOOT_ROMSIZE_KB_2048 - default 4096 if COREBOOT_ROMSIZE_KB_4096 - default 8192 if COREBOOT_ROMSIZE_KB_8192 - default 12288 if COREBOOT_ROMSIZE_KB_12288 - default 16384 if COREBOOT_ROMSIZE_KB_16384 - default 32768 if COREBOOT_ROMSIZE_KB_32768 - default 65536 if COREBOOT_ROMSIZE_KB_65536 - -# Map the config names to a hex value (bytes). -config ROM_SIZE - hex - default 0x10000 if COREBOOT_ROMSIZE_KB_64 - default 0x20000 if COREBOOT_ROMSIZE_KB_128 - default 0x40000 if COREBOOT_ROMSIZE_KB_256 - default 0x80000 if COREBOOT_ROMSIZE_KB_512 - default 0x100000 if COREBOOT_ROMSIZE_KB_1024 - default 0x200000 if COREBOOT_ROMSIZE_KB_2048 - default 0x400000 if COREBOOT_ROMSIZE_KB_4096 - default 0x800000 if COREBOOT_ROMSIZE_KB_8192 - default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 - default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 - default 0x2000000 if COREBOOT_ROMSIZE_KB_32768 - default 0x4000000 if COREBOOT_ROMSIZE_KB_65536 - -config ENABLE_POWER_BUTTON - bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL - default y if POWER_BUTTON_DEFAULT_ENABLE - default n if POWER_BUTTON_DEFAULT_DISABLE - help - The selected mainboard can optionally have the power button tied - to ground with a jumper so that the button appears to be - constantly depressed. If this option is enabled and the jumper is - installed then the board will turn on, but turn off again after a - short timeout, usually 4 seconds. - - Select Y here if you have removed the jumper and want to use an - actual power button. Select N if you have the jumper installed. - -config ENABLE_POWER_BUTTON - def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE - def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE +source "src/mainboard/Kconfig.mainboard" diff --git a/src/mainboard/Kconfig.mainboard b/src/mainboard/Kconfig.mainboard new file mode 100644 index 0000000..babbb95 --- /dev/null +++ b/src/mainboard/Kconfig.mainboard @@ -0,0 +1,157 @@ +config BOARD_ROMSIZE_KB_64 + bool +config BOARD_ROMSIZE_KB_128 + bool +config BOARD_ROMSIZE_KB_256 + bool +config BOARD_ROMSIZE_KB_512 + bool +config BOARD_ROMSIZE_KB_1024 + bool +config BOARD_ROMSIZE_KB_2048 + bool +config BOARD_ROMSIZE_KB_4096 + bool +config BOARD_ROMSIZE_KB_8192 + bool +config BOARD_ROMSIZE_KB_12288 + bool +config BOARD_ROMSIZE_KB_16384 + bool +config BOARD_ROMSIZE_KB_32768 + bool +config BOARD_ROMSIZE_KB_65536 + bool + +# TODO: No help text possible for choice fields? +choice + prompt "ROM chip size" + default COREBOOT_ROMSIZE_KB_64 if BOARD_ROMSIZE_KB_64 + default COREBOOT_ROMSIZE_KB_128 if BOARD_ROMSIZE_KB_128 + default COREBOOT_ROMSIZE_KB_256 if BOARD_ROMSIZE_KB_256 + default COREBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 + default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 + default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 + default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 + default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 + default COREBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 + default COREBOOT_ROMSIZE_KB_32768 if BOARD_ROMSIZE_KB_32768 + default COREBOOT_ROMSIZE_KB_65536 if BOARD_ROMSIZE_KB_65536 + help + Select the size of the ROM chip you intend to flash coreboot on. + + The build system will take care of creating a coreboot.rom file + of the matching size. + +config COREBOOT_ROMSIZE_KB_64 + bool "64 KB" + help + Choose this option if you have a 64 KB ROM chip. + +config COREBOOT_ROMSIZE_KB_128 + bool "128 KB" + help + Choose this option if you have a 128 KB ROM chip. + +config COREBOOT_ROMSIZE_KB_256 + bool "256 KB" + help + Choose this option if you have a 256 KB ROM chip. + +config COREBOOT_ROMSIZE_KB_512 + bool "512 KB" + help + Choose this option if you have a 512 KB ROM chip. + +config COREBOOT_ROMSIZE_KB_1024 + bool "1024 KB (1 MB)" + help + Choose this option if you have a 1024 KB (1 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_2048 + bool "2048 KB (2 MB)" + help + Choose this option if you have a 2048 KB (2 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_4096 + bool "4096 KB (4 MB)" + help + Choose this option if you have a 4096 KB (4 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_8192 + bool "8192 KB (8 MB)" + help + Choose this option if you have a 8192 KB (8 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_12288 + bool "12288 KB (12 MB)" + help + Choose this option if you have a 12288 KB (12 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_16384 + bool "16384 KB (16 MB)" + help + Choose this option if you have a 16384 KB (16 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_32768 + bool "32768 KB (32 MB)" + help + Choose this option if you have a 32768 KB (32 MB) ROM chip. + +config COREBOOT_ROMSIZE_KB_65536 + bool "65536 KB (64 MB)" + help + Choose this option if you have a 65536 KB (64 MB) ROM chip. + +endchoice + +# Map the config names to an integer (KB). +config COREBOOT_ROMSIZE_KB + int + default 64 if COREBOOT_ROMSIZE_KB_64 + default 128 if COREBOOT_ROMSIZE_KB_128 + default 256 if COREBOOT_ROMSIZE_KB_256 + default 512 if COREBOOT_ROMSIZE_KB_512 + default 1024 if COREBOOT_ROMSIZE_KB_1024 + default 2048 if COREBOOT_ROMSIZE_KB_2048 + default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 8192 if COREBOOT_ROMSIZE_KB_8192 + default 12288 if COREBOOT_ROMSIZE_KB_12288 + default 16384 if COREBOOT_ROMSIZE_KB_16384 + default 32768 if COREBOOT_ROMSIZE_KB_32768 + default 65536 if COREBOOT_ROMSIZE_KB_65536 + +# Map the config names to a hex value (bytes). +config ROM_SIZE + hex + default 0x10000 if COREBOOT_ROMSIZE_KB_64 + default 0x20000 if COREBOOT_ROMSIZE_KB_128 + default 0x40000 if COREBOOT_ROMSIZE_KB_256 + default 0x80000 if COREBOOT_ROMSIZE_KB_512 + default 0x100000 if COREBOOT_ROMSIZE_KB_1024 + default 0x200000 if COREBOOT_ROMSIZE_KB_2048 + default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x800000 if COREBOOT_ROMSIZE_KB_8192 + default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 + default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 + default 0x2000000 if COREBOOT_ROMSIZE_KB_32768 + default 0x4000000 if COREBOOT_ROMSIZE_KB_65536 + +config ENABLE_POWER_BUTTON + bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL + default y if POWER_BUTTON_DEFAULT_ENABLE + default n if POWER_BUTTON_DEFAULT_DISABLE + help + The selected mainboard can optionally have the power button tied + to ground with a jumper so that the button appears to be + constantly depressed. If this option is enabled and the jumper is + installed then the board will turn on, but turn off again after a + short timeout, usually 4 seconds. + + Select Y here if you have removed the jumper and want to use an + actual power button. Select N if you have the jumper installed. + +config ENABLE_POWER_BUTTON + def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE + def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE -- To view, visit https://review.coreboot.org/21236 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I732dad9758817b0c5a4ade314489bf4d5662e60b Gerrit-Change-Number: 21236 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu>

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Change in libgfxinit[master]: gma: Fix refined contract of Initialize()
by Patrick Georgi (Code Review) 28 Aug '17

28 Aug '17

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/21207 ) Change subject: gma: Fix refined contract of Initialize() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/21207 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I86e42163d7847f7011bcf9a0ef5c2c7f25b4b1be Gerrit-Change-Number: 21207 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 28 Aug 2017 14:18:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registe...
by Subrata Banik (Code Review) 28 Aug '17

28 Aug '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/21235 ) Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP] ...................................................................... Patch Set 6: i need to split this patch logically to make some code into common and soc can use the same, -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 28 Aug 2017 14:07:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registe...
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21235 ) Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP] ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14714/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59405/ : SUCCESS -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 28 Aug 2017 13:46:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registe...
by Subrata Banik (Code Review) 28 Aug '17

28 Aug '17

Hello dhaval v sharma, Balaji Manigandan, build bot (Jenkins), Lijian Zhao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21235 to look at the new patch set (#6). Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP] ...................................................................... soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP] This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot cannonlake RVP successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. 6. Enable C6 DRAM with PRMRR size 0MB and boot to OS. Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/systemagent.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/romstage.c 5 files changed, 142 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/21235/6 -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registe...
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21235 ) Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP] ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59404/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14713/ : SUCCESS -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 28 Aug 2017 13:29:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registe...
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21235 ) Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP] ...................................................................... Patch Set 4: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59403/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14712/ : SUCCESS -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 28 Aug 2017 13:20:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registe...
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21235 ) Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers [WIP] ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59402/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14711/ : SUCCESS -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 28 Aug 2017 13:10:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registers
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21235 ) Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59401/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14710/ : SUCCESS -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 28 Aug 2017 12:57:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registers
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21235 ) Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/59400/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14709/ : SUCCESS -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 28 Aug 2017 12:51:03 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017