coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/cannonlake: Usable dram top calculation based on HW registers
by Subrata Banik (Code Review) 28 Aug '17

28 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21235 Change subject: soc/intel/cannonlake: Usable dram top calculation based on HW registers ...................................................................... soc/intel/cannonlake: Usable dram top calculation based on HW registers This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot cannonlake RVP successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. 6. Enable C6 DRAM with PRMRR size 0MB and boot to OS. Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/include/soc/systemagent.h M src/soc/intel/cannonlake/memmap.c 3 files changed, 99 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/21235/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 48305fe..9b50846 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -186,6 +186,8 @@ /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; + /* Enable C6 DRAM */ + uint8_t enable_c6dram; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h index 1902314..da83c38 100644 --- a/src/soc/intel/cannonlake/include/soc/systemagent.h +++ b/src/soc/intel/cannonlake/include/soc/systemagent.h @@ -40,4 +40,7 @@ #define MCH_DDR_POWER_LIMIT_LO 0x58e0 #define MCH_DDR_POWER_LIMIT_HI 0x58e4 +#define IMRBASE 0x6A40 +#define IMRLIMIT 0x6A48 + #endif diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 8b487f6..1b6e6da 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -34,15 +34,105 @@ write32(top_of_ram_register(), 0); } +/* + * Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | DMA Protected Region | + * +--------------------------+ DPR + * | PRM (C6DRAM/SGX) | + * +--------------------------+ PRMRR + * | ME Stolen Memory | + * +--------------------------+ ME Stolen + * | PTT | + * +--------------------------+ top_of_ram + * | Reserved - FSP/CBMEM | + * +--------------------------+ TOLUM + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal making the size of those + * regions 0. The reason is because the memory controller internally subtracts + * the base registers from each other to determine sizes of the regions. In + * other words, the memory map is in a fixed order no matter what. + */ +static u32 calculate_dram_base(void) +{ + const struct soc_intel_cannonlake_config *config; + const struct device *dev; + uint32_t dram_base; + uint32_t prmrr_base; + size_t prmrr_size; + size_t imr_size; + + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); + + /* Read TOLUD from Host Bridge offset */ + dram_base = sa_get_tolud_base(); + + if (dev->enabled) { + /* Read BDSM from Host Bridge */ + dram_base -= sa_get_dsm_size(); + + /* Read BGSM from Host Bridge */ + dram_base -= sa_get_gsm_size(); + } + /* Get TSEG size */ + dram_base -= smm_region_size(); + + /* Get DPR size */ + if (IS_ENABLED(CONFIG_SA_ENABLE_DPR)) + dram_base -= sa_get_dpr_size(); + + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); + config = dev->chip_info; + prmrr_size = config->PrmrrSize; + + if (prmrr_size > 0) { + /* + * PRMRR Sizes that are > 1MB and < 32MB are + * not supported and will fail out. + */ + if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB)) + die("PRMRR Sizes that are > 1MB and < 32MB are not" + "supported!\n"); + + prmrr_base = dram_base - prmrr_size; + if (prmrr_size >= 32*MiB) + prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB); + dram_base = prmrr_base; + } else if (config->enable_c6dram && prmrr_size == 0) { + /* Allocate PRMRR memory for C6DRAM */ + dram_base -= 1*MiB; + } + + /* ME stolen memory */ + imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE); + if (imr_size > 0) + dram_base -= imr_size; + + if (is_ptt_enable()) + dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */ + + return dram_base; +} + void cbmem_top_init(void) { - struct range_entry fsp_mem; uintptr_t top; - if (fsp_find_reserved_memory(&fsp_mem)) - die("Can't file top of ram.\n"); + top = calculate_dram_base(); - top = ALIGN_UP(range_entry_base(&fsp_mem), 16 * MiB); write32(top_of_ram_register(), top); } -- To view, visit https://review.coreboot.org/21235 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Gerrit-Change-Number: 21235 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in libhwbase[master]: linux pci: Add dummy PCI access for shared contracts
by Nico Huber (Code Review) 28 Aug '17

28 Aug '17

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Change in libhwbase[master]: linux pci: Add dummy PCI access for shared contracts
by Nico Huber (Code Review) 28 Aug '17

28 Aug '17

Hello Adrian-Ken Rueegsegger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21206 to look at the new patch set (#2). Change subject: linux pci: Add dummy PCI access for shared contracts ...................................................................... linux pci: Add dummy PCI access for shared contracts Other implementations may update the PCI_State in Resource_Size() and Map(). To share the contract with those implementations, we have to simulate such accesses. Change-Id: If994db22d91eb3707e555871d854c3a25a13678b Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/linux/hw-pci-dev.adb 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libhwbase refs/changes/06/21206/2 -- To view, visit https://review.coreboot.org/21206 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If994db22d91eb3707e555871d854c3a25a13678b Gerrit-Change-Number: 21206 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: sb/amd/sb700/lpc.c: Optimize code flow for less indentation
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21234 ) Change subject: sb/amd/sb700/lpc.c: Optimize code flow for less indentation ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14708/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59399/ : SUCCESS -- To view, visit https://review.coreboot.org/21234 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I50ca99a759a276e9d49327c6ae6c69eeab2a8c90 Gerrit-Change-Number: 21234 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 11:10:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/sb/sb700: Allocate wide LPC I/O devices where possible
by Arthur Heymans (Code Review) 28 Aug '17

28 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/21217 ) Change subject: amd/sb/sb700: Allocate wide LPC I/O devices where possible ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/21217/1/src/southbridge/amd/sb700/lpc.c File src/southbridge/amd/sb700/lpc.c: https://review.coreboot.org/#/c/21217/1/src/southbridge/amd/sb700/lpc.c@a166 PS1, Line 166: : > Could the indentation be reduced by simply doing "continue" on the opposite done in https://review.coreboot.org/#/c/21234/ -- To view, visit https://review.coreboot.org/21217 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I004bd0be31c91b76ae2a5e72690b44dca2fd9297 Gerrit-Change-Number: 21217 Gerrit-PatchSet: 1 Gerrit-Owner: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 11:05:15 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/amd/sb700/lpc.c: Optimize code flow for less indentation
by Arthur Heymans (Code Review) 28 Aug '17

28 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21234 Change subject: sb/amd/sb700/lpc.c: Optimize code flow for less indentation ...................................................................... sb/amd/sb700/lpc.c: Optimize code flow for less indentation This changes the code flow so less indentation has to be used. This also changes some lines to limit their length. Change-Id: I50ca99a759a276e9d49327c6ae6c69eeab2a8c90 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/amd/sb700/lpc.c 1 file changed, 74 insertions(+), 72 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/21234/1 diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 8ee0395..281e247 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -163,83 +163,85 @@ device_t child; for (child = link->children; child; child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - u32 base, end; /* don't need long long */ - if (!(res->flags & IORESOURCE_IO)) + if (!(child->enabled + && (child->path.type == DEVICE_PATH_PNP))) + continue; + + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); + printk(BIOS_DEBUG, "sb700 lpc decode:%s," + " base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + reg |= (1 << 29); + break; + case 0x3f8: /* COM1 */ + reg |= (1 << 6); + break; + case 0x2f8: /* COM2 */ + reg |= (1 << 7); + break; + case 0x378: /* Parallel 1 */ + reg |= (1 << 0); + reg |= (1 << 1); /* + 0x778 for ECP */ + break; + case 0x3f0: /* FD0 */ + reg |= (1 << 26); + break; + case 0x220: /* Audio 0 */ + reg |= (1 << 8); + break; + case 0x300: /* Midi 0 */ + reg |= (1 << 18); + break; + case 0x400: + reg_x |= (1 << 16); + break; + case 0x480: + reg_x |= (1 << 17); + break; + case 0x500: + reg_x |= (1 << 18); + break; + case 0x580: + reg_x |= (1 << 19); + break; + case 0x4700: + reg_x |= (1 << 22); + break; + case 0xfd60: + reg_x |= (1 << 23); + break; + default: + if (var_num >= 3) + /* only 3 var ; compact them ? */ continue; - base = res->base; - end = resource_end(res); - printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); - switch (base) { - case 0x60: /* KB */ - case 0x64: /* MS */ - reg |= (1 << 29); + switch (var_num) { + case 0: + reg_x |= (1 << 2); + if ((end - base) < 16) + wiosize |= (1 << 0); break; - case 0x3f8: /* COM1 */ - reg |= (1 << 6); + case 1: + reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 2); break; - case 0x2f8: /* COM2 */ - reg |= (1 << 7); + case 2: + reg_x |= (1 << 25); + reg_x |= (1 << 24); + if ((end - base) < 16) + wiosize |= (1 << 3); break; - case 0x378: /* Parallel 1 */ - reg |= (1 << 0); - reg |= (1 << 1); /* + 0x778 for ECP */ - break; - case 0x3f0: /* FD0 */ - reg |= (1 << 26); - break; - case 0x220: /* Audio 0 */ - reg |= (1 << 8); - break; - case 0x300: /* Midi 0 */ - reg |= (1 << 18); - break; - case 0x400: - reg_x |= (1 << 16); - break; - case 0x480: - reg_x |= (1 << 17); - break; - case 0x500: - reg_x |= (1 << 18); - break; - case 0x580: - reg_x |= (1 << 19); - break; - case 0x4700: - reg_x |= (1 << 22); - break; - case 0xfd60: - reg_x |= (1 << 23); - break; - default: - if (var_num >= 3) - continue; /* only 3 var ; compact them ? */ - switch (var_num) { - case 0: - reg_x |= (1 << 2); - if ((end - base) < 16) - wiosize |= (1 << 0); - break; - case 1: - reg_x |= (1 << 24); - if ((end - base) < 16) - wiosize |= (1 << 2); - break; - case 2: - reg_x |= (1 << 25); - reg_x |= (1 << 24); - if ((end - base) < 16) - wiosize |= (1 << 3); - break; - } - reg_var[var_num++] = - base & 0xffff; } + reg_var[var_num++] = base & 0xffff; } } } -- To view, visit https://review.coreboot.org/21234 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I50ca99a759a276e9d49327c6ae6c69eeab2a8c90 Gerrit-Change-Number: 21234 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in libhwbase[master]: linux pci: Add dummy PCI access for shared contracts
by Nico Huber (Code Review) 28 Aug '17

28 Aug '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/21206 ) Change subject: linux pci: Add dummy PCI access for shared contracts ...................................................................... Patch Set 1: (1 comment) > (1 comment) > > Instead of faking an access on Linux another potential approach > could be to explicitly specify the global contracts and accept/ > justify the warning in the Linux implementation using pragma > Annotate (GNATprove). This only just became feasible since GNATprove's flow analysis doesn't seem to explode any more when you give explicit contracts in generic packages. A first test seems to work with SPARK GPL 2017. > > Have not tested it and will result in more code due to contracts. > On the other hand one would avoid the automatic contract > generation... I'm planning to use more explicit contracts once I've tested newer GNATprove versions more thoroughly. Especially such cases with a contract shared among different implementations deserve an explicit contract (i.e. lesson learned). Though, I'm not fond of warning justifications and try to avoid them where possible. Maybe that changes once GNAT developers stop rewording the warnings ;) https://review.coreboot.org/#/c/21206/1/common/linux/hw-pci-dev.adb File common/linux/hw-pci-dev.adb: https://review.coreboot.org/#/c/21206/1/common/linux/hw-pci-dev.adb@44 PS1, Line 44: package Dummy is > Wrapping the procedure in a Dummy package is not necessary. Is there a part Hmmm, IIRC, I was forced to this pattern by some upstream GNAT version once and applied it ever since. I'll retest with coreboot's current reference toolchain (GCC 6.3). Maybe it's not needed any more. -- To view, visit https://review.coreboot.org/21206 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If994db22d91eb3707e555871d854c3a25a13678b Gerrit-Change-Number: 21206 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 28 Aug 2017 10:24:23 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: google/Bruce: Add Raydium touch screen support
by build bot (Jenkins) (Code Review) 28 Aug '17

28 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21233 ) Change subject: google/Bruce: Add Raydium touch screen support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14707/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59398/ : SUCCESS -- To view, visit https://review.coreboot.org/21233 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7 Gerrit-Change-Number: 21233 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 28 Aug 2017 09:35:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/Bruce: Add Raydium touch screen support
by Pan Sheng-Liang (Code Review) 28 Aug '17

28 Aug '17

Pan Sheng-Liang has uploaded this change for review. ( https://review.coreboot.org/21233 Change subject: google/Bruce: Add Raydium touch screen support ...................................................................... google/Bruce: Add Raydium touch screen support Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64705535 BRANCH=master TEST=emerge-coral coreboot Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan(a)quantatw.com> --- M src/mainboard/google/reef/variants/coral/devicetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/21233/1 diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index d5f546c..4f889d8 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -188,6 +188,13 @@ register "has_power_resource" = "1" device i2c 10 on end end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 39 on end + end end # - I2C 3 device pci 17.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/21233 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7 Gerrit-Change-Number: 21233 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com>

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Change in libhwbase[master]: linux pci: Add dummy PCI access for shared contracts
by Adrian-Ken Rueegsegger (Code Review) 28 Aug '17

28 Aug '17

Adrian-Ken Rueegsegger has posted comments on this change. ( https://review.coreboot.org/21206 ) Change subject: linux pci: Add dummy PCI access for shared contracts ...................................................................... Patch Set 1: (1 comment) Instead of faking an access on Linux another potential approach could be to explicitly specify the global contracts and accept/justify the warning in the Linux implementation using pragma Annotate (GNATprove). Have not tested it and will result in more code due to contracts. On the other hand one would avoid the automatic contract generation... https://review.coreboot.org/#/c/21206/1/common/linux/hw-pci-dev.adb File common/linux/hw-pci-dev.adb: https://review.coreboot.org/#/c/21206/1/common/linux/hw-pci-dev.adb@44 PS1, Line 44: package Dummy is Wrapping the procedure in a Dummy package is not necessary. Is there a particular reason for it? -- To view, visit https://review.coreboot.org/21206 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If994db22d91eb3707e555871d854c3a25a13678b Gerrit-Change-Number: 21206 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 28 Aug 2017 09:07:53 +0000 Gerrit-HasComments: Yes

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coreboot-gerrit August 2017