coreboot-gerrit August 2017

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Change in coreboot[master]: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20970 ) Change subject: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58471/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13873/ : SUCCESS -- To view, visit https://review.coreboot.org/20970 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iebe8aa1c4c3019414c6a23404cc5dc7f668cd8eb Gerrit-Change-Number: 20970 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 18:52:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/amd/mct_ddr3/mct_d.c: Break out of allow_config_restore loop
by Arthur Heymans (Code Review) 12 Aug '17

12 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20971 Change subject: nb/amd/mct_ddr3/mct_d.c: Break out of allow_config_restore loop ...................................................................... nb/amd/mct_ddr3/mct_d.c: Break out of allow_config_restore loop No need to further search for non matching SPD when first one is found. Change-Id: Ie669d1bc38411e40ab95c28b17ee8818874dc741 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/20971/1 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index da803ff..e4612f1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2715,9 +2715,12 @@ struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; - if (pDCTstat->NodePresent) - if (!pDCTstat->spd_data.nvram_spd_match) + if (pDCTstat->NodePresent) { + if (!pDCTstat->spd_data.nvram_spd_match) { allow_config_restore = 0; + break; + } + } } /* FIXME -- To view, visit https://review.coreboot.org/20971 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie669d1bc38411e40ab95c28b17ee8818874dc741 Gerrit-Change-Number: 20971 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS
by Arthur Heymans (Code Review) 12 Aug '17

12 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20970 to look at the new patch set (#2). Change subject: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS ...................................................................... nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS Was presumably missed when linking most amd fam10 files in 75a3d1fb7c: "amdfam10: Perform major include ".c" cleanup". Change-Id: Iebe8aa1c4c3019414c6a23404cc5dc7f668cd8eb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/amdfam10/debug.c M src/northbridge/amd/amdfam10/debug.h M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct/mct_d.h 4 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/20970/2 -- To view, visit https://review.coreboot.org/20970 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iebe8aa1c4c3019414c6a23404cc5dc7f668cd8eb Gerrit-Change-Number: 20970 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20970 ) Change subject: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58470/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13872/ : SUCCESS -- To view, visit https://review.coreboot.org/20970 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iebe8aa1c4c3019414c6a23404cc5dc7f668cd8eb Gerrit-Change-Number: 20970 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 18:19:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS
by Arthur Heymans (Code Review) 12 Aug '17

12 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20970 Change subject: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS ...................................................................... nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS Was presumably missed when linking most amd fam10 files in 75a3d1fb7c: "amdfam10: Perform major include ".c" cleanup". Change-Id: Iebe8aa1c4c3019414c6a23404cc5dc7f668cd8eb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/amdfam10/debug.c M src/northbridge/amd/amdfam10/debug.h 2 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/20970/1 diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index 067c299..762295b 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -18,6 +18,9 @@ #include <arch/io.h> #include <device/pci_def.h> #include <delay.h> +#include "amdfam10.h" + +extern int spd_read_byte(u32 device, u32 address); void print_debug_addr(const char *str, void *val) { @@ -222,7 +225,7 @@ if ((j & 0xf) == 0) { printk(BIOS_DEBUG, "\n%02x: ", j); } - status = smbus_read_byte(device, j); + status = spd_read_byte(device, j); if (status < 0) { break; } @@ -241,7 +244,7 @@ if ((j & 0xf) == 0) { printk(BIOS_DEBUG, "\n%02x: ", j); } - status = smbus_read_byte(device, j); + status = spd_read_byte(device, j); if (status < 0) { break; } @@ -259,12 +262,12 @@ printk(BIOS_DEBUG, "\n"); for (device = 1; device < 0x80; device++) { int j; - if (smbus_read_byte(device, 0) < 0) continue; + if (spd_read_byte(device, 0) < 0) continue; printk(BIOS_DEBUG, "smbus: %02x", device); for (j = 0; j < 256; j++) { int status; u8 byte; - status = smbus_read_byte(device, j); + status = spd_read_byte(device, j); if (status < 0) { break; } diff --git a/src/northbridge/amd/amdfam10/debug.h b/src/northbridge/amd/amdfam10/debug.h index a4ecfe9..0afa1b3 100644 --- a/src/northbridge/amd/amdfam10/debug.h +++ b/src/northbridge/amd/amdfam10/debug.h @@ -18,6 +18,7 @@ #include <inttypes.h> #include "pci.h" +#include "amdfam10.h" void print_debug_addr(const char *str, void *val); void print_debug_pci_dev(u32 dev); -- To view, visit https://review.coreboot.org/20970 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iebe8aa1c4c3019414c6a23404cc5dc7f668cd8eb Gerrit-Change-Number: 20970 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: console: Add weak method to notify about death
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19696 ) Change subject: console: Add weak method to notify about death ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58469/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13871/ : SUCCESS -- To view, visit https://review.coreboot.org/19696 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I71f8ddfc96047e8a0d39f084588db1fe2f251612 Gerrit-Change-Number: 19696 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 14:55:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8: Add panic method
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19695 ) Change subject: ec/lenovo/h8: Add panic method ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58468/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13870/ : SUCCESS -- To view, visit https://review.coreboot.org/19695 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id34d399f154952a48c1f4ccb0c41a238b2d7ccb8 Gerrit-Change-Number: 19695 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 14:40:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] drv/intel/gma/opregion: Add common init_idg_opregion()
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20969 ) Change subject: [WIP] drv/intel/gma/opregion: Add common init_idg_opregion() ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58467/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13869/ : SUCCESS -- To view, visit https://review.coreboot.org/20969 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970 Gerrit-Change-Number: 20969 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 14:07:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] drv/intel/gma/opregion: Add common init_idg_opregion()
by Patrick Rudolph (Code Review) 12 Aug '17

12 Aug '17

Hello Matt DeVillier, I'd like you to do a code review. Please visit https://review.coreboot.org/20969 to review the following change. Change subject: [WIP] drv/intel/gma/opregion: Add common init_idg_opregion() ...................................................................... [WIP] drv/intel/gma/opregion: Add common init_idg_opregion() Add a new common method to initialize ACPI OpRegion. * Try to locate vbt.bin in CBFS. * Try to locate VBIOS in CBFS. * Keep existing code to probe at 0xc0000. Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/intel/gma/opregion.c 1 file changed, 115 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/20969/1 diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index e9cbba1..d557204 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -17,6 +17,7 @@ #include <arch/acpi.h> #include <types.h> #include <string.h> +#include <cbfs.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -67,12 +68,14 @@ } } +/* + * Try to locate Intel VBIOS at 0xc0000. It might have been placed by + * Native Graphics Init as fake Option ROM or when coreboot did run the + * VBIOS on legacy platforms. + * TODO: Place generated fake VBT in CBMEM and get rid of this. + */ static void *get_intel_vbios(void) { - /* This should probably be looking at CBFS or we should always - * deploy the VBIOS on Intel systems, even if we don't run it - * in coreboot (e.g. SeaBIOS only scenarios). - */ u8 *vbios = (u8 *)0xc0000; optionrom_header_t *oprom = (optionrom_header_t *)vbios; @@ -80,61 +83,129 @@ oprom->pcir_offset); printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n", - oprom->signature, pcir->vendor, pcir->classcode[0], - pcir->classcode[1], pcir->classcode[2]); + oprom->signature, pcir->vendor, pcir->classcode[0], + pcir->classcode[1], pcir->classcode[2]); if ((oprom->signature == OPROM_SIGNATURE) && - (pcir->vendor == PCI_VENDOR_ID_INTEL) && - (pcir->classcode[0] == 0x00) && - (pcir->classcode[1] == 0x00) && - (pcir->classcode[2] == 0x03)) + (pcir->vendor == PCI_VENDOR_ID_INTEL) && + (pcir->classcode[0] == 0x00) && + (pcir->classcode[1] == 0x00) && + (pcir->classcode[2] == 0x03)) return (void *)vbios; return NULL; } -static enum cb_err init_opregion_vbt(igd_opregion_t *opregion) -{ - void *vbios; - vbios = get_intel_vbios(); - if (!vbios) { - printk(BIOS_DEBUG, "VBIOS not found.\n"); - return CB_ERR; - } - - printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios); - optionrom_header_t *oprom = (optionrom_header_t *)vbios; - optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios + - oprom->vbt_offset); - - if (read32(vbt->hdr_signature) != VBT_SIGNATURE) { - printk(BIOS_DEBUG, "VBT not found!\n"); - return CB_ERR; - } - - memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); - memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ? - vbt->hdr_vbt_size : 7168); - - return CB_SUCCESS; -} - /* Initialize IGD OpRegion, called from ACPI code and OS drivers */ -enum cb_err intel_gma_init_igd_opregion(igd_opregion_t *opregion) +enum cb_err +intel_gma_init_igd_opregion(igd_opregion_t *opregion) { - enum cb_err ret; + struct region_device vbt_rdev; + optionrom_vbt_t *vbt = NULL; + optionrom_vbt_t *ext_vbt; + struct cbfsf file_desc; + bool need_unmap = false; - memset((void *)opregion, 0, sizeof(igd_opregion_t)); + /* try to locate vbt.bin in CBFS */ + if (cbfs_boot_locate(&file_desc, "vbt.bin", NULL) == CB_SUCCESS) { + cbfs_file_data(&vbt_rdev, &file_desc); + vbt = rdev_mmap_full(&vbt_rdev); + if (vbt) { + uint32_t vbtsig = 0; + /* Validate the vbt file */ + memcpy(&vbtsig, vbt, sizeof(uint32_t)); + if (vbtsig == VBT_SIGNATURE) { + need_unmap = true; + } else { + printk(BIOS_ERR, + "GMA: Invalid signature in VBT data" + " file (vbt.bin)!\n"); + rdev_munmap(&vbt_rdev, vbt); + vbt = NULL; + } + } else { + printk(BIOS_ERR, "GMA: VBT couldn't be read\n"); + } + } else { + printk(BIOS_NOTICE, + "GMA: Could not locate a VBT file in CBFS\n"); + } - // FIXME if IGD is disabled, we should exit here. + /* If no vbt.bin, try to load from VBIOS in CBFS */ + if (!vbt) { + optionrom_header_t *oprom = (optionrom_header_t *) + pci_rom_probe(dev_find_slot(0, PCI_DEVFN(0x2, 0))); + if (oprom) { + printk(BIOS_DEBUG, "GMA: VBIOS found at %p\n", oprom); + vbt = (optionrom_vbt_t *)(oprom + oprom->vbt_offset); + if (read32(vbt->hdr_signature) != VBT_SIGNATURE) { + printk(BIOS_DEBUG, + "GMA: Invalid signature in VBT\n"); + vbt = NULL; + } + } else { + printk(BIOS_NOTICE, "GMA: VBIOS not found in CFBS\n"); + } + } + + /* 3rd option - use generated fake VBT */ + if (!vbt) { + /* FIXME: Read from CBMEM or generate using devicetree */ + void *vbios = get_intel_vbios(); + if (!vbios) { + printk(BIOS_NOTICE, + "GMA: VBIOS not found at 0xc0000\n"); + } else { + printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios); + optionrom_header_t *oprom = + (optionrom_header_t *)vbios; + vbt = (optionrom_vbt_t *)(vbios + oprom->vbt_offset); + if (read32(vbt->hdr_signature) != VBT_SIGNATURE) { + printk(BIOS_NOTICE, + "GMA: Invalid signature in VBT\n"); + vbt = NULL; + } + } + } + + if (!vbt) { + printk(BIOS_ERR, "GMA: VBT not found\n"); + return CB_ERR; + } + + memset(opregion, 0, sizeof(igd_opregion_t)); memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, - sizeof(opregion->header.signature)); + sizeof(opregion->header.signature)); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, + ARRAY_SIZE(vbt->coreblock_biosbuild)); + /* Extended VBT support */ + if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) { + ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size); - /* 8kb */ - opregion->header.size = sizeof(igd_opregion_t) / 1024; - opregion->header.version = IGD_OPREGION_VERSION; + if (ext_vbt == NULL) { + printk(BIOS_ERR, + "GMA: Unable to add Ext VBT to cbmem!\n"); + if (need_unmap) + rdev_munmap(&vbt_rdev, vbt); + return CB_ERR; + } + + memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); + opregion->mailbox3.rvda = (uintptr_t)ext_vbt; + opregion->mailbox3.rvds = vbt->hdr_vbt_size; + } else { + /* Raw VBT size which can fit in gvd1 */ + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size); + } + + if (need_unmap) + rdev_munmap(&vbt_rdev, vbt); + + /* 8KiB */ + opregion->header.size = sizeof(igd_opregion_t) / KiB; + opregion->header.version = (IGD_OPREGION_VERSION << 24); // FIXME We just assume we're mobile for now opregion->header.mailboxes = MAILBOXES_MOBILE; @@ -157,10 +228,6 @@ opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; - - ret = init_opregion_vbt(opregion); - if (ret != CB_SUCCESS) - return ret; /* Write ASLS PCI register and prepare SWSCI register. */ intel_gma_opregion_register((uintptr_t)opregion); -- To view, visit https://review.coreboot.org/20969 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970 Gerrit-Change-Number: 20969 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: Experimental T61 support. Board boots to console over dock. No RAM yet.
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/8482 ) Change subject: Experimental T61 support. Board boots to console over dock. No RAM yet. ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58466/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/13868/ : SUCCESS -- To view, visit https://review.coreboot.org/8482 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idbc058207a6a2efc9e1baaef8564664e6c8063e2 Gerrit-Change-Number: 8482 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Francis Rowe <info(a)gluglug.org.uk> Gerrit-Reviewer: Peter Stuge <peter(a)stuge.se> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 08:36:17 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017