coreboot-gerrit August 2017

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Change in coreboot[master]: Experimental T61 support. Board boots to console over dock. No RAM yet.
by Damien Zammit (Code Review) 12 Aug '17

12 Aug '17

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/8482 Change subject: Experimental T61 support. Board boots to console over dock. No RAM yet. ...................................................................... Experimental T61 support. Board boots to console over dock. No RAM yet. Change-Id: Idbc058207a6a2efc9e1baaef8564664e6c8063e2 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/cpu/intel/speedstep/Makefile.inc M src/cpu/x86/smm/smmrelocate.S M src/mainboard/lenovo/Kconfig A src/mainboard/lenovo/t61/Kconfig A src/mainboard/lenovo/t61/Makefile.inc A src/mainboard/lenovo/t61/acpi_tables.c A src/mainboard/lenovo/t61/devicetree.cb A src/mainboard/lenovo/t61/dock.c A src/mainboard/lenovo/t61/dock.h A src/mainboard/lenovo/t61/romstage.c M src/northbridge/intel/Kconfig M src/northbridge/intel/Makefile.inc A src/northbridge/intel/i965/Kconfig A src/northbridge/intel/i965/Makefile.inc A src/northbridge/intel/i965/acpi.c A src/northbridge/intel/i965/acpi/hostbridge.asl A src/northbridge/intel/i965/acpi/i965.asl A src/northbridge/intel/i965/acpi/igd.asl A src/northbridge/intel/i965/acpi/peg.asl A src/northbridge/intel/i965/bootblock.c A src/northbridge/intel/i965/debug.c A src/northbridge/intel/i965/early_init.c A src/northbridge/intel/i965/errata.c A src/northbridge/intel/i965/i965.h A src/northbridge/intel/i965/ram_calc.c A src/northbridge/intel/i965/raminit.c A src/northbridge/intel/i965/raminit.h A src/northbridge/intel/i965/rcven.c A src/northbridge/intel/i965/udelay.c M src/southbridge/intel/Kconfig M src/southbridge/intel/Makefile.inc A src/southbridge/intel/i82801hx/Kconfig A src/southbridge/intel/i82801hx/Makefile.inc A src/southbridge/intel/i82801hx/acpi/audio.asl A src/southbridge/intel/i82801hx/acpi/globalnvs.asl A src/southbridge/intel/i82801hx/acpi/irqlinks.asl A src/southbridge/intel/i82801hx/acpi/lpc.asl A src/southbridge/intel/i82801hx/acpi/pata.asl A src/southbridge/intel/i82801hx/acpi/pci.asl A src/southbridge/intel/i82801hx/acpi/pcie.asl A src/southbridge/intel/i82801hx/acpi/sata.asl A src/southbridge/intel/i82801hx/acpi/sleepstates.asl A src/southbridge/intel/i82801hx/acpi/smbus.asl A src/southbridge/intel/i82801hx/acpi/usb.asl A src/southbridge/intel/i82801hx/azalia.c A src/southbridge/intel/i82801hx/bootblock.c A src/southbridge/intel/i82801hx/chip.h A src/southbridge/intel/i82801hx/early_lpc.c A src/southbridge/intel/i82801hx/early_smbus.c A src/southbridge/intel/i82801hx/i82801hx.c A src/southbridge/intel/i82801hx/i82801hx.h A src/southbridge/intel/i82801hx/ide.c A src/southbridge/intel/i82801hx/lpc.c A src/southbridge/intel/i82801hx/nic.c A src/southbridge/intel/i82801hx/nvs.h A src/southbridge/intel/i82801hx/pci.c A src/southbridge/intel/i82801hx/pcie.c A src/southbridge/intel/i82801hx/reset.c A src/southbridge/intel/i82801hx/sata.c A src/southbridge/intel/i82801hx/smbus.c A src/southbridge/intel/i82801hx/smbus.h A src/southbridge/intel/i82801hx/smi.c A src/southbridge/intel/i82801hx/smihandler.c A src/southbridge/intel/i82801hx/usb.c A src/southbridge/intel/i82801hx/usb_ehci.c A src/southbridge/intel/i82801hx/watchdog.c 66 files changed, 13,212 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/8482/1 -- To view, visit https://review.coreboot.org/8482 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idbc058207a6a2efc9e1baaef8564664e6c8063e2 Gerrit-Change-Number: 8482 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Francis Rowe <info(a)gluglug.org.uk> Gerrit-Reviewer: Peter Stuge <peter(a)stuge.se> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com>

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Change in coreboot[master]: payload/tianocore: Add patch to preserve coreboot table
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20968 ) Change subject: payload/tianocore: Add patch to preserve coreboot table ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58465/ : SUCCESS -- To view, visit https://review.coreboot.org/20968 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92 Gerrit-Change-Number: 20968 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 08:00:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: payload/tianocore: Add patch to preserve coreboot table
by Arthur Heymans (Code Review) 12 Aug '17

12 Aug '17

Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20968 to look at the new patch set (#2). Change subject: payload/tianocore: Add patch to preserve coreboot table ...................................................................... payload/tianocore: Add patch to preserve coreboot table Credit for this patch goes to 'ReddestDream'. The patch is pulled from https://github.com/MattDevo/edk2 TESTED on thinkpad X200. Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch 1 file changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/20968/2 -- To view, visit https://review.coreboot.org/20968 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92 Gerrit-Change-Number: 20968 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payload/tianocore: Add patch to preserve coreboot table
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20968 ) Change subject: payload/tianocore: Add patch to preserve coreboot table ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58464/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13867/ : SUCCESS -- To view, visit https://review.coreboot.org/20968 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92 Gerrit-Change-Number: 20968 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 07:41:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: payload/tianocore: Add patch to preserve coreboot table
by Arthur Heymans (Code Review) 12 Aug '17

12 Aug '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/20968 Change subject: payload/tianocore: Add patch to preserve coreboot table ...................................................................... payload/tianocore: Add patch to preserve coreboot table Credit for this patch goes to 'ReddestDream'. Patches pulled from https://github.com/MattDevo/edk2 TESTED on thinkpad X200. Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch 1 file changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/20968/1 diff --git a/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch new file mode 100644 index 0000000..649c6ee --- /dev/null +++ b/payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch @@ -0,0 +1,52 @@ +From 07742664925f8d055505220258f2589a9c73a80b Mon Sep 17 00:00:00 2001 +From: ReddestDream <reddestdream(a)gmail.com> +Date: Wed, 3 May 2017 00:13:28 -0400 +Subject: [PATCH] CbSupportPei: prevent lower coreboot table from being + overwritten + +Exclude the bottom 4kb from being included in System Memory HoB + +diff --git a/CorebootModulePkg/CbSupportPei/CbSupportPei.c b/CorebootModulePkg/CbSupportPei/CbSupportPei.c +index 262e6b9d7d..da8f060783 100755 +--- a/CorebootModulePkg/CbSupportPei/CbSupportPei.c ++++ b/CorebootModulePkg/CbSupportPei/CbSupportPei.c +@@ -246,23 +246,20 @@ CbPeiEntryPoint ( + UINTN PmGpeEnBase; + CB_MEM_INFO CbMemInfo; + +- // +- // Report lower 640KB of RAM. Attribute EFI_RESOURCE_ATTRIBUTE_TESTED +- // is intentionally omitted to prevent erasing of the coreboot header +- // record before it is processed by CbParseMemoryInfo. +- // + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | ++ EFI_RESOURCE_ATTRIBUTE_TESTED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ), +- (EFI_PHYSICAL_ADDRESS)(0), +- (UINT64)(0xA0000) ++ // Lower 640KB, except for first 4KB where the lower coreboot pointer ("LBIO") resides ++ (EFI_PHYSICAL_ADDRESS)(0 + 0x1000), ++ (UINT64)(0xA0000 - 0x1000) + ); + + +@@ -309,7 +306,7 @@ CbPeiEntryPoint ( + // Set cache on the physical memory + // + MtrrSetMemoryAttribute (BASE_1MB, LowMemorySize - BASE_1MB, CacheWriteBack); +- MtrrSetMemoryAttribute (0, 0xA0000, CacheWriteBack); ++ MtrrSetMemoryAttribute ((0 + 0x1000), (0xA0000 - 0x1000), CacheWriteBack); + + // + // Create Memory Type Information HOB +-- +2.14.0 + -- To view, visit https://review.coreboot.org/20968 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1517607cee8308c5f5443c58c16ce44056611e92 Gerrit-Change-Number: 20968 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/denverton_ns: Add FSP header files for De...
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20805 ) Change subject: vendorcode/intel/fsp/fsp2_0/denverton_ns: Add FSP header files for Denverton_NS SoC ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58461/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13864/ : SUCCESS -- To view, visit https://review.coreboot.org/20805 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9672610df09089c549e74072345781bea0b4d06f Gerrit-Change-Number: 20805 Gerrit-PatchSet: 7 Gerrit-Owner: Mariusz Szafranski Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: FEI WANG <wangfei.jimei(a)gmail.com> Gerrit-Reviewer: Fei Wang Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Mariusz Szafranski Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 01:36:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/denverton_ns: Add support for Denverton_NS SoC
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20861 ) Change subject: soc/intel/denverton_ns: Add support for Denverton_NS SoC ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58462/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13865/ : SUCCESS -- To view, visit https://review.coreboot.org/20861 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1 Gerrit-Change-Number: 20861 Gerrit-PatchSet: 3 Gerrit-Owner: Mariusz Szafranski Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: FEI WANG <wangfei.jimei(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 01:32:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/harcuvar: Add support for Intel Harcuvar CRB
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20862 ) Change subject: mainboard/intel/harcuvar: Add support for Intel Harcuvar CRB ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58460/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13863/ : SUCCESS -- To view, visit https://review.coreboot.org/20862 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a Gerrit-Change-Number: 20862 Gerrit-PatchSet: 3 Gerrit-Owner: Mariusz Szafranski Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: FEI WANG <wangfei.jimei(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 01:19:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Revert CAR teardown wbinvd
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20967 ) Change subject: soc/amd/stoneyridge: Revert CAR teardown wbinvd ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58458/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13862/ : SUCCESS -- To view, visit https://review.coreboot.org/20967 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a Gerrit-Change-Number: 20967 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 23:25:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Add postcar stage
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20966 ) Change subject: soc/amd/stoneyridge: Add postcar stage ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58457/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13861/ : SUCCESS -- To view, visit https://review.coreboot.org/20966 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 Gerrit-Change-Number: 20966 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 23:15:34 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017