coreboot-gerrit August 2017

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Change in coreboot[master]: arch/x86: Make postcar TempRamExit call generic
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20965 ) Change subject: arch/x86: Make postcar TempRamExit call generic ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58459/ : SUCCESS -- To view, visit https://review.coreboot.org/20965 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Gerrit-Change-Number: 20965 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 23:02:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: arch/x86: Make postcar TempRamExit call generic
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20965 ) Change subject: arch/x86: Make postcar TempRamExit call generic ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58456/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/13860/ : SUCCESS -- To view, visit https://review.coreboot.org/20965 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Gerrit-Change-Number: 20965 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 22:48:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: arch/x86: Make postcar TempRamExit call generic
by Marshall Dawson (Code Review) 12 Aug '17

12 Aug '17

Marshall Dawson has uploaded a new patch set (#2). ( https://review.coreboot.org/20965 ) Change subject: arch/x86: Make postcar TempRamExit call generic ...................................................................... arch/x86: Make postcar TempRamExit call generic Move the FSP-specific call for tearing down cache-as-RAM out of postcar.c and replace it with an empty weak function. This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built when CONFIG_FSP_CAR is true. Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar.c M src/drivers/intel/fsp2_0/temp_ram_exit.c 3 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/20965/2 -- To view, visit https://review.coreboot.org/20965 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Gerrit-Change-Number: 20965 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Revert CAR teardown wbinvd
by Marshall Dawson (Code Review) 12 Aug '17

12 Aug '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20967 Change subject: soc/amd/stoneyridge: Revert CAR teardown wbinvd ...................................................................... soc/amd/stoneyridge: Revert CAR teardown wbinvd Change the cache-as-ram teardown to use invd instead of wbinvd. CAR teardown had been modified to use wbinvd to send CAR contents to DRAM backing prior to teardown. This allowed CAR variables, stack, and local variables to be preserved while running the AMD_DISABLE_STACK macro. Using the wbinvd instruction has the side effect of sending all dirty cache contents to DRAM and not only our CAR data. This would likely cause corruption, e.g. during S3 resume. Stoney Ridge now uses a postcar stage and this is no longer a requirement. Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc 1 file changed, 2 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/20967/1 diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc index 92fd7e2..c744e47 100644 --- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc @@ -401,16 +401,6 @@ * Return any family specific controls to their 'standard' * settings for using cache with main memory. * -* Note: Customized for coreboot: -* A wbinvd is used to send cache to memory. The existing stack is preserved -* at its original location and additional information is preserved (e.g. -* coreboot CAR globals, heap structures, etc.). This implementation should -* NOT be used with S3 resume IF the stack/cache area is not reserved and -* over system memory. -* -* This CPU resume path doesn't use CAR, but be careful if porting to -* other CPUs. -* * Inputs: * ESI - [31:24] flags; [15,8]= Node#; [7,0]= core# * Outputs: @@ -644,12 +634,7 @@ # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved. #-------------------------------------------------------------------------- - #-------------------------------------------------------------------------- - # Send cache to memory. Preserve stack and coreboot CAR globals. - # This shouldn't be used with S3 resume IF the stack/cache area is - # not reserved and over system memory. - #-------------------------------------------------------------------------- - wbinvd + invd # #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM? # cmp $01, %bh @@ -1289,17 +1274,7 @@ .endm /***************************************************************************** -* AMD_DISABLE_STACK: Implementation is modified for coreboot from -* the original AMD intent. A WBINVD is used in the HOOK -* to send dirty cache contents to DRAM backing before -* disabling cache-as-ram. This is not safe for S3 resume. -* -* todo: -* * rework PI/AGESA source to set DRAM to UC to send -* writes directly to memory -* * move DCACHE_BASE or use postcar stage for teardown -* to eliminate car_migrated problem that will occur -* after wbinvd is changed back to invd +* AMD_DISABLE_STACK: * * In: * none -- To view, visit https://review.coreboot.org/20967 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a Gerrit-Change-Number: 20967 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Add postcar stage
by Marshall Dawson (Code Review) 12 Aug '17

12 Aug '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20966 Change subject: soc/amd/stoneyridge: Add postcar stage ...................................................................... soc/amd/stoneyridge: Add postcar stage Insert a postcar stage for Stoney Ridge and move romstage's CAR teardown there. The AMD cache-as-ram teardown procedure currently uses a wbinvd instruction to send CAR contents to DRAM backing. This allows preserving stack contents and CAR globals after the teardown happens, but likely results in memory corruption during S3 resume. Due to the current base of the DCACHE region, reverting to an invd instruction will break the detection mechanism for CAR migrated variables. Using postcar avoids this problem. The current behavior of AGESA is to set up all cores' MTRRs during the AmdInitPost() entry point. This implementation preloads the postcar frame with those settings to avoid them being erased by the postcar _start. The change also moves AmdInitEnv(), which needs to follow CAR teardown, from romstage to the earliest opportunity in ramstage. Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/cpu/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/romstage.c M src/vendorcode/amd/pi/Makefile.inc 7 files changed, 49 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/20966/1 diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index 8e6972e..ecc9afb 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1,2 +1,3 @@ bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 0425beb..4a7f6c7 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -49,6 +49,10 @@ select SOC_AMD_COMMON_BLOCK_CAR select C_ENVIRONMENT_BOOTBLOCK select BOOTBLOCK_CONSOLE + select RELOCATABLE_MODULES + select RELOCATABLE_RAMSTAGE + select POSTCAR_STAGE + select POSTCAR_CONSOLE config VBOOT select AMDFW_OUTSIDE_CBFS diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 30006b3..8c435e6 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -60,6 +60,9 @@ verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c +postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c +postcar-y += ramtop.c + ramstage-y += chip.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 2af466b..b586af1 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -14,10 +14,13 @@ */ #include <chip.h> +#include <bootstate.h> #include <cpu/amd/mtrr.h> #include <cpu/cpu.h> #include <device/device.h> #include <device/pci.h> +#include <agesawrapper.h> +#include <agesawrapper_call.h> #include <soc/hudson.h> #include <soc/northbridge.h> @@ -78,3 +81,11 @@ .init = &soc_init, .final = &soc_final }; + +static void do_initenv(void *unused) +{ + post_code(0x46); + AGESAWRAPPER(amdinitenv); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, do_initenv, NULL); diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index e082a9d..1509850 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -27,7 +27,4 @@ void fam15_finalize(void *chip_info); void setup_uma_memory(void); -/* todo: remove this when postcar stage is in place */ -asmlinkage void chipset_teardown_car(void); - #endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 1380fb7..c3154c1 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> #include <program_loading.h> @@ -24,6 +27,9 @@ asmlinkage void car_stage_entry(void) { + struct postcar_frame pcf; + int i; + console_init(); post_code(0x40); @@ -35,18 +41,30 @@ post_code(0x42); cbmem_initialize_empty(); - /* - * This writes contents to DRAM backing before teardown. - * todo: move CAR teardown to postcar implementation and - * relocate amdinitenv to ramstage. - */ - chipset_teardown_car(); - post_code(0x43); - AGESAWRAPPER(amdinitenv); + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); - post_code(0x50); - run_ramstage(); + post_code(0x44); + /* AGESA has already set up MTRRs. Put into frame to preserve them. */ + for (i = 0 ; i < 7 ; i++) { + msr_t base = rdmsr(MTRR_PHYS_BASE(i)); + msr_t mask = rdmsr(MTRR_PHYS_MASK(i)); + if (!(mask.lo & MTRR_PHYS_MASK_VALID)) + continue; - post_code(0x54); /* Should never see this post code. */ + /* + * Note: Only ranges below 4GB are programmed to MTRRs by + * AGESA so the base.hi may be assumed = 0. The DRAM region + * above 4GB is automatically handled by setting the + * Tom2ForceMemTypeWB bit in in SYS_CFG. + */ + postcar_frame_add_mtrr(&pcf, base.lo & ~0xfff, + ~(mask.lo & ~0xfff) + 1, base.lo & 0x7); + } + + post_code(0x45); + run_postcar_phase(&pcf); + + post_code(0x50); /* Should never see this post code. */ } diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index bcf078d..b1f658f 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -85,6 +85,7 @@ CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_postcar := $(CC_postcar) $(AGESA_INC) $(AGESA_CFLAGS) CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_64 := $(CC_x86_64) $(AGESA_INC) $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/20966 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 Gerrit-Change-Number: 20966 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: arch/x86: make postcar TempRamExit call generic
by Marshall Dawson (Code Review) 12 Aug '17

12 Aug '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20965 Change subject: arch/x86: make postcar TempRamExit call generic ...................................................................... arch/x86: make postcar TempRamExit call generic Move the FSP-specific call for tearing down cache-as-RAM out of postcar.c and replace it with an empty weak function. This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built when CONFIG_FSP_CAR is true. Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar.c M src/drivers/intel/fsp2_0/temp_ram_exit.c 3 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/20965/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 8a44ef9..a379d20 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -297,6 +297,13 @@ * utilizes prog_run() internally. */ void run_postcar_phase(struct postcar_frame *pcf); + +/* + * Generic call from postcar for relying on FSP or binayPI to + * perform the cache-as-ram teardown. + */ +void run_blob_temp_ram_exit(void); + #endif #endif /* ARCH_CPU_H */ diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index 34a4335..099650a 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -13,18 +13,18 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> #include <cbmem.h> #include <console/console.h> #include <main_decl.h> #include <program_loading.h> #include <soc/intel/common/util.h> -#include <fsp/util.h> + +__attribute__((weak)) void run_blob_temp_ram_exit(void) { /* do nothing */ } void main(void) { - /* Call TempRamExit FSP API if enabled. */ - if (IS_ENABLED(CONFIG_FSP_CAR)) - fsp_temp_ram_exit(); + run_blob_temp_ram_exit(); console_init(); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 21eb367..fe33b74 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -47,3 +47,8 @@ die("TempRamExit returned an error!\n"); } } + +void run_blob_temp_ram_exit(void) +{ + fsp_temp_ram_exit(); +} -- To view, visit https://review.coreboot.org/20965 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479 Gerrit-Change-Number: 20965 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/intel/common/block: Fix PMC common block dependency
by build bot (Jenkins) (Code Review) 11 Aug '17

11 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20964 ) Change subject: soc/intel/common/block: Fix PMC common block dependency ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58455/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13859/ : SUCCESS -- To view, visit https://review.coreboot.org/20964 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I88077626aff3efba0a95b3aaee0dbd71344ccb42 Gerrit-Change-Number: 20964 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 11 Aug 2017 20:35:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Fix PMC common block dependency
by Shaunak Saha (Code Review) 11 Aug '17

11 Aug '17

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/20964 Change subject: soc/intel/common/block: Fix PMC common block dependency ...................................................................... soc/intel/common/block: Fix PMC common block dependency This patch fix the dependency for PMC common block code. PMC block use SLP_TYP macros and acpi_sleep_from_pm1 function which is defined in arch/acpi.h and guarded by CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES. So we need PMC common block to depend on that config for proper inclusion. Change-Id: I88077626aff3efba0a95b3aaee0dbd71344ccb42 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/soc/intel/common/block/pmc/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/20964/1 diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 4e10f93..c00e14c 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -1,5 +1,6 @@ config SOC_INTEL_COMMON_BLOCK_PMC depends on SOC_INTEL_COMMON_BLOCK_GPIO + depends on ACPI_INTEL_HARDWARE_SLEEP_VALUES bool help Intel Processor common code for Power Management controller(PMC) -- To view, visit https://review.coreboot.org/20964 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I88077626aff3efba0a95b3aaee0dbd71344ccb42 Gerrit-Change-Number: 20964 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com>

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Change in coreboot[master]: ec/google: update ec_commands.h
by Martin Roth (Code Review) 11 Aug '17

11 Aug '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/20945 ) Change subject: ec/google: update ec_commands.h ...................................................................... ec/google: update ec_commands.h Copy from chrome-ec codebase, except for keeping the long-form license header. BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: I513123547f3854945e827d2f7f6c0df6591886eb Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: https://review.coreboot.org/20945 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/chromeec/ec_commands.h 1 file changed, 31 insertions(+), 2 deletions(-) Approvals: Martin Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 3e093f6..46ab905 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -31,7 +31,7 @@ #ifndef __CROS_EC_EC_COMMANDS_H #define __CROS_EC_EC_COMMANDS_H -#ifndef __ACPI__ +#if !defined(__ACPI__) && !defined(__KERNEL__) #include <stdint.h> #endif @@ -1121,6 +1121,14 @@ }; /*****************************************************************************/ +/* Get the board's SKU ID from EC */ +#define EC_CMD_GET_SKU_ID 0x000E + +struct __ec_align4 ec_response_sku_id { + uint32_t sku_id; +}; + +/*****************************************************************************/ /* Flash commands */ /* Get flash info */ @@ -1151,6 +1159,13 @@ /* Flags for version 1+ flash info command */ /* EC flash erases bits to 0 instead of 1 */ #define EC_FLASH_INFO_ERASE_TO_0 (1 << 0) + +/* Flash must be selected for read/write/erase operations to succeed. This may + * be necessary on a chip where write/erase can be corrupted by other board + * activity, or where the chip needs to enable some sort of programming voltage, + * or where the read/write/erase operations require cleanly suspending other + * chip functionality. */ +#define EC_FLASH_INFO_SELECT_REQUIRED (1 << 1) /* * Version 1 returns the same initial fields as version 0, with additional @@ -1421,6 +1436,16 @@ /* Status registers from command 0x05 and 0x35 */ uint8_t sr1, sr2; }; + + +/* Select flash during flash operations */ +#define EC_CMD_FLASH_SELECT 0x0019 + +struct __ec_align4 ec_params_flash_select { + /* 1 to select flash, 0 to deselect flash */ + uint8_t select; +}; + /*****************************************************************************/ /* PWM commands */ @@ -2980,6 +3005,7 @@ #define EC_MKBP_POWER_BUTTON 0 #define EC_MKBP_VOL_UP 1 #define EC_MKBP_VOL_DOWN 2 +#define EC_MKBP_RECOVERY 3 /* Switches */ #define EC_MKBP_LID_OPEN 0 @@ -3935,6 +3961,9 @@ #define EC_CMD_USB_PD_PORTS 0x0102 +/* Maximum number of PD ports on a device, num_ports will be <= this */ +#define EC_USB_PD_MAX_PORTS 8 + struct __ec_align1 ec_response_usb_pd_ports { uint8_t num_ports; }; @@ -4425,6 +4454,6 @@ #define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1 #define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE -#endif /* !__ACPI__ */ +#endif /* !__ACPI__ && !__KERNEL__ */ #endif /* __CROS_EC_EC_COMMANDS_H */ -- To view, visit https://review.coreboot.org/20945 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I513123547f3854945e827d2f7f6c0df6591886eb Gerrit-Change-Number: 20945 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 11 Aug '17

11 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 48: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58452/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13858/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-Change-Number: 18305 Gerrit-PatchSet: 48 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Fri, 11 Aug 2017 18:50:27 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017