coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

1 participants
1999 discussions

Change in coreboot[master]: amd/pi/hudson: Expand 48MHz for both osc signals
by Marshall Dawson (Code Review) 16 Aug '17

16 Aug '17

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/21034 ) Change subject: amd/pi/hudson: Expand 48MHz for both osc signals ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/21034/1/src/southbridge/amd/pi/hudson/early… File src/southbridge/amd/pi/hudson/early_setup.c: https://review.coreboot.org/#/c/21034/1/src/southbridge/amd/pi/hudson/early… PS1, Line 273: (u32) remove https://review.coreboot.org/#/c/21034/1/src/southbridge/amd/pi/hudson/early… PS1, Line 276: (u32) remove -- To view, visit https://review.coreboot.org/21034 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaee093d05fa712f62052a3787e56c5eaf4045483 Gerrit-Change-Number: 21034 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 16 Aug 2017 14:40:56 +0000 Gerrit-HasComments: Yes

1 0

Change in coreboot[master]: amd/padmelon: Fixes to enable power button
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

John E. Kabat has uploaded this change for review. ( https://review.coreboot.org/21048 Change subject: amd/padmelon: Fixes to enable power button ...................................................................... amd/padmelon: Fixes to enable power button More fixes to enable the power button, remove uneeded code and general cleanup In gpe.asl clear the PSIN_FLAG in the sio. In dsdt.asl use the superio.asl file in the f81803a directory. The remainder is general cleanup due to changes in amd code. Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b --- M src/mainboard/amd/padmelon/BiosCallOuts.c M src/mainboard/amd/padmelon/Kconfig M src/mainboard/amd/padmelon/OemCustomize.c M src/mainboard/amd/padmelon/acpi/gpe.asl M src/mainboard/amd/padmelon/devicetree.cb M src/mainboard/amd/padmelon/dsdt.asl M src/mainboard/amd/padmelon/romstage.c 7 files changed, 31 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/21048/1 diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c index 91c5efe..1c19912 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -15,29 +15,23 @@ #include <device/pci_def.h> #include <device/device.h> -#include "AGESA.h" -#include "amdlib.h" -#include <northbridge/amd/pi/BiosCallOuts.h> +#include <AGESA.h> +#include <amdlib.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> #include <northbridge/amd/pi/00660F01/chip.h> -#include "Ids.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "cbfs.h" -#include "imc.h" -#include "hudson.h" +#include <Ids.h> +#include <heapManager.h> +#include <FchPlatform.h> +#include <cbfs.h> +#include <imc.h> +#include <hudson.h> #include <stdlib.h> -#include "BiosCallOuts.h" #include "northbridge/amd/pi/dimmSpd.h" #include "northbridge/amd/pi/agesawrapper.h" -#include <boardid.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); -const BIOS_CALLOUT_STRUCT BiosCallouts[] = -{ - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_READ_SPD, agesa_ReadSpd }, {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, @@ -70,6 +64,7 @@ FchParams_reset->FchReset.SataEnable = hudson_sata_enable(); FchParams_reset->FchReset.IdeEnable = hudson_ide_enable(); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_padmelon_gpio; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; @@ -82,8 +77,8 @@ FchParams_env->Usb.Xhci0Enable = TRUE; else FchParams_env->Usb.Xhci0Enable = FALSE; + FchParams_env->Usb.Xhci1Enable = FALSE; FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ - /* SD configuration */ FchParams_env->Sd.SdSlotType = 1; /* eMMC */ } diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 7f75dc4..b518149 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y + select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c index 9ed7e42..2516fde 100644 --- a/src/mainboard/amd/padmelon/OemCustomize.c +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <PlatformMemoryConfiguration.h> -#include <boardid.h> +#include <vendorcode/amd/pi/00660F01/AGESA.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl index ba8d878..095d3c1 100644 --- a/src/mainboard/amd/padmelon/acpi/gpe.asl +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -17,11 +17,11 @@ /* General event 3 */ Method(_L03) { - /* DBGO("\\_GPE\\_L03\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + /* DBGO("\\_GPE\\_L03\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* Legacy PM event - Power Button */ + /* Legacy PM event - Power Button */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ \_SB.SIO0.CPSI() /* clear psin state in sio */ @@ -77,4 +77,4 @@ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } -} /* End Scope GPE */ +} /* End Scope GPE */ diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb index f47cc70..82b57b3 100644 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -25,7 +25,7 @@ chip northbridge/amd/pi/00660F01 # PCI side of HT root complex device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9874 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge device pci 2.1 off end # No x4 PCIe slot @@ -54,6 +54,7 @@ end # SM device pci 14.3 on # LPC 0x439d chip superio/fintek/f81803a + register "conf_key_mode" = "0x77" device pnp 4e.1 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 @@ -67,7 +68,6 @@ device pnp 4e.6 off end # GPIO device pnp 4e.7 off end # WDT device pnp 4e.a on end # PME - end # f81803a end # LPC device pci 14.7 on end # SD diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 470ee26..76adaa4 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -72,8 +72,8 @@ /* Describe the devices in the Southbridge */ #include "acpi/carrizo_fch.asl" - /* Describe the Fintek F81803A SIO */ - #include "acpi/superio.asl" + /* Describe the Fintek F81803A SIO */ + #include <superio/fintek/f81803a/acpi/superio.asl> } /* End \_SB scope */ diff --git a/src/mainboard/amd/padmelon/romstage.c b/src/mainboard/amd/padmelon/romstage.c index 7f29002..f53d66f 100644 --- a/src/mainboard/amd/padmelon/romstage.c +++ b/src/mainboard/amd/padmelon/romstage.c @@ -20,6 +20,7 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> +#include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -32,9 +33,6 @@ { u32 val; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { @@ -42,6 +40,9 @@ hudson_clk_output_48Mhz(2); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +#if IS_ENABLED(CONFIG_HUDSON_UART) + configure_hudson_uart(); +#endif post_code(0x31); console_init(); } @@ -65,18 +66,16 @@ post_code(0x40); AGESAWRAPPER(amdinitpost); +} + +void agesa_postcar(struct sysinfo *cb) +{ post_code(0x41); AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); if (acpi_is_wakeup_s4()) { outb(0xEE, PM_INDEX); outb(0x8, PM_DATA); } - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ } -- To view, visit https://review.coreboot.org/21048 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b Gerrit-Change-Number: 21048 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com>

1 0

Change in coreboot[master]: amd/padmelon: Adding more Fintek F81803A files
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

Hello John E. Kabat Jr., I'd like you to do a code review. Please visit https://review.coreboot.org/21047 to review the following change. Change subject: amd/padmelon: Adding more Fintek F81803A files ...................................................................... amd/padmelon: Adding more Fintek F81803A files This reorganizes the Fintek F81803A files and adds new features. superio.asl add access to PME ACPI Control Register 5 for clearing the PSIN_FLAG. Method CPSI() is used by asl power button code to clear this. f81803a.h consolidates all the bit and register definition in one place. superio.c consolidates all the initialization functions. Superio.asl moved to the acpi directory. chip.h fintek_internal.h and f81803a_pme.c have been folded into other files and are no longer needed Change-Id: Ib4b078a590ba27f698dad84d6bd6237c8331e60f Signed-off-by: John Kabat <john.kabat(a)scarletltd.com> --- M src/superio/fintek/f81803a/Makefile.inc A src/superio/fintek/f81803a/acpi/superio.asl D src/superio/fintek/f81803a/chip.h M src/superio/fintek/f81803a/f81803a.h D src/superio/fintek/f81803a/f81803a_pme.c D src/superio/fintek/f81803a/fintek_internal.h M src/superio/fintek/f81803a/superio.c 7 files changed, 217 insertions(+), 239 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21047/1 diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc index 372de05..9156bf9 100644 --- a/src/superio/fintek/f81803a/Makefile.inc +++ b/src/superio/fintek/f81803a/Makefile.inc @@ -15,4 +15,3 @@ ## ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c -ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += f81803a_pme.c diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl new file mode 100644 index 0000000..7568131 --- /dev/null +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the F81803A SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x1 UARTA Implemented, partially tested + * 0x2 UARTB UART only, partially tested + * 0x4 HWM Not implemented + * 0x5 KBC Implemented, untested + * 0x6 GPIO6 Not implemented + * 0x7 WDT0&PLED Not implemented + * 0xa ACPI/PME/ERP Partially implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * F81803A_SHOW_UARTA If defined, UARTA will be exposed. + * F81803A_SHOW_UARTB If defined, UARTB will be exposed. + * F81803A_SHOW_KBC If defined, the KBC will be exposed. + * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. + * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. + */ +#undef SUPERIO_DEV +#define SUPERIO_DEV SIO0 +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME F81803A +#define SUPERIO_PNP_BASE 0x4E +#define F81803A_SHOW_PME +#include <superio/acpi/pnp.asl> + + + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F81803A Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + offset(0xFB), + APC5, 8, /* PME ACPI Control Register 5 */ + } + + Method(_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef F81803A_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #define SUPERIO_UART_PM_REG UAPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #define SUPERIO_UART_PM_REG UBPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_PME + #undef SUPERIO_PME_LDN + #define SUPERIO_PME_LDN 0x0A + + OperationRegion(APCx, SystemIO, APC5, 0x01) + Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ + { + Offset(0x00), /*Control Reg 5 */ + , 7, + PSIN, 1 /* PSIN_FLAG */ + } + + /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ + Method(CPSI, 0, Serialized) + { + /* DBG0("SIO CPSI")*/ + ENTER_CONFIG_MODE(SUPERIO_PME_LDN) + Store(1, PSIN) + EXIT_CONFIG_MODE() + } +#endif + +} diff --git a/src/superio/fintek/f81803a/chip.h b/src/superio/fintek/f81803a/chip.h deleted file mode 100644 index 063f746..0000000 --- a/src/superio/fintek/f81803a/chip.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_FINTEK_F81803A_CHIP_H -#define SUPERIO_FINTEK_F81803A_CHIP_H - -#include <stdint.h> - -/* register in Fintek F81803A */ -#define LDN_REG 0x07 - -/* Global Control Registers */ -#define CLOCK_SELECT_REG 0x26 -#define FUNC_PROG_SELECT (1<<3) -#define CONFIG_PORT_SELECT_REG 0x27 - -#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */ -#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */ -#define MULTI_FUNC_SEL_REG1 0x29 -#define MULTI_FUNC_SEL_REG2 0x2A -#define MULTI_FUNC_SEL_REG3 0x2B -#define MULTI_FUNC_SEL_REG4 0x2C -#define WAKEUP_CONTROL_REG 0x2d - -/* LUN A - PMZE, ACPI, ERP */ -#define PME_DEVICE_ENABLE_REG 0x30 -#define PME_ENABLE (1<<0) -#define PME_ERP_ENABLE_REG 0xE0 -#define ERP_ENABLE (1<<7) -#define ERP_PME_EN (1<<1) -#define ERP_PSOUT_EN (1<<0) -#define PME_ERP_CONTROL_1_REG 0xE1 -#define PME_ERP_CONTROL_2_REG 0xE2 -#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3 -#define PME_ERP_WAKEUP_ENABLE_REG 0xE8 -#define PME_ERP_MODE_SELECT_REG 0xEC -#define PME_EVENT_ENABLE_1_REG 0xF0 -#define PME_EVENT_STATUS_1_REG 0xF1 -#define PME_EVENT_ENABLE_2_REG 0xF2 -#define PME_EVENT_STATUS_2_REG 0xF3 -#define PME_ACPI_CONTROL_1_REG 0xF4 -#define PME_ACPI_CONTROL_2_REG 0xF5 -#define PME_ACPI_CONTROL_3_REG 0xF6 -#define PME_ACPI_CONTROL_4_REG 0xF7 -#define PME_ACPI_CONTROL_5_REG 0xFB -#define PME_ACPI_CONTROL_6_REG 0xFC - - -#endif /* SUPERIO_FINTEK_F81803A_CHIP_H */ diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h index 9e2055c..a955d46 100644 --- a/src/superio/fintek/f81803a/f81803a.h +++ b/src/superio/fintek/f81803a/f81803a.h @@ -22,15 +22,53 @@ #ifndef SUPERIO_FINTEK_F81803_H #define SUPERIO_FINTEK_F81803_H -/* Logical Device Numbers (LDN). */ -#define F81803A_SP1 0x01 /* UART1 */ -#define F81803A_SP2 0x02 /* UART2 */ -#define F81803A_HWM 0x04 /* Hardware Monitor */ -#define F81803A_KBC 0x05 /* Keyboard/Mouse */ +/* Logical Device Numbers (LDN) */ +#define F81803A_SP1 0x01 /* UART1 */ +#define F81803A_SP2 0x02 /* UART2 */ +#define F81803A_HWM 0x04 /* Hardware Monitor */ +#define F81803A_KBC 0x05 /* Keyboard/Mouse */ #define F81803A_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F81803A_WDT 0x07 /* Watch Dog Timer */ -#define F81803A_PME 0x0a /* Power Management Events (PME) */ +#define F81803A_WDT 0x07 /* Watch Dog Timer */ +#define F81803A_PME 0x0a /* Power Management Events (PME) */ + +/* registers in Fintek F81803A */ +#define LDN_REG 0x07 + +/* Global Control Registers */ +#define CLOCK_SELECT_REG 0x26 +#define FUNC_PROG_SELECT (1<<3) +#define CONFIG_PORT_SELECT_REG 0x27 + +#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */ +#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */ +#define MULTI_FUNC_SEL_REG1 0x29 +#define MULTI_FUNC_SEL_REG2 0x2A +#define MULTI_FUNC_SEL_REG3 0x2B +#define MULTI_FUNC_SEL_REG 0x2C +#define WAKEUP_CONTROL_REG 0x2d + +/* LUN A - PME, ACPI, ERP */ +#define PME_DEVICE_ENABLE_REG 0x30 +#define PME_ENABLE (1<<0) +#define PME_ERP_ENABLE_REG 0xE0 +#define ERP_ENABLE (1<<7) +#define ERP_PME_EN (1<<1) +#define ERP_PSOUT_EN (1<<0) +#define PME_ERP_CONTROL_1_REG 0xE1 +#define PME_ERP_CONTROL_2_REG 0xE2 +#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3 +#define PME_ERP_WAKEUP_ENABLE_REG 0xE8 +#define PME_ERP_MODE_SELECT_REG 0xEC +#define PME_EVENT_ENABLE_1_REG 0xF0 +#define PME_EVENT_STATUS_1_REG 0xF1 +#define PME_EVENT_ENABLE_2_REG 0xF2 +#define PME_EVENT_STATUS_2_REG 0xF3 +#define PME_ACPI_CONTROL_1_REG 0xF4 +#define PME_ACPI_CONTROL_2_REG 0xF5 +#define PME_ACPI_CONTROL_3_REG 0xF6 +#define PME_ACPI_CONTROL_4_REG 0xF7 +#define PME_ACPI_CONTROL_5_REG 0xFB +#define PME_ACPI_CONTROL_6_REG 0xFC #endif /* SUPERIO_FINTEK_F81803_H */ -#include "fintek_internal.h" diff --git a/src/superio/fintek/f81803a/f81803a_pme.c b/src/superio/fintek/f81803a/f81803a_pme.c deleted file mode 100644 index 2223212..0000000 --- a/src/superio/fintek/f81803a/f81803a_pme.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pnp.h> -#include "f81803a.h" - - - -void f81803a_pme_init(struct device *dev) -{ - - printk(BIOS_INFO, "F81803A PME: Init.\n"); - - pnp_enter_conf_mode(dev); - pnp_write_config(dev, LDN_REG, F81803A_PME); - - /* enable ERP function*/ - /* also set PSIN to generate PSOUT*/ - pnp_write_config(dev, PME_ERP_ENABLE_REG,ERP_ENABLE | ERP_PSOUT_EN); - - pnp_exit_conf_mode(dev); -} diff --git a/src/superio/fintek/f81803a/fintek_internal.h b/src/superio/fintek/f81803a/fintek_internal.h deleted file mode 100644 index 5b8d275..0000000 --- a/src/superio/fintek/f81803a/fintek_internal.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef SUPERIO_FINTEK_F81803A_INTERNAL_H -#define SUPERIO_FINTEK_F81803A_INTERNAL_H - -#include <arch/io.h> -#include <device/pnp.h> -#include "chip.h" - -struct f81803a_reg_tab -{ - const char *reg_name; - uint8_t reg; -}; -void f81803a_pme_init(struct device *dev); -void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab); -#endif /* SUPERIO_FINTEK_F81803A_INTERNAL_H */ diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c index 3f5636a..3ebca87 100644 --- a/src/superio/fintek/f81803a/superio.c +++ b/src/superio/fintek/f81803a/superio.c @@ -23,118 +23,39 @@ #include <pc80/keyboard.h> #include "f81803a.h" -#ifdef F81803A_REGDUMP -/* for Debug */ -static struct f81803a_reg_tab f81803a_pme_regs1[] = { - - { "CLOCK_SELECT_REG", CLOCK_SELECT_REG }, - { "CONFIG_PORT_SELECT_REG", CONFIG_PORT_SELECT_REG }, - { "TSI_PIN_SELECT_REG", TSI_PIN_SELECT_REG }, - { NULL, 0 } -}; - - -static struct f81803a_reg_tab f81803a_pme_regs2[] = { - { "TSI_LEVEL_SELECT_REG", TSI_LEVEL_SELECT_REG }, - { "MULTI_FUNC_SEL_REG1", MULTI_FUNC_SEL_REG1 }, - { "MULTI_FUNC_SEL_REG2", MULTI_FUNC_SEL_REG2 }, - { "MULTI_FUNC_SEL_REG3", MULTI_FUNC_SEL_REG3 }, - { "MULTI_FUNC_SEL_REG4", MULTI_FUNC_SEL_REG4 }, - { "WAKEUP_CONTROL_REG", WAKEUP_CONTROL_REG }, - { "PME_DEVICE_ENABLE_REG", PME_DEVICE_ENABLE_REG }, - { "PME_ERP_ENABLE_REG", PME_ERP_ENABLE_REG }, - { "PME_ERP_CONTROL_1_REG", PME_ERP_CONTROL_1_REG }, - { "PME_ERP_CONTROL_2_REG", PME_ERP_CONTROL_2_REG }, - { "PME_ERP_PSIN_DEBOUNCE_REG", PME_ERP_PSIN_DEBOUNCE_REG }, - { "PME_ERP_WAKEUP_ENABLE_REG", PME_ERP_WAKEUP_ENABLE_REG }, - { "PME_EVENT_ENABLE_1_REG", PME_EVENT_ENABLE_1_REG }, - { "PME_EVENT_ENABLE_2_REG", PME_EVENT_ENABLE_2_REG }, - { "PME_ACPI_CONTROL_1_REG", PME_ACPI_CONTROL_1_REG }, - { "PME_ACPI_CONTROL_2_REG", PME_ACPI_CONTROL_2_REG }, - { "PME_ACPI_CONTROL_3_REG", PME_ACPI_CONTROL_3_REG }, - { "PME_ACPI_CONTROL_4_REG", PME_ACPI_CONTROL_4_REG }, - { "PME_ACPI_CONTROL_5_REG", PME_ACPI_CONTROL_5_REG }, - { "PME_ACPI_CONTROL_6_REG", PME_ACPI_CONTROL_6_REG }, - { NULL, 0 } -}; - -void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab) +static void f81803a_pme_init(struct device *dev) { - uint8_t val; - for (; tab->reg_name; tab++) - { - val = pnp_read_config(dev, tab->reg); - printk(BIOS_INFO, " %02X %s %02X\n", tab->reg, tab->reg_name, val & 0xff); - } - + pnp_enter_conf_mode(dev); + pnp_write_config(dev, LDN_REG, F81803A_PME); + /* enable ERP function*/ + /* also set PSIN to generate PSOUT*/ + pnp_write_config(dev, PME_ERP_ENABLE_REG, ERP_ENABLE | ERP_PSOUT_EN); + pnp_exit_conf_mode(dev); } -static void f81803a_pme_reg_dump(struct device *dev, const char *s) -{ - uint8_t save_clock_select; - printk(BIOS_INFO, "\nF81803A PME: Regs %s\n", s); - pnp_enter_conf_mode(dev); - pnp_write_config(dev, LDN_REG, F81803A_PME); - /* - * this is done with two tables as FUNC_PROG_SEL in CLOCK_SELECT_REG - * is used as a bank select register for the TSI registers index 28 - * We assume that FUNC_PROG_SELECT is 0 for now - * - * Note the actual writeup for FUNC_PROG_SEL on page 52 say: - * "Index 0x29, 0x2B and 0x2C bank select register" - * However this is not the case and only reg 28 appears to be affected - * TODO: Confirm this - */ - /* read CLOCK_SELECT_REGISTER and save it */ - save_clock_select = pnp_read_config(dev, CLOCK_SELECT_REG); - /* set FUNC_PROG_SELECT so we read TSI_PIN_SELECT*/ - pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select | FUNC_PROG_SELECT); - f81803a_reg_dump(dev, f81803a_pme_regs1); - - /* now set it back to 0 and read the rest*/ - - pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select); - f81803a_reg_dump(dev, f81803a_pme_regs2); - - pnp_exit_conf_mode(dev); - printk(BIOS_INFO, "\nF81803A PME: Regs Done %s\n", s); -} -#endif static void f81803a_init(struct device *dev) { - - printk(BIOS_INFO, "F81803A_INIT.\n"); - if (!dev->enabled) return; - switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F81803A_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; - case F81803A_PME: -#ifdef F81803A_REGDUMP - f81803a_pme_reg_dump(dev,"before"); -#endif - f81803a_pme_init(dev); -#ifdef F81803A_REGDUMP - f81803a_pme_reg_dump(dev, "after"); -#endif - break; - - + case F81803A_PME: + f81803a_pme_init(dev); + break; } } static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, - .enable_resources = pnp_enable_resources, - .enable = pnp_alt_enable, - .init = f81803a_init, - .ops_pnp_mode = &pnp_conf_mode_8787_aa, + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f81803a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { @@ -155,6 +76,5 @@ } struct chip_operations superio_fintek_f81803a_ops = { - CHIP_NAME("Fintek F81803A Super I/O") .enable_dev = enable_dev }; -- To view, visit https://review.coreboot.org/21047 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib4b078a590ba27f698dad84d6bd6237c8331e60f Gerrit-Change-Number: 21047 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com>

1 0

Change in coreboot[master]: amd/padmelon: Clear GPIO overrides
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/21046 to review the following change. Change subject: amd/padmelon: Clear GPIO overrides ...................................................................... amd/padmelon: Clear GPIO overrides Remove the GPIO settings left over from Bettong. The following settings are no longer applicable: * 64: GBe / x4 Mux * 86: SATA switch New settings will be added as features are turned on. Change-Id: I57e5baddf0dc8dcb89d8fbc19f373887c40cd3c3 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/BiosCallOuts.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/21046/1 diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c index 152c724..91c5efe 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -51,8 +51,6 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); static const GPIO_CONTROL oem_padmelon_gpio[] = { - {86, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, - {64, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE | DrvStrengthSel_12mA}, {-1} }; /** -- To view, visit https://review.coreboot.org/21046 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I57e5baddf0dc8dcb89d8fbc19f373887c40cd3c3 Gerrit-Change-Number: 21046 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: AMD Padmelon Power Button Fix
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

Hello John E. Kabat Jr., I'd like you to do a code review. Please visit https://review.coreboot.org/21045 to review the following change. Change subject: AMD Padmelon Power Button Fix ...................................................................... AMD Padmelon Power Button Fix This code allows the Padmelon power button to work properly. Initialization of the F81803A was corrected and gpe.asl was modified to use _l08 for the power button and reset thePSIN_FLAG inthe SIO. Change-Id: I025be4d6bcc9de668681b59eb54dbcdbdd092bce Signed-off-by: John Kabat <john.kabat(a)scarletltd.com> --- M src/mainboard/amd/padmelon/acpi/gpe.asl A src/mainboard/amd/padmelon/acpi/superio.asl M src/mainboard/amd/padmelon/devicetree.cb M src/mainboard/amd/padmelon/dsdt.asl M src/superio/fintek/f81803a/Makefile.inc A src/superio/fintek/f81803a/chip.h M src/superio/fintek/f81803a/f81803a.h A src/superio/fintek/f81803a/f81803a_pme.c A src/superio/fintek/f81803a/fintek_internal.h M src/superio/fintek/f81803a/superio.c 10 files changed, 439 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/21045/1 diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl index 9a84698..ba8d878 100644 --- a/src/mainboard/amd/padmelon/acpi/gpe.asl +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -17,13 +17,19 @@ /* General event 3 */ Method(_L03) { - /* DBGO("\\_GPE\\_L00\n") */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + /* DBGO("\\_GPE\\_L03\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - /* Legacy PM event */ + /* Legacy PM event - Power Button */ Method(_L08) { - /* DBGO("\\_GPE\\_L08\n") */ + /* DBGO("\\_GPE\\_L08\n") */ + \_SB.SIO0.CPSI() /* clear psin state in sio */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } /* Temp warning (TWarn) event */ @@ -34,7 +40,7 @@ /* USB controller PME# */ Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ + /* DBGO("\\_GPE\\_L0B\n") */ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ @@ -57,7 +63,7 @@ /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ + /* DBGO("\\_GPE\\_L18\n") */ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ diff --git a/src/mainboard/amd/padmelon/acpi/superio.asl b/src/mainboard/amd/padmelon/acpi/superio.asl new file mode 100644 index 0000000..5341f82 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/superio.asl @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the W83627DHG SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x1 UARTA Implemented, partially tested + * 0x2 UARTB UART only, partially tested + * 0x4 HWM Resources, PM only + * 0x5 KBC Implemented, untested + * 0x6 GPIO6 Not implemented + * 0x7 WDT0&PLED Not implemented + * 0x9 GPIO2-5 Not implemented + * 0xa ACPI/PME/ERP Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * F81803A_SHOW_UARTA If defined, UARTA will be exposed. + * F81803A_SHOW_UARTB If defined, UARTB will be exposed. + * F81803A_SHOW_KBC If defined, the KBC will be exposed. + * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. + * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. + */ +#undef SUPERIO_DEV +#define SUPERIO_DEV SIO0 +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME F81803A +#define SUPERIO_PNP_BASE 0x4E +#include <superio/acpi/pnp.asl> + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F81803A Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + + offset(0xFB), + APC5, 8, /* PME ACPI Control Register 5 */ + } + + + + /* PMx-- registers to get the addresses of the ACPI Registers */ + IndexField(PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset(0x60), /* AcpiPmEvBlk */ + P1EB, 16, /* AcpiPmEvtBlk */ + P1CB, 16, /* AcpiPm1CntBlk */ + Offset(0xEE), + UPWS, 3, + } + + + /* AcpiPmEvtBlk registers*/ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, Nolock, Preserve) + { + Offset(0x02), /* Pm1Enable */ + , 14, + PEWD, 1, /* bit 1: PciExpWakeDis*/ + } + + + /* AcpiPm1CntBlk registers*/ + OperationRegion(P1C0, SystemIO, P1CB, 0x04) + Field(P1C0, ByteAcc, Nolock, Preserve) + { + Offset(0x00), /* PmControl */ + , 10, + P1ST, 3, /* Bits SlpTyp */ + P1SE, 1, /* SlpTypEn*/ + } + + OperationRegion(APCx, SystemIO, APC5, 0x01) + Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ + { + Offset(0x00), /*Control Reg 5 */ + , 7, + PSIN, 1, /* PSIN_FLAG */ + } + + /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ + Method(CPSI, 0, Serialized) + { + /* DBG0("SIO CPSI")*/ + ENTER_CONFIG_MODE(10) + Store(1, PSIN) + EXIT_CONFIG_MODE() + } + + + + Method(_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef F81803A_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #define SUPERIO_UART_PM_REG UAPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #define SUPERIO_UART_PM_REG UBPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + + +} diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb index 1902311..f47cc70 100644 --- a/src/mainboard/amd/padmelon/devicetree.cb +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -54,7 +54,6 @@ end # SM device pci 14.3 on # LPC 0x439d chip superio/fintek/f81803a - register "conf_key_mode" = "0x77" device pnp 4e.1 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 @@ -67,7 +66,7 @@ device pnp 4e.5 off end # KBC device pnp 4e.6 off end # GPIO device pnp 4e.7 off end # WDT - device pnp 4e.a off end # PME + device pnp 4e.a on end # PME end # f81803a end # LPC diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl index 2e6c96c..470ee26 100644 --- a/src/mainboard/amd/padmelon/dsdt.asl +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -34,7 +34,7 @@ /* PCI IRQ mapping for the Southbridge */ #include <southbridge/amd/pi/hudson/acpi/pcie.asl> - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_PR) */ #include <cpu/amd/pi/00660F01/acpi/cpu.asl> /* Contains the supported sleep states for this chipset */ @@ -72,6 +72,9 @@ /* Describe the devices in the Southbridge */ #include "acpi/carrizo_fch.asl" + /* Describe the Fintek F81803A SIO */ + #include "acpi/superio.asl" + } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */ diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc index 9156bf9..372de05 100644 --- a/src/superio/fintek/f81803a/Makefile.inc +++ b/src/superio/fintek/f81803a/Makefile.inc @@ -15,3 +15,4 @@ ## ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += superio.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A) += f81803a_pme.c diff --git a/src/superio/fintek/f81803a/chip.h b/src/superio/fintek/f81803a/chip.h new file mode 100644 index 0000000..063f746 --- /dev/null +++ b/src/superio/fintek/f81803a/chip.h @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F81803A_CHIP_H +#define SUPERIO_FINTEK_F81803A_CHIP_H + +#include <stdint.h> + +/* register in Fintek F81803A */ +#define LDN_REG 0x07 + +/* Global Control Registers */ +#define CLOCK_SELECT_REG 0x26 +#define FUNC_PROG_SELECT (1<<3) +#define CONFIG_PORT_SELECT_REG 0x27 + +#define TSI_LEVEL_SELECT_REG 0x28 /* FUNC_PROG_SEL = 0 */ +#define TSI_PIN_SELECT_REG 0x28 /* FUNC_PROG_SEL = 1 */ +#define MULTI_FUNC_SEL_REG1 0x29 +#define MULTI_FUNC_SEL_REG2 0x2A +#define MULTI_FUNC_SEL_REG3 0x2B +#define MULTI_FUNC_SEL_REG4 0x2C +#define WAKEUP_CONTROL_REG 0x2d + +/* LUN A - PMZE, ACPI, ERP */ +#define PME_DEVICE_ENABLE_REG 0x30 +#define PME_ENABLE (1<<0) +#define PME_ERP_ENABLE_REG 0xE0 +#define ERP_ENABLE (1<<7) +#define ERP_PME_EN (1<<1) +#define ERP_PSOUT_EN (1<<0) +#define PME_ERP_CONTROL_1_REG 0xE1 +#define PME_ERP_CONTROL_2_REG 0xE2 +#define PME_ERP_PSIN_DEBOUNCE_REG 0xE3 +#define PME_ERP_WAKEUP_ENABLE_REG 0xE8 +#define PME_ERP_MODE_SELECT_REG 0xEC +#define PME_EVENT_ENABLE_1_REG 0xF0 +#define PME_EVENT_STATUS_1_REG 0xF1 +#define PME_EVENT_ENABLE_2_REG 0xF2 +#define PME_EVENT_STATUS_2_REG 0xF3 +#define PME_ACPI_CONTROL_1_REG 0xF4 +#define PME_ACPI_CONTROL_2_REG 0xF5 +#define PME_ACPI_CONTROL_3_REG 0xF6 +#define PME_ACPI_CONTROL_4_REG 0xF7 +#define PME_ACPI_CONTROL_5_REG 0xFB +#define PME_ACPI_CONTROL_6_REG 0xFC + + +#endif /* SUPERIO_FINTEK_F81803A_CHIP_H */ diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h index ed78cab..9e2055c 100644 --- a/src/superio/fintek/f81803a/f81803a.h +++ b/src/superio/fintek/f81803a/f81803a.h @@ -18,6 +18,7 @@ * Datasheet: * - Name: F81803A */ + #ifndef SUPERIO_FINTEK_F81803_H #define SUPERIO_FINTEK_F81803_H @@ -31,3 +32,5 @@ #define F81803A_PME 0x0a /* Power Management Events (PME) */ #endif /* SUPERIO_FINTEK_F81803_H */ +#include "fintek_internal.h" + diff --git a/src/superio/fintek/f81803a/f81803a_pme.c b/src/superio/fintek/f81803a/f81803a_pme.c new file mode 100644 index 0000000..2223212 --- /dev/null +++ b/src/superio/fintek/f81803a/f81803a_pme.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "f81803a.h" + + + +void f81803a_pme_init(struct device *dev) +{ + + printk(BIOS_INFO, "F81803A PME: Init.\n"); + + pnp_enter_conf_mode(dev); + pnp_write_config(dev, LDN_REG, F81803A_PME); + + /* enable ERP function*/ + /* also set PSIN to generate PSOUT*/ + pnp_write_config(dev, PME_ERP_ENABLE_REG,ERP_ENABLE | ERP_PSOUT_EN); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/fintek/f81803a/fintek_internal.h b/src/superio/fintek/f81803a/fintek_internal.h new file mode 100644 index 0000000..5b8d275 --- /dev/null +++ b/src/superio/fintek/f81803a/fintek_internal.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2017 Nicola Corna <nicola(a)corna.info> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F81803A_INTERNAL_H +#define SUPERIO_FINTEK_F81803A_INTERNAL_H + +#include <arch/io.h> +#include <device/pnp.h> +#include "chip.h" + +struct f81803a_reg_tab +{ + const char *reg_name; + uint8_t reg; +}; +void f81803a_pme_init(struct device *dev); +void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab); +#endif /* SUPERIO_FINTEK_F81803A_INTERNAL_H */ diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c index c5504c1..3f5636a 100644 --- a/src/superio/fintek/f81803a/superio.c +++ b/src/superio/fintek/f81803a/superio.c @@ -23,8 +23,87 @@ #include <pc80/keyboard.h> #include "f81803a.h" +#ifdef F81803A_REGDUMP +/* for Debug */ +static struct f81803a_reg_tab f81803a_pme_regs1[] = { + + { "CLOCK_SELECT_REG", CLOCK_SELECT_REG }, + { "CONFIG_PORT_SELECT_REG", CONFIG_PORT_SELECT_REG }, + { "TSI_PIN_SELECT_REG", TSI_PIN_SELECT_REG }, + { NULL, 0 } +}; + + +static struct f81803a_reg_tab f81803a_pme_regs2[] = { + { "TSI_LEVEL_SELECT_REG", TSI_LEVEL_SELECT_REG }, + { "MULTI_FUNC_SEL_REG1", MULTI_FUNC_SEL_REG1 }, + { "MULTI_FUNC_SEL_REG2", MULTI_FUNC_SEL_REG2 }, + { "MULTI_FUNC_SEL_REG3", MULTI_FUNC_SEL_REG3 }, + { "MULTI_FUNC_SEL_REG4", MULTI_FUNC_SEL_REG4 }, + { "WAKEUP_CONTROL_REG", WAKEUP_CONTROL_REG }, + { "PME_DEVICE_ENABLE_REG", PME_DEVICE_ENABLE_REG }, + { "PME_ERP_ENABLE_REG", PME_ERP_ENABLE_REG }, + { "PME_ERP_CONTROL_1_REG", PME_ERP_CONTROL_1_REG }, + { "PME_ERP_CONTROL_2_REG", PME_ERP_CONTROL_2_REG }, + { "PME_ERP_PSIN_DEBOUNCE_REG", PME_ERP_PSIN_DEBOUNCE_REG }, + { "PME_ERP_WAKEUP_ENABLE_REG", PME_ERP_WAKEUP_ENABLE_REG }, + { "PME_EVENT_ENABLE_1_REG", PME_EVENT_ENABLE_1_REG }, + { "PME_EVENT_ENABLE_2_REG", PME_EVENT_ENABLE_2_REG }, + { "PME_ACPI_CONTROL_1_REG", PME_ACPI_CONTROL_1_REG }, + { "PME_ACPI_CONTROL_2_REG", PME_ACPI_CONTROL_2_REG }, + { "PME_ACPI_CONTROL_3_REG", PME_ACPI_CONTROL_3_REG }, + { "PME_ACPI_CONTROL_4_REG", PME_ACPI_CONTROL_4_REG }, + { "PME_ACPI_CONTROL_5_REG", PME_ACPI_CONTROL_5_REG }, + { "PME_ACPI_CONTROL_6_REG", PME_ACPI_CONTROL_6_REG }, + { NULL, 0 } +}; + +void f81803a_reg_dump(struct device *dev, struct f81803a_reg_tab *tab) +{ + uint8_t val; + for (; tab->reg_name; tab++) + { + val = pnp_read_config(dev, tab->reg); + printk(BIOS_INFO, " %02X %s %02X\n", tab->reg, tab->reg_name, val & 0xff); + } + +} +static void f81803a_pme_reg_dump(struct device *dev, const char *s) +{ + uint8_t save_clock_select; + printk(BIOS_INFO, "\nF81803A PME: Regs %s\n", s); + pnp_enter_conf_mode(dev); + pnp_write_config(dev, LDN_REG, F81803A_PME); + /* + * this is done with two tables as FUNC_PROG_SEL in CLOCK_SELECT_REG + * is used as a bank select register for the TSI registers index 28 + * We assume that FUNC_PROG_SELECT is 0 for now + * + * Note the actual writeup for FUNC_PROG_SEL on page 52 say: + * "Index 0x29, 0x2B and 0x2C bank select register" + * However this is not the case and only reg 28 appears to be affected + * TODO: Confirm this + */ + + /* read CLOCK_SELECT_REGISTER and save it */ + save_clock_select = pnp_read_config(dev, CLOCK_SELECT_REG); + /* set FUNC_PROG_SELECT so we read TSI_PIN_SELECT*/ + pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select | FUNC_PROG_SELECT); + f81803a_reg_dump(dev, f81803a_pme_regs1); + + /* now set it back to 0 and read the rest*/ + + pnp_write_config(dev, CLOCK_SELECT_REG, save_clock_select); + f81803a_reg_dump(dev, f81803a_pme_regs2); + + pnp_exit_conf_mode(dev); + printk(BIOS_INFO, "\nF81803A PME: Regs Done %s\n", s); +} +#endif static void f81803a_init(struct device *dev) { + + printk(BIOS_INFO, "F81803A_INIT.\n"); if (!dev->enabled) return; @@ -34,7 +113,19 @@ case F81803A_KBC: pc_keyboard_init(NO_AUX_DEVICE); break; + case F81803A_PME: +#ifdef F81803A_REGDUMP + f81803a_pme_reg_dump(dev,"before"); +#endif + f81803a_pme_init(dev); +#ifdef F81803A_REGDUMP + f81803a_pme_reg_dump(dev, "after"); +#endif + break; + + } + } static struct device_operations ops = { @@ -53,12 +144,13 @@ { &ops, F81803A_HWM, PNP_IO0 | PNP_IRQ0, 0xff8, }, { &ops, F81803A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, }, { &ops, F81803A_GPIO, PNP_IO0 | PNP_IRQ0, 0x7f8, }, - { &ops, F81803A_WDT, PNP_IO0, 0x7f8 }, + //{ &ops, F81803A_WDT, PNP_IO0, 0x7f8 }, { &ops, F81803A_PME, }, }; static void enable_dev(struct device *dev) { + printk(BIOS_INFO, "F81803A : enable_dev\n"); pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } -- To view, visit https://review.coreboot.org/21045 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I025be4d6bcc9de668681b59eb54dbcdbdd092bce Gerrit-Change-Number: 21045 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com>

1 0

Change in coreboot[master]: amd/padmelon: Remove board ID file
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/21044 to review the following change. Change subject: amd/padmelon: Remove board ID file ...................................................................... amd/padmelon: Remove board ID file Padmelon does not use an identifying scheme like Bettong. Remove the support associated with determining the ID. Change-Id: I34fb1d61016e84b8bd12b21de65fed40c5e2e4d9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/Makefile.inc D src/mainboard/amd/padmelon/boardid.c 2 files changed, 0 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/21044/1 diff --git a/src/mainboard/amd/padmelon/Makefile.inc b/src/mainboard/amd/padmelon/Makefile.inc index cfcc9c0..72cd042 100644 --- a/src/mainboard/amd/padmelon/Makefile.inc +++ b/src/mainboard/amd/padmelon/Makefile.inc @@ -15,9 +15,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c -romstage-y += boardid.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c -ramstage-y += boardid.c diff --git a/src/mainboard/amd/padmelon/boardid.c b/src/mainboard/amd/padmelon/boardid.c deleted file mode 100644 index 5cbb1a7..0000000 --- a/src/mainboard/amd/padmelon/boardid.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <southbridge/amd/common/amd_defs.h> -#include <boardid.h> - -/** - *todo: remove this file - * - *Bettong uses 3 GPIO(5-7) pins to identify board. - *The GPIO ports are mapped to MMIO space. - *The GPIO value and board version are mapped as follow: - *GPIO5 GPIO6 GPIO7 Version - * 0 0 0 A - * 0 0 1 B - * ...... - * 1 1 1 H - */ -uint8_t board_id(void) -{ - void *gpiommioaddr; - u8 value = 0; - u8 boardrev = 0; - char boardid; - - gpiommioaddr = (void *)AMD_SB_ACPI_MMIO_ADDR + 0x1500; - value = read8(gpiommioaddr + (7 << 2) + 2); /* agpio7: board_id2 */ - boardrev = value & 1; - value = read8(gpiommioaddr + (6 << 2) + 2); /* agpio6: board_id1 */ - boardrev |= (value & 1) << 1; - value = read8(gpiommioaddr + (5 << 2) + 2); /* agpio5: board_id0 */ - boardrev |= (value & 1) << 2; - - boardid = 'A' + boardrev; - - return boardid; -} -- To view, visit https://review.coreboot.org/21044 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I34fb1d61016e84b8bd12b21de65fed40c5e2e4d9 Gerrit-Change-Number: 21044 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: amd/padmelon: Remove XHCI1 setting
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/21043 to review the following change. Change subject: amd/padmelon: Remove XHCI1 setting ...................................................................... amd/padmelon: Remove XHCI1 setting Family 15h Models 60h-6Fh have only a single xHCI controller. Remove the disable for the second one. Change-Id: I26f525b282b6e6ffebed98fc6de3bbac135ed34d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/BiosCallOuts.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/21043/1 diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c index e316474..152c724 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -72,7 +72,6 @@ FchParams_reset->FchReset.SataEnable = hudson_sata_enable(); FchParams_reset->FchReset.IdeEnable = hudson_ide_enable(); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_padmelon_gpio; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; @@ -85,7 +84,6 @@ FchParams_env->Usb.Xhci0Enable = TRUE; else FchParams_env->Usb.Xhci0Enable = FALSE; - FchParams_env->Usb.Xhci1Enable = FALSE; FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ /* SD configuration */ -- To view, visit https://review.coreboot.org/21043 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I26f525b282b6e6ffebed98fc6de3bbac135ed34d Gerrit-Change-Number: 21043 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: amd/padmelon: Enable the SATA controller
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/21042 to review the following change. Change subject: amd/padmelon: Enable the SATA controller ...................................................................... amd/padmelon: Enable the SATA controller Change-Id: Ide5f0c9d63746a80a83a886dfb62e3475657cea0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/BiosCallOuts.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/21042/1 diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c index 7abb69a..e316474 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -69,6 +69,8 @@ FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + FchParams_reset->FchReset.SataEnable = hudson_sata_enable(); + FchParams_reset->FchReset.IdeEnable = hudson_ide_enable(); FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_reset->FchReset.Xhci1Enable = FALSE; FchParams_reset->EarlyOemGpioTable = oem_padmelon_gpio; @@ -86,7 +88,6 @@ FchParams_env->Usb.Xhci1Enable = FALSE; FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ - /* sata configuration */ /* SD configuration */ FchParams_env->Sd.SdSlotType = 1; /* eMMC */ } -- To view, visit https://review.coreboot.org/21042 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide5f0c9d63746a80a83a886dfb62e3475657cea0 Gerrit-Change-Number: 21042 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: amd/padmelon: Fix SD controller setting
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/21041 to review the following change. Change subject: amd/padmelon: Fix SD controller setting ...................................................................... amd/padmelon: Fix SD controller setting Remove the check for the board ID and downgrading the performance. Also set the configuration for eMMC. Change-Id: If01e426760138a3dc0487ba99ac87b35a939a958 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/BiosCallOuts.c 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/21041/1 diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c index 5c11742..7abb69a 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -88,10 +88,7 @@ /* sata configuration */ /* SD configuration */ - /* Rev F has an on-board eMMC, which only supports SD 2.0 */ - if (board_id() == 'F') { - FchParams_env->Sd.SdConfig = SdVer2; - } + FchParams_env->Sd.SdSlotType = 1; /* eMMC */ } printk(BIOS_DEBUG, "Done\n"); -- To view, visit https://review.coreboot.org/21041 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If01e426760138a3dc0487ba99ac87b35a939a958 Gerrit-Change-Number: 21041 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Change in coreboot[master]: amd/padmelon: Fix if IS_ENABLED()
by John E. Kabat (Code Review) 16 Aug '17

16 Aug '17

Hello Marshall Dawson, I'd like you to do a code review. Please visit https://review.coreboot.org/21040 to review the following change. Change subject: amd/padmelon: Fix if IS_ENABLED() ...................................................................... amd/padmelon: Fix if IS_ENABLED() Convert the #if usage to if(). Complete remove the #if IS_ENABLED that controls including imc.h. Change-Id: Ia9f18b40a931c00a0c4d873f40c2ddd853611d63 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/padmelon/BiosCallOuts.c 1 file changed, 6 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/21040/1 diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c index ac18f94..5c11742 100644 --- a/src/mainboard/amd/padmelon/BiosCallOuts.c +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -23,9 +23,7 @@ #include "heapManager.h" #include "FchPlatform.h" #include "cbfs.h" -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) #include "imc.h" -#endif #include "hudson.h" #include <stdlib.h> #include "BiosCallOuts.h" @@ -77,16 +75,14 @@ } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - oem_fan_control(FchParams_env); -#endif + if (IS_ENABLED(CONFIG_HUDSON_IMC_FWM)) + oem_fan_control(FchParams_env); /* XHCI configuration */ -#if IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE) - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + if (IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE)) + FchParams_env->Usb.Xhci0Enable = TRUE; + else + FchParams_env->Usb.Xhci0Enable = FALSE; FchParams_env->Usb.Xhci1Enable = FALSE; FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ -- To view, visit https://review.coreboot.org/21040 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia9f18b40a931c00a0c4d873f40c2ddd853611d63 Gerrit-Change-Number: 21040 Gerrit-PatchSet: 1 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2017