coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Move PMC lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21029 ) Change subject: soc/intel/skylake: Move PMC lock down config after PCI enumeration ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58633/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14016/ : SUCCESS -- To view, visit https://review.coreboot.org/21029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Gerrit-Change-Number: 21029 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 16 Aug 2017 13:50:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Remove TCO lock down programming
by Subrata Banik (Code Review) 16 Aug '17

16 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21031 Change subject: soc/intel/skylake: Remove TCO lock down programming ...................................................................... soc/intel/skylake: Remove TCO lock down programming FSP is doing TCO lock inside Notofy 1 hence remove TCO Lock down programming inside coreboot. TEST= Ensure TCO_LOCK offset 8 bit 12 is set. Change-Id: Iec9e3075df01862f8558b303a458126c68202bff Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/finalize.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/21031/1 diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 53c1c58..aed7e87 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -86,8 +86,6 @@ { device_t dev; uint32_t reg32; - u16 tcobase; - u16 tcocnt; uint8_t *pmcbase; config_t *config; u8 reg8; @@ -97,12 +95,6 @@ /* Lock FAST_SPIBAR */ fast_spi_lock_bar(); - - /*TCO Lock down */ - tcobase = smbus_tco_regs(); - tcocnt = inw(tcobase + TCO1_CNT); - tcocnt |= TCO_LOCK; - outw(tcocnt, tcobase + TCO1_CNT); /* Display me status before we hide it */ intel_me_status(); -- To view, visit https://review.coreboot.org/21031 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec9e3075df01862f8558b303a458126c68202bff Gerrit-Change-Number: 21031 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Move DMI lock down config after PCI enumeration
by Subrata Banik (Code Review) 16 Aug '17

16 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21030 Change subject: soc/intel/skylake: Move DMI lock down config after PCI enumeration ...................................................................... soc/intel/skylake: Move DMI lock down config after PCI enumeration This patch to ensures that coreboot is meeting Intel Silicon recommendation to performing register lockdown. TEST=Ensure DMI register offset 0x274c bit 0 is set. Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/lockdown.c 2 files changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/21030/1 diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 3bb1324..53c1c58 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -35,8 +35,6 @@ #include <soc/systemagent.h> #include <stdlib.h> -#define PCR_DMI_GCS 0x274C -#define PCR_DMI_GCS_BILD (1 << 0) #define PSF_BASE_ADDRESS 0xA00 #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) @@ -154,12 +152,8 @@ } /* Bios Interface Lock */ - if (config->LockDownConfigBiosInterface == 0) { + if (config->LockDownConfigBiosInterface == 0) fast_spi_set_bios_interface_lock_down(); - - /* GCS reg of DMI */ - pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); - } /* Bios Lock */ if (config->LockDownConfigBiosLock == 0) diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 7564131..e31cf09 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -17,10 +17,15 @@ #include <bootstate.h> #include <chip.h> #include <console/console.h> +#include <intelblocks/pcr.h> #include <soc/lpc.h> #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <soc/pm.h> #include <string.h> + +#define PCR_DMI_GCS 0x274C +#define PCR_DMI_GCS_BILD (1 << 0) static void lpc_lockdown_config(void) { @@ -68,6 +73,12 @@ write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); } +static void dmi_lockdown_config(void) +{ + /* GCS reg of DMI */ + pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); +} + static void platform_lockdown_config(void *unused) { /* LPC lock down configuration */ @@ -75,6 +86,9 @@ /* PMC lock down configuration */ pmc_lockdown_config(); + + /* DMI lock down configuration */ + dmi_lockdown_config(); } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, -- To view, visit https://review.coreboot.org/21030 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Gerrit-Change-Number: 21030 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Move PMC lock down config after PCI enumeration
by Subrata Banik (Code Review) 16 Aug '17

16 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21029 Change subject: soc/intel/skylake: Move PMC lock down config after PCI enumeration ...................................................................... soc/intel/skylake: Move PMC lock down config after PCI enumeration This patch to ensure that coreboot is meeting Intel Silicon recommendation to performing register lockdown. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/lockdown.c 2 files changed, 21 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/21029/1 diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 01aa4dd..3bb1324 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -92,7 +92,6 @@ u16 tcocnt; uint8_t *pmcbase; config_t *config; - u32 pmsyncreg; u8 reg8; /* Set FAST_SPI opcode menu */ @@ -107,22 +106,11 @@ tcocnt |= TCO_LOCK; outw(tcocnt, tcobase + TCO1_CNT); - /* Lock down ABASE and sleep stretching policy */ - dev = PCH_DEV_PMC; - reg32 = pci_read_config32(dev, GEN_PMCON_B); - reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK); - pci_write_config32(dev, GEN_PMCON_B, reg32); - - /* PMSYNC */ - pmcbase = pmc_mmio_regs(); - pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); - pmsyncreg |= PMSYNC_LOCK; - write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); - /* Display me status before we hide it */ intel_me_status(); - /* we should disable Heci1 based on the devicetree policy */ + dev = PCH_DEV_PMC; + pmcbase = pmc_mmio_regs(); config = dev->chip_info; /* diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index a61e423..7564131 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <soc/lpc.h> #include <soc/pci_devs.h> +#include <soc/pm.h> #include <string.h> static void lpc_lockdown_config(void) @@ -52,10 +53,28 @@ pci_read_config8(dev, BIOS_CNTL); } +static void pmc_lockdown_config(void) +{ + struct device *dev; + uint8_t *pmcbase; + u32 pmsyncreg; + + dev = PCH_DEV_PMC; + + /* PMSYNC */ + pmcbase = pmc_mmio_regs(); + pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG); + pmsyncreg |= PMSYNC_LOCK; + write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg); +} + static void platform_lockdown_config(void *unused) { /* LPC lock down configuration */ lpc_lockdown_config(); + + /* PMC lock down configuration */ + pmc_lockdown_config(); } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, -- To view, visit https://review.coreboot.org/21029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Gerrit-Change-Number: 21029 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Sideband lock skipped in FSP and done in coreboot
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20956 ) Change subject: soc/intel/skylake: Sideband lock skipped in FSP and done in coreboot ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58632/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14015/ : SUCCESS -- To view, visit https://review.coreboot.org/20956 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a Gerrit-Change-Number: 20956 Gerrit-PatchSet: 6 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 16 Aug 2017 13:25:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/intel/gma: Put gma_gfxinit() into its own header
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20112 ) Change subject: drivers/intel/gma: Put gma_gfxinit() into its own header ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58631/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14014/ : SUCCESS -- To view, visit https://review.coreboot.org/20112 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89 Gerrit-Change-Number: 20112 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 12:46:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/smbus: Reuse I2C bus operations where applicable
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20855 ) Change subject: device/smbus: Reuse I2C bus operations where applicable ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58629/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14012/ : SUCCESS -- To view, visit https://review.coreboot.org/20855 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a93f17b905de38752254891aa4347ba4ed3b205 Gerrit-Change-Number: 20855 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 12:38:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/i2c/rx6110sa: Drop I2C interface arbitration
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20454 ) Change subject: drivers/i2c/rx6110sa: Drop I2C interface arbitration ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58628/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14011/ : SUCCESS -- To view, visit https://review.coreboot.org/20454 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib31e77eec639c231520198c0b978d6c3c1eadaed Gerrit-Change-Number: 20454 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 12:27:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Reinvent I2C ops
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20846 ) Change subject: Reinvent I2C ops ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58630/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14013/ : SUCCESS -- To view, visit https://review.coreboot.org/20846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818 Gerrit-Change-Number: 20846 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 16 Aug 2017 12:27:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/common/mrc_cache: Move update_mrc_cache after BS_DEV_RESOURCES
by build bot (Jenkins) (Code Review) 16 Aug '17

16 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21028 ) Change subject: intel/common/mrc_cache: Move update_mrc_cache after BS_DEV_RESOURCES ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58627/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14010/ : SUCCESS -- To view, visit https://review.coreboot.org/21028 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0 Gerrit-Change-Number: 21028 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 16 Aug 2017 11:44:37 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017