coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Fix SGX init sequence
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21007 ) Change subject: soc/intel/skylake: Fix SGX init sequence ...................................................................... Patch Set 4: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58807/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/14171/ : SUCCESS -- To view, visit https://review.coreboot.org/21007 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1 Gerrit-Change-Number: 21007 Gerrit-PatchSet: 4 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 00:35:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/inte/cannonlake: Define soc_intel_cannonlake_config
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21080 ) Change subject: soc/inte/cannonlake: Define soc_intel_cannonlake_config ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58805/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14170/ : SUCCESS -- To view, visit https://review.coreboot.org/21080 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Gerrit-Change-Number: 21080 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 23:59:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/inte/cannonlake: Define soc_intel_cannonlake_config
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21080 ) Change subject: soc/inte/cannonlake: Define soc_intel_cannonlake_config ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58804/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/14169/ : SUCCESS -- To view, visit https://review.coreboot.org/21080 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Gerrit-Change-Number: 21080 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 23:52:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/inte/cannonlake: Define soc_intel_cannonlake_config
by Pratikkumar V Prajapati (Code Review) 18 Aug '17

18 Aug '17

Pratikkumar V Prajapati has uploaded a new patch set (#2). ( https://review.coreboot.org/21080 ) Change subject: soc/inte/cannonlake: Define soc_intel_cannonlake_config ...................................................................... soc/inte/cannonlake: Define soc_intel_cannonlake_config - Populate soc_intel_cannonlake_config - Add usb.h and vr_config.h for CannonLake Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/include/soc/usb.h A src/soc/intel/cannonlake/include/soc/vr_config.h 3 files changed, 295 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/21080/2 -- To view, visit https://review.coreboot.org/21080 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Gerrit-Change-Number: 21080 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/inte/cannonlake: Define soc_intel_cannonlake_config
by Pratikkumar V Prajapati (Code Review) 18 Aug '17

18 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21080 Change subject: soc/inte/cannonlake: Define soc_intel_cannonlake_config ...................................................................... soc/inte/cannonlake: Define soc_intel_cannonlake_config - Populate soc_intel_cannonlake_config - Add usb.h and vr_config.h for CannonLake Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/include/soc/usb.h A src/soc/intel/cannonlake/include/soc/vr_config.h 3 files changed, 297 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/21080/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 67be85d..a3f5ffc 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -20,10 +20,200 @@ #include <intelblocks/gspi.h> #include <stdint.h> +#include <soc/usb.h> +#include <soc/vr_config.h> struct soc_intel_cannonlake_config { + + /* Interrupt Routing configuration. + * If bit7 is 1, the interrupt is disabled. */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; + + /* GPE configuration */ + uint32_t gpe0_en_1; /* GPE0_EN_31_0 */ + uint32_t gpe0_en_2; /* GPE0_EN_63_32 */ + uint32_t gpe0_en_3; /* GPE0_EN_95_64 */ + uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */ + + /* Gpio group routed to each dword of the GPE0 block. Values are + * of the form GPP_[A:G] or GPD. */ + uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable S0iX support */ + int s0ix_enable; + /* Enable DPTF support */ + int dptf_enable; + + /* Deep SX enable for both AC and DC */ + int deep_s3_enable; + int deep_s5_enable; + + /* + * Deep Sx Configuration + * DSX_EN_WAKE_PIN - Enable WAKE# pin + * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin + * DSX_EN_AC_PRESENT_PIN - Enable AC_PRESENT pin + */ + uint32_t deep_sx_config; + + /* TCC activation offset */ + uint32_t tcc_offset; + + uint64_t PlatformMemorySize; + uint8_t SmramMask; + uint8_t MrcFastBoot; + uint32_t TsegSize; + uint16_t MmioSize; + + /* DDR Frequency Limit. Maximum Memory Frequency Selections in Mhz. + * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ + uint16_t DdrFreqLimit; + + /* SAGV Low Frequency Selections in Mhz. + * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ + uint16_t FreqSaGvLow; + + /* SAGV Mid Frequency Selections in Mhz. + * Options : 1067, 1333, 1600, 1867, 2133, 2400, 2667, 2933, 0(Auto) */ + uint16_t FreqSaGvMid; + + /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. + * When enabled memory will be training at two different frequencies. + * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled */ + uint8_t SaGv; + + /* Rank Margin Tool. 1:Enable, 0:Disable */ + uint8_t RMT; + + /* LAN controller. 1:Enable, 0:Disable */ + uint8_t PchLanEnable; + + /* USB related */ + struct usb2_port_config usb2_ports[16]; + struct usb3_port_config usb3_ports[10]; + uint8_t XdciEnable; + uint8_t SsicPortEnable; + + /* SATA related */ + uint8_t SataEnable; + uint8_t SataMode; + uint8_t SataSalpSupport; + uint8_t SataPortsEnable[8]; + uint8_t SataPortsDevSlp[8]; + + /* Audio related */ + uint8_t PchHdaEnable; + uint8_t PchHdaDspEnable; + + /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ + uint8_t PchHdaAudioLinkHda; + + /* Pcie Root Ports */ + uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; + + /* SMBus */ + uint8_t SmbusEnable; + /* GSPI */ struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; + + /* eMMC and SD */ + uint8_t ScsEmmcEnabled; + uint8_t ScsEmmcHs400Enabled; + uint8_t PchScsEmmcHs400TuningRequired; + uint8_t ScsSdCardEnabled; + uint8_t ScsUfsEnabled; + + /* Integrated Sensor */ + uint8_t PchIshEnable; + + /* Heci related */ + uint8_t HeciTimeouts; + uint8_t Heci3Enabled; + + /* Gfx related */ + uint8_t IgdDvmt50PreAlloc; + uint8_t PrimaryDisplay; + uint8_t InternalGfx; + uint8_t ApertureSize; + uint8_t SkipExtGfxScan; + uint8_t ScanExtGfxForLegacyOpRom; + + uint32_t LogoPtr; + uint32_t LogoSize; + uint32_t GraphicsConfigPtr; + uint8_t Device4Enable; + + uint8_t RtcLock; + /* GPIO IRQ Select. The valid value is 14 or 15 */ + uint8_t GpioIrqRoute; + /* SCI IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */ + uint8_t SciIrqSelect; + /* TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23 */ + uint8_t TcoIrqSelect; + uint8_t TcoIrqEnable; + /* Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit */ + uint8_t PchLockDownGlobalSmi; + /* Enable BIOS Interface Lock Down bit to prevent writes to + * the Backup Control Register. */ + uint8_t PchLockDownBiosInterface; + /* Enable the BIOS Lock feature and set EISS bit for the + * BIOS region protection. */ + uint8_t PchLockDownBiosLock; + /* PCH power button override period. + * 000b-4s, 0001b-6s, 0010b-8s, 0011b-10s, 0100b-12s, 0101b-14s */ + uint8_t PchPmPwrBtnOverridePeriod; + + enum { + RESET_POWER_CYCLE_DEFAULT = 0, + RESET_POWER_CYCLE_1S = 1, + RESET_POWER_CYCLE_2S = 2, + RESET_POWER_CYCLE_3S = 3, + RESET_POWER_CYCLE_4S = 4, + } PmConfigPwrCycDur; + + /* Determines if enable Serial IRQ. 0:Disabled, 1:Enabled */ + uint8_t PchSirqEnable; + /* Serial IRQ Mode Select. 0:PchQuietMode, 1:PchContinuousMode */ + uint8_t PchSirqMode; + /* Start Frame Pulse Width. + * Values: 0:PchSfpw4Clk, 1:PchSfpw6Clk, 2:PchSfpw8Clk */ + uint8_t PchStartFramePulse; + uint8_t SkipMpInit; + /* VrConfig Settings for 5 domains + * 0 = System Agent, 1 = IA Core, 2 = Ring, + * 3 = GT unsliced, 4 = GT sliced */ + struct vr_config domain_vr_config[NUM_VR_DOMAINS]; + /* HeciEnabled decides the state of Heci1 at end of boot + * Setting to 0 (default) disables Heci1 and hides the device from OS */ + uint8_t HeciEnabled; + /* PL2 Override value in Watts */ + uint32_t tdp_pl2_override; + /* Intel Speed Shift Technology */ + uint8_t speed_shift_enable; + /* Enable VR specific mailbox command + * 00b - no VR specific cmd sent + * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent + * 10b - VR specific cmd sent for PS4 exit issue + * 11b - Reserved */ + uint8_t SendVrMbxCmd; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h new file mode 100644 index 0000000..eac017e --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_USB_H_ +#define _SOC_USB_H_ + +#include <stdint.h> + +struct usb2_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_bias; + uint8_t tx_emp_enable; + uint8_t pre_emp_bias; + uint8_t pre_emp_bit; +}; + +struct usb3_port_config { + uint8_t enable; + uint8_t ocpin; + uint8_t tx_de_emp; + uint8_t tx_downscale_amp; +}; + +#endif diff --git a/src/soc/intel/cannonlake/include/soc/vr_config.h b/src/soc/intel/cannonlake/include/soc/vr_config.h new file mode 100644 index 0000000..47f659a --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/vr_config.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* VR Settings for each domain */ + +#ifndef _SOC_VR_CONFIG_H_ +#define _SOC_VR_CONFIG_H_ + +#include <fsp/api.h> + +struct vr_config { + + /* The below settings will take effect when this is set to 1 + * for that domain. */ + uint8_t vr_config_enable; + + /* Power State X current cuttof in 1/4 Amp increments + * Range is 0-128A */ + uint16_t psi1threshold; + uint16_t psi2threshold; + uint16_t psi3threshold; + + /* Enable power state 3/4 for different domains */ + uint8_t psi3enable; + uint8_t psi4enable; + + /* Imon slope correction. Specified in 1/100 increment + * values. Range is 0-200. 125 = 1.25 */ + uint8_t imon_slope; + + /* Imon offset correction. Units 1/1000, Range 0-63999 + * For an offset = 12.580, use 12580. 0 = Auto */ + uint8_t imon_offset; + + /* VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A */ + uint16_t icc_max; + + /* VR Voltage Limit. Range is 0-7999mV */ + uint16_t voltage_limit; + + /* AC and DC Loadline in 1/100 mOhms. Range is 0-6249 */ + uint16_t ac_loadline; + uint16_t dc_loadline; +}; + +/* VrConfig Settings for 4 domains + * 0 = System Agent, 1 = IA Core, + * 2 = GT unsliced, 3 = GT sliced */ +enum vr_domain { + VR_SYSTEM_AGENT, + VR_IA_CORE, + VR_GT_UNSLICED, + VR_GT_SLICED, + NUM_VR_DOMAINS +}; + +#endif -- To view, visit https://review.coreboot.org/21080 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Gerrit-Change-Number: 21080 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add functions to common CPU library code
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21051 ) Change subject: soc/intel/common/block: Add functions to common CPU library code ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58803/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14168/ : SUCCESS -- To view, visit https://review.coreboot.org/21051 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id34eb7e03069656238ca0cbdf6ce33f116e0e413 Gerrit-Change-Number: 21051 Gerrit-PatchSet: 3 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 23:22:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: binarypi mainboards: Clean up IS_ENABLED fan control
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21058 ) Change subject: binarypi mainboards: Clean up IS_ENABLED fan control ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58784/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14149/ : SUCCESS -- To view, visit https://review.coreboot.org/21058 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If88af42d00227285931829441909a982fc292b2b Gerrit-Change-Number: 21058 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 22:56:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: AGESA mainboards: Clean up IS_ENABLED fan control
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21059 ) Change subject: AGESA mainboards: Clean up IS_ENABLED fan control ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58785/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14150/ : SUCCESS -- To view, visit https://review.coreboot.org/21059 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9 Gerrit-Change-Number: 21059 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 22:56:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd: Standardize guards on header files
by Marshall Dawson (Code Review) 18 Aug '17

18 Aug '17

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/21073 ) Change subject: soc/amd: Standardize guards on header files ...................................................................... Patch Set 1: (2 comments) If you touch this patch again, you could also standardize the #endif /* __NAME_H__ */ . Some have a tab after endif and others a single space. Otherwise, meh. https://review.coreboot.org/#/c/21073/1/src/soc/amd/common/dimmSpd.h File src/soc/amd/common/dimmSpd.h: https://review.coreboot.org/#/c/21073/1/src/soc/amd/common/dimmSpd.h@26 PS1, Line 26: #endif I saw you added a comment in another file on an #endif. I don't feel like one is needed here, but thought I'd mention it in case you left it out accidentally. https://review.coreboot.org/#/c/21073/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/imc.h: https://review.coreboot.org/#/c/21073/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 27: #endif Same comment as before regarding the #endif. -- To view, visit https://review.coreboot.org/21073 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4466df529ab201c922096a31d7438381778b582f Gerrit-Change-Number: 21073 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 22:53:33 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: amd/bettong: Fix IS_ENABLED for xHCI
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21060 ) Change subject: amd/bettong: Fix IS_ENABLED for xHCI ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58786/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14151/ : SUCCESS -- To view, visit https://review.coreboot.org/21060 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf6db485735cb8bbadb3e742a079d0bafaacd79c Gerrit-Change-Number: 21060 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 22:53:25 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017