coreboot-gerrit August 2017

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Change in coreboot[master]: soc/amd: Standardize guards on header files
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21073 ) Change subject: soc/amd: Standardize guards on header files ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58779/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14145/ : SUCCESS -- To view, visit https://review.coreboot.org/21073 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4466df529ab201c922096a31d7438381778b582f Gerrit-Change-Number: 21073 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 21:57:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Update vboot submodule to upstream master
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21074 ) Change subject: Update vboot submodule to upstream master ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58780/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14146/ : SUCCESS -- To view, visit https://review.coreboot.org/21074 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89 Gerrit-Change-Number: 21074 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 21:55:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Update depthcharge stable to upstream master
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21075 ) Change subject: Update depthcharge stable to upstream master ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58778/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14144/ : SUCCESS -- To view, visit https://review.coreboot.org/21075 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If030bc3e75dd470838590540880213bd841154b8 Gerrit-Change-Number: 21075 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 21:46:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Update depthcharge stable to upstream master
by Martin Roth (Code Review) 17 Aug '17

17 Aug '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21075 Change subject: Update depthcharge stable to upstream master ...................................................................... Update depthcharge stable to upstream master Updating from commit id 5a086f5c - Tue Jul 11 23:57:30 2017: (ps8751: enable software sync.) to commit id a843f262 - Wed Aug 16 23:37:52 2017: (kahlee: select emmc boot first if available) This brings in 20 new commits. This matches with the updated vboot submodule. Change-Id: If030bc3e75dd470838590540880213bd841154b8 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M payloads/external/depthcharge/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21075/1 diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index 8115eb1..f069e95 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -1,5 +1,5 @@ # stabilize-9430.B - Wed Mar 29, 2017 -STABLE_COMMIT_ID=5a086f5c9a5edd56d5dc81e11af10597aaab4218 +STABLE_COMMIT_ID=a843f262420f0e1a7f70d3f8f590d32a78d05ef8 project_name=depthcharge project_dir=$(CURDIR)/depthcharge -- To view, visit https://review.coreboot.org/21075 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If030bc3e75dd470838590540880213bd841154b8 Gerrit-Change-Number: 21075 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: Update vboot submodule to upstream master
by Martin Roth (Code Review) 17 Aug '17

17 Aug '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21074 Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 8b714252: 2017-07-18 02:36:16 -0700 - (crossystem: Remove defunct sw_wpsw_boot field) to commit id 8c4b8285: 2017-08-14 20:37:45 -0700 - (detachables: Skip "Enable Developer Mode" in DEV mode) This brings in 6 new commits. Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/21074/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 8b71425..8c4b828 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 8b71425257d251858410de71efcf389df8b200d2 +Subproject commit 8c4b828502d8c6c7112286720dddfd30c92a968e -- To view, visit https://review.coreboot.org/21074 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7769035453796a162c6313cd0c87661ef1e64f89 Gerrit-Change-Number: 21074 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd: Standardize guards on header files
by Martin Roth (Code Review) 17 Aug '17

17 Aug '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21073 Change subject: soc/amd: Standardize guards on header files ...................................................................... soc/amd: Standardize guards on header files The guards in the header files were inconsistent. Some had no leading or trailing underscores, some had one, some had both leading and trailing. Change all to double leading & trailing underscores. BUG=b:62235990 Test=Build Kahlee Change-Id: I4466df529ab201c922096a31d7438381778b582f Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/BiosCallOuts.h M src/soc/amd/common/agesawrapper.h M src/soc/amd/common/agesawrapper_call.h M src/soc/amd/common/amd_defs.h M src/soc/amd/common/amd_pci_util.h M src/soc/amd/common/block/include/amdblocks/psp.h M src/soc/amd/common/dimmSpd.h M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/include/amd_pci_int_defs.h M src/soc/amd/stoneyridge/include/amd_pci_int_types.h M src/soc/amd/stoneyridge/include/soc/acpi.h M src/soc/amd/stoneyridge/include/soc/gpio.h M src/soc/amd/stoneyridge/include/soc/imc.h M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/nvs.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/smbus.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/southbridge.h 19 files changed, 54 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21073/1 diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h index 50931dc..4456466 100644 --- a/src/soc/amd/common/BiosCallOuts.h +++ b/src/soc/amd/common/BiosCallOuts.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef CALLOUTS_AMD_AGESA_H -#define CALLOUTS_AMD_AGESA_H +#ifndef __CALLOUTS_AMD_AGESA_H__ +#define __CALLOUTS_AMD_AGESA_H__ #include <Porting.h> #include <AGESA.h> @@ -64,4 +64,4 @@ extern const BIOS_CALLOUT_STRUCT BiosCallouts[]; extern const int BiosCalloutsLen; -#endif /* CALLOUTS_AMD_AGESA_H */ +#endif /* __CALLOUTS_AMD_AGESA_H__ */ diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h index 97d52f7..b42f531 100644 --- a/src/soc/amd/common/agesawrapper.h +++ b/src/soc/amd/common/agesawrapper.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _AGESAWRAPPER_H_ -#define _AGESAWRAPPER_H_ +#ifndef __AGESAWRAPPER_H__ +#define __AGESAWRAPPER_H__ #include <stdint.h> #include <Porting.h> @@ -56,4 +56,4 @@ void OemPostParams(AMD_POST_PARAMS *PostParams); -#endif /* _AGESAWRAPPER_H_ */ +#endif /* __AGESAWRAPPER_H__ */ diff --git a/src/soc/amd/common/agesawrapper_call.h b/src/soc/amd/common/agesawrapper_call.h index 64c97f6..21a1e23 100644 --- a/src/soc/amd/common/agesawrapper_call.h +++ b/src/soc/amd/common/agesawrapper_call.h @@ -11,8 +11,8 @@ * GNU General Public License for more details. */ -#ifndef _AGESAWRAPPER_CALL_H_ -#define _AGESAWRAPPER_CALL_H_ +#ifndef __AGESAWRAPPER_CALL_H__ +#define __AGESAWRAPPER_CALL_H__ #include <stdint.h> #include <console/console.h> @@ -56,4 +56,4 @@ #define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func() -#endif +#endif /* __AGESAWRAPPER_CALL_H__ */ diff --git a/src/soc/amd/common/amd_defs.h b/src/soc/amd/common/amd_defs.h index 55db30f..e4ce1db 100644 --- a/src/soc/amd/common/amd_defs.h +++ b/src/soc/amd/common/amd_defs.h @@ -14,8 +14,8 @@ */ -#ifndef _AMD_SB_DEFS_H_ -#define _AMD_SB_DEFS_H_ +#ifndef __AMD_SB_DEFS_H__ +#define __AMD_SB_DEFS_H__ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000ul diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/amd_pci_util.h index 4789542..b8d48ef 100644 --- a/src/soc/amd/common/amd_pci_util.h +++ b/src/soc/amd/common/amd_pci_util.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef AMD_PCI_UTIL_H -#define AMD_PCI_UTIL_H +#ifndef __AMD_PCI_UTIL_H__ +#define __AMD_PCI_UTIL_H__ #include <stdint.h> #include <amd_pci_int_defs.h> @@ -38,4 +38,4 @@ void write_pci_cfg_irqs(void); void write_pci_int_table(void); -#endif /* AMD_PCI_UTIL_H */ +#endif /* __AMD_PCI_UTIL_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h index c70c0b1..42b9fb7 100644 --- a/src/soc/amd/common/block/include/amdblocks/psp.h +++ b/src/soc/amd/common/block/include/amdblocks/psp.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef AMD_PSP_H -#define AMD_PSP_H +#ifndef __AMD_PSP_H__ +#define __AMD_PSP_H__ #include <stdint.h> #include <compiler.h> @@ -94,4 +94,4 @@ /* BIOS-to-PSP functions return 0 if successful, else negative value */ int psp_notify_dram(void); -#endif /* AMD_PSP_H */ +#endif /* __AMD_PSP_H__ */ diff --git a/src/soc/amd/common/dimmSpd.h b/src/soc/amd/common/dimmSpd.h index 75a7990..cdcdb73 100644 --- a/src/soc/amd/common/dimmSpd.h +++ b/src/soc/amd/common/dimmSpd.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _DIMMSPD_H_ -#define _DIMMSPD_H_ +#ifndef __DIMMSPD_H__ +#define __DIMMSPD_H__ AGESA_STATUS AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data, diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 747c295..cd3bc74 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef STONEYRIDGE_CHIP_H -#define STONEYRIDGE_CHIP_H +#ifndef __STONEYRIDGE_CHIP_H__ +#define __STONEYRIDGE_CHIP_H__ #include <stdint.h> @@ -32,4 +32,4 @@ extern struct device_operations pci_domain_ops; -#endif /* STONEYRIDGE_CHIP_H */ +#endif /* __STONEYRIDGE_CHIP_H__ */ diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h index f3f60d3..a8e75f63 100644 --- a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef AMD_PCI_INT_DEFS_H -#define AMD_PCI_INT_DEFS_H +#ifndef __AMD_PCI_INT_DEFS_H__ +#define __AMD_PCI_INT_DEFS_H__ /* * PIRQ and device routing - these define the index @@ -72,4 +72,4 @@ #define PIRQ_UART0 0x74 #define PIRQ_UART1 0x75 -#endif /* AMD_PCI_INT_DEFS_H */ +#endif /* __AMD_PCI_INT_DEFS_H__ */ diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h index ab1f70b..08bdc10 100644 --- a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h +++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef AMD_PCI_INT_TYPES_H -#define AMD_PCI_INT_TYPES_H +#ifndef __AMD_PCI_INT_TYPES_H__ +#define __AMD_PCI_INT_TYPES_H__ const char *intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", @@ -34,4 +34,4 @@ [0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t", }; -#endif /* AMD_PCI_INT_TYPES_H */ +#endif /* __AMD_PCI_INT_TYPES_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h index f573b0e..0452567 100644 --- a/src/soc/amd/stoneyridge/include/soc/acpi.h +++ b/src/soc/amd/stoneyridge/include/soc/acpi.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef _SOC_STONEYRIDGE_ACPI_H_ -#define _SOC_STONEYRIDGE_ACPI_H_ +#ifndef __SOC_STONEYRIDGE_ACPI_H__ +#define __SOC_STONEYRIDGE_ACPI_H__ #include <arch/acpi.h> @@ -35,4 +35,4 @@ void southbridge_inject_dsdt(device_t device); -#endif /* _SOC_STONEYRIDGE_ACPI_H_ */ +#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index c43dd27..278bb34 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _STONEYRIDGE_GPIO_H_ -#define _STONEYRIDGE_GPIO_H_ +#ifndef __STONEYRIDGE_GPIO_H__ +#define __STONEYRIDGE_GPIO_H__ #include <soc/amd/common/amd_defs.h> #include <types.h> @@ -129,4 +129,4 @@ typedef uint32_t gpio_t; -#endif /* _STONEYRIDGE_GPIO_H_ */ +#endif /* __STONEYRIDGE_GPIO_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/imc.h b/src/soc/amd/stoneyridge/include/soc/imc.h index 3d0e740..f2aed2e 100644 --- a/src/soc/amd/stoneyridge/include/soc/imc.h +++ b/src/soc/amd/stoneyridge/include/soc/imc.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef STONEYRIDGE_IMC_H -#define STONEYRIDGE_IMC_H +#ifndef __STONEYRIDGE_IMC_H__ +#define __STONEYRIDGE_IMC_H__ #include <Porting.h> #include <AGESA.h> diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index e082a9d..13d7d36 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef PI_STONEYRIDGE_NORTHBRIDGE_H -#define PI_STONEYRIDGE_NORTHBRIDGE_H +#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ #include <arch/cpu.h> #include <arch/io.h> @@ -30,4 +30,4 @@ /* todo: remove this when postcar stage is in place */ asmlinkage void chipset_teardown_car(void); -#endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */ +#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index b28f386..4219fa3 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -21,8 +21,8 @@ * */ -#ifndef _SOC_STONEYRIDGE_NVS_H_ -#define _SOC_STONEYRIDGE_NVS_H_ +#ifndef __SOC_STONEYRIDGE_NVS_H__ +#define __SOC_STONEYRIDGE_NVS_H__ #include <stdint.h> #include <vendorcode/google/chromeos/gnvs.h> @@ -48,4 +48,4 @@ chromeos_acpi_t chromeos; } __attribute__((packed)) global_nvs_t; -#endif /* _SOC_STONEYRIDGE_NVS_H_ */ +#endif /* __SOC_STONEYRIDGE_NVS_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 8bea376..5c7f86a 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef _PI_STONEYRIDGE_PCI_DEVS_H_ -#define _PI_STONEYRIDGE_PCI_DEVS_H_ +#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ +#define __PI_STONEYRIDGE_PCI_DEVS_H__ #include <device/pci_def.h> #include <rules.h> @@ -285,4 +285,4 @@ #define SD_DEVID 0x7906 #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) -#endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */ +#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index c9b19e5..1379e19 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef STONEYRIDGE_SMBUS_H -#define STONEYRIDGE_SMBUS_H +#ifndef __STONEYRIDGE_SMBUS_H__ +#define __STONEYRIDGE_SMBUS_H__ #include <stdint.h> @@ -67,4 +67,4 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); -#endif /* STONEYRIDGE_SMBUS_H */ +#endif /* __STONEYRIDGE_SMBUS_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index 193fb0c..46004c9 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -5,8 +5,8 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ -#ifndef _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H -#define _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H +#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ #include <arch/io.h> @@ -62,4 +62,4 @@ void enable_smi_generation(void); #endif -#endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */ +#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index de481f0..20edf5f 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef STONEYRIDGE_H -#define STONEYRIDGE_H +#ifndef __STONEYRIDGE_H__ +#define __STONEYRIDGE_H__ #include <arch/io.h> #include <types.h> @@ -204,4 +204,4 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); void bootblock_fch_early_init(void); -#endif /* STONEYRIDGE_H */ +#endif /* __STONEYRIDGE_H__ */ -- To view, visit https://review.coreboot.org/21073 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4466df529ab201c922096a31d7438381778b582f Gerrit-Change-Number: 21073 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/intel/common/block: Add functions to common CPU library code
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21051 ) Change subject: soc/intel/common/block: Add functions to common CPU library code ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58777/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14143/ : SUCCESS -- To view, visit https://review.coreboot.org/21051 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id34eb7e03069656238ca0cbdf6ce33f116e0e413 Gerrit-Change-Number: 21051 Gerrit-PatchSet: 2 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 18:53:21 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: Rework receive enable calibration
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18692 ) Change subject: nb/intel/x4x/raminit: Rework receive enable calibration ...................................................................... Patch Set 24: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58776/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14142/ : SUCCESS -- To view, visit https://review.coreboot.org/18692 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d Gerrit-Change-Number: 18692 Gerrit-PatchSet: 24 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Thu, 17 Aug 2017 18:48:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/t430s: Enable libgfxinit
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21070 ) Change subject: mb/lenovo/t430s: Enable libgfxinit ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58775/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14141/ : SUCCESS -- To view, visit https://review.coreboot.org/21070 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifb1471ecb18927c30c61c64011cbb0e20a465558 Gerrit-Change-Number: 21070 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 18:35:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/gigabyte/ga-b75m-d3v: add libgfxinit support
by build bot (Jenkins) (Code Review) 17 Aug '17

17 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21071 ) Change subject: mb/gigabyte/ga-b75m-d3v: add libgfxinit support ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58774/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14140/ : SUCCESS -- To view, visit https://review.coreboot.org/21071 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib1513fc57b79eebc5d047c2e24585731c44bc215 Gerrit-Change-Number: 21071 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 17 Aug 2017 18:34:03 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017