coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/skylake: Enable power button SMI when jumping to payload
by Furquan Shaikh (Code Review) 18 Aug '17

18 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21082 to look at the new patch set (#3). Change subject: soc/intel/skylake: Enable power button SMI when jumping to payload ...................................................................... soc/intel/skylake: Enable power button SMI when jumping to payload Instead of enabling power button SMI unconditionally, add a boot state handler to enable power button SMI just before jumping to payload. This ensures that: 1. We do not respond to power button SMI until we know that coreboot is done. 2. On resume, there is no need to enable power button SMI. This avoids any power button presses during resume path from triggering a shutdown. BUG=b:64811381 Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/smi.c M src/soc/intel/skylake/smihandler.c 4 files changed, 32 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/21082/3 -- To view, visit https://review.coreboot.org/21082 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Gerrit-Change-Number: 21082 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Enable power button SMI when jumping to payload
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21082 ) Change subject: soc/intel/skylake: Enable power button SMI when jumping to payload ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58826/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/14186/ : SUCCESS -- To view, visit https://review.coreboot.org/21082 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Gerrit-Change-Number: 21082 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 04:34:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable power button SMI when jumping to payload
by Furquan Shaikh (Code Review) 18 Aug '17

18 Aug '17

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/21082 ) Change subject: soc/intel/skylake: Enable power button SMI when jumping to payload ...................................................................... soc/intel/skylake: Enable power button SMI when jumping to payload Instead of enabling power button SMI unconditionally, add a boot state handler to enable power button SMI just before jumping to payload. This ensures that: 1. We do not respond to power button SMI until we know that coreboot is done. 2. On resume, there is no need to enable power button SMI. This avoids any power button presses during resume path from triggering a shutdown. BUG=b:64811381 Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/smi.c M src/soc/intel/skylake/smihandler.c 4 files changed, 24 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/21082/2 -- To view, visit https://review.coreboot.org/21082 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Gerrit-Change-Number: 21082 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Enable power button SMI when jumping to payload
by Furquan Shaikh (Code Review) 18 Aug '17

18 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/21082 Change subject: soc/intel/skylake: Enable power button SMI when jumping to payload ...................................................................... soc/intel/skylake: Enable power button SMI when jumping to payload Instead of enabling power button SMI unconditionally, add a boot state handler to enable power button SMI just before jumping to payload. This ensures that: 1. We do not respond to power button SMI until we know that coreboot is done. 2. On resume, there is no need to enable power button SMI. This avoids any power button presses during resume path from triggering a shutdown. BUG=b:64811381 Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/smi.c M src/soc/intel/skylake/smihandler.c 4 files changed, 25 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/21082/1 diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 67b1f43..73e1e0e 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -160,6 +160,7 @@ uint16_t clear_pm1_status(void); void enable_pm1(uint16_t events); uint32_t clear_smi_status(void); +uint16_t read_pm1_enable(void); /* SMI */ void enable_smi(uint32_t mask); diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 9b38531..b3496c3 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -136,12 +136,22 @@ return print_pm1_status(reset_pm1_status()); } -/* Set the PM1 register to events */ +/* + * Enable supplied events in PM1_EN register. This does not disable any already + * set events. + */ void enable_pm1(u16 events) { - outw(events, ACPI_BASE_ADDRESS + PM1_EN); + u16 pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + pm1_en |= events; + outw(pm1_en, ACPI_BASE_ADDRESS + PM1_EN); } +/* Read events set in PM1_EN register. */ +uint16_t read_pm1_enable(void) +{ + return inw(ACPI_BASE_ADDRESS + PM1_EN); +} /* * SMI diff --git a/src/soc/intel/skylake/smi.c b/src/soc/intel/skylake/smi.c index 7343637..1c264f0 100644 --- a/src/soc/intel/skylake/smi.c +++ b/src/soc/intel/skylake/smi.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootstate.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> @@ -53,8 +54,9 @@ void southbridge_smm_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); + /* Configure events */ - enable_pm1(PWRBTN_EN | GBL_EN); + enable_pm1(GBL_EN); disable_gpe(PME_B0_EN); /* @@ -88,3 +90,10 @@ "d" (APM_CNT) ); } + +static void pm1_enable_pwrbtn_smi(void *unused) +{ + enable_pm1(PWRBTN_EN); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index d87994e..3e79065 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -343,12 +343,13 @@ static void southbridge_smi_pm1(void) { u16 pm1_sts = clear_pm1_status(); + u16 pm1_en = read_pm1_enable(); /* * While OSPM is not active, poweroff immediately on a power button * event. */ - if (pm1_sts & PWRBTN_STS) { + if ((pm1_sts & PWRBTN_STS) && (pm1_en & PWRBTN_EN)) { /* power button pressed */ if (IS_ENABLED(CONFIG_ELOG_GSMI)) elog_add_event(ELOG_TYPE_POWER_BUTTON); -- To view, visit https://review.coreboot.org/21082 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Gerrit-Change-Number: 21082 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: [wip]soc/intel/cannonlake: Add cpu.c and MP init support
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21081 ) Change subject: [wip]soc/intel/cannonlake: Add cpu.c and MP init support ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58825/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14185/ : SUCCESS -- To view, visit https://review.coreboot.org/21081 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Gerrit-Change-Number: 21081 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 04:15:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [wip]soc/intel/cannonlake: Add cpu.c and MP init support
by Pratikkumar V Prajapati (Code Review) 18 Aug '17

18 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21081 to look at the new patch set (#2). Change subject: [wip]soc/intel/cannonlake: Add cpu.c and MP init support ...................................................................... [wip]soc/intel/cannonlake: Add cpu.c and MP init support WIP. Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/ramstage.h 4 files changed, 297 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/21081/2 -- To view, visit https://review.coreboot.org/21081 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Gerrit-Change-Number: 21081 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [wip]soc/intel/cannonlake: Add cpu.c and MP init support
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21081 ) Change subject: [wip]soc/intel/cannonlake: Add cpu.c and MP init support ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58824/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14184/ : SUCCESS -- To view, visit https://review.coreboot.org/21081 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Gerrit-Change-Number: 21081 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 04:12:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [wip]soc/intel/cannonlake: Add cpu.c and MP init support
by Pratikkumar V Prajapati (Code Review) 18 Aug '17

18 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21081 Change subject: [wip]soc/intel/cannonlake: Add cpu.c and MP init support ...................................................................... [wip]soc/intel/cannonlake: Add cpu.c and MP init support WIP. Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.c A src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/ramstage.h 4 files changed, 297 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/21081/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a83eb0..414a8be 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -23,6 +23,7 @@ romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-y += chip.c +ramstage-y += cpu.c ramstage-y += gspi.c ramstage-y += memmap.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 62181a3..b9b1560 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -29,6 +29,11 @@ fsp_silicon_init(romstage_handoff_is_resume()); } +void soc_fsp_load(void) +{ + fsps_load(romstage_handoff_is_resume()); +} + static void pci_domain_set_resources(device_t dev) { assign_resources(dev->link_list); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c new file mode 100755 index 0000000..22cb7cd --- /dev/null +++ b/src/soc/intel/cannonlake/cpu.c @@ -0,0 +1,290 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <bootstate.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <chip.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/speedstep.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/name.h> +#include <cpu/x86/smm.h> +#include <delay.h> +#include <intelblocks/cpulib.h> +#include <intelblocks/fast_spi.h> +#include <intelblocks/mp_init.h> +#include <intelblocks/msr.h> +#include <intelblocks/sgx.h> +#include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> +#include <soc/cpu.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/ramstage.h> +#include <intelblocks/smm.h> +#include <soc/systemagent.h> + +#define EMULATE_DELAY_VALUE 0x13 +#define CTC_FREQ 19200000 + +static void configure_isst(void) +{ + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + msr_t msr; + + if (conf->speed_shift_enable) { + /* + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + * is supported or not. coreboot needs to configure MSR 0x1AA + * which is then reflected in the CPUID register. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } else { + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } +} + +static void configure_misc(void) +{ + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + if (conf->eist_enable) + cpu_enable_eist(); + else + cpu_disable_eist(); + wrmsr(IA32_MISC_ENABLE, msr); + + /* Disable Thermal interrupts */ + msr.lo = 0; + msr.hi = 0; + wrmsr(IA32_THERM_INTERRUPT, msr); + + /* Enable package critical interrupt only */ + msr.lo = 1 << 4; + msr.hi = 0; + wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); + + /* Enable PROCHOT */ + msr = rdmsr(MSR_POWER_CTL); + msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ + msr.lo |= (1 << 23); /* Lock it */ + wrmsr(MSR_POWER_CTL, msr); +} + +static void enable_lapic_tpr(void) +{ + msr_t msr; + + msr = rdmsr(MSR_PIC_MSG_CONTROL); + msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ + wrmsr(MSR_PIC_MSG_CONTROL, msr); +} + +static void configure_dca_cap(void) +{ + struct cpuid_result cpuid_regs; + msr_t msr; + + /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */ + cpuid_regs = cpuid(1); + if (cpuid_regs.ecx & (1 << 18)) { + msr = rdmsr(IA32_PLATFORM_DCA_CAP); + msr.lo |= 1; + wrmsr(IA32_PLATFORM_DCA_CAP, msr); + } +} + +static void set_energy_perf_bias(u8 policy) +{ + msr_t msr; + int ecx; + + /* Determine if energy efficient policy is supported. */ + ecx = cpuid_ecx(0x6); + if (!(ecx & (1 << 3))) + return; + + /* Energy Policy is bits 3:0 */ + msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS); + msr.lo &= ~0xf; + msr.lo |= policy & 0xf; + wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr); +} + +static void configure_mca(void) +{ + msr_t msr; + int i; + int num_banks; + + msr = rdmsr(IA32_MCG_CAP); + num_banks = msr.lo & 0xff; + msr.lo = msr.hi = 0; + /* + * TODO(adurbin): This should only be done on a cold boot. Also, some + * of these banks are core vs package scope. For now every CPU clears + * every bank. + */ + for (i = 0; i < num_banks; i++) { + /* Clear the machine check status */ + wrmsr(IA32_MC0_STATUS + (i * 4), msr); + /* Initialize machine checks */ + wrmsr(IA32_MC0_CTL + i * 4, + (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); + } +} + +static void configure_c_states(void) +{ + msr_t msr; + + /* C-state Interrupt Response Latency Control 0 - package C3 latency */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); + + /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); + + /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); + + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); +} + +/* All CPUs including BSP will run the following function. */ +void soc_core_init(device_t cpu, const void *microcode) +{ + + /* Clear out pending MCEs */ + configure_mca(); + + /* Enable the local CPU apics */ + enable_lapic_tpr(); + setup_lapic(); + + /* Configure c-state interrupt response time */ + configure_c_states(); + + /* Configure Enhanced SpeedStep and Thermal Sensors */ + configure_misc(); + + /* Configure Intel Speed Shift */ + configure_isst(); + + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + + /* Enable Turbo */ + enable_turbo(); + +} + +static int adjust_apic_id(int index, int apic_id) +{ + unsigned int num_cores, num_threads; + + if (cpu_read_topology(&num_cores, &num_threads)) + return 2 * index; + else + return index; +} + +static void post_mp_init(void) +{ + /* Set Max Ratio */ + cpu_set_max_ratio(); + + /* + * Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. + */ + //southbridge_smm_enable_smi(); + + /* Lock down the SMRAM space. */ +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + smm_lock(); +#endif +} + + +static const struct mp_ops mp_ops = { + /* + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + */ + .pre_mp_init = soc_fsp_load, + .get_cpu_count = get_cpu_count, + .get_microcode_info = get_microcode_info, + .adjust_cpu_apic_entry = adjust_apic_id, + .post_mp_init = post_mp_init, +}; + +void soc_init_cpus(struct bus *cpu_bus, const void *microcode) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure."); + +} + diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h index 4a96185..29ad9d2 100644 --- a/src/soc/intel/cannonlake/include/soc/ramstage.h +++ b/src/soc/intel/cannonlake/include/soc/ramstage.h @@ -24,5 +24,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params); void soc_init_pre_device(void *chip_info); +void soc_fsp_load(void); #endif -- To view, visit https://review.coreboot.org/21081 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d Gerrit-Change-Number: 21081 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/inte/cannonlake: Define soc_intel_cannonlake_config
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21080 ) Change subject: soc/inte/cannonlake: Define soc_intel_cannonlake_config ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58823/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/14183/ : SUCCESS -- To view, visit https://review.coreboot.org/21080 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2a6e737594da1e766b157a38942e19a4f7fb9dfa Gerrit-Change-Number: 21080 Gerrit-PatchSet: 3 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 03:58:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/padmelon: Fixes to enable power button
by build bot (Jenkins) (Code Review) 18 Aug '17

18 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21048 ) Change subject: amd/padmelon: Fixes to enable power button ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58822/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14182/ : SUCCESS -- To view, visit https://review.coreboot.org/21048 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I104a6d3cabc15f0a61d6197d6aeb5189ce2e483b Gerrit-Change-Number: 21048 Gerrit-PatchSet: 5 Gerrit-Owner: John E. Kabat <sljkrr(a)gmail.com> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 18 Aug 2017 03:39:15 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017