coreboot-gerrit July 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: libpayload: video: Add support for font scaling with a factor
by build bot (Jenkins) (Code Review) 30 Jul '17

30 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20709 ) Change subject: libpayload: video: Add support for font scaling with a factor ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58042/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13477/ : SUCCESS -- To view, visit https://review.coreboot.org/20709 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029 Gerrit-Change-Number: 20709 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Ben Gardner <gardner.ben(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Stuge <peter(a)stuge.se> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jul 2017 12:54:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo: add Lenovo ThinkPad X131e (Intel)
by build bot (Jenkins) (Code Review) 30 Jul '17

30 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20694 ) Change subject: mb/lenovo: add Lenovo ThinkPad X131e (Intel) ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58037/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13472/ : SUCCESS -- To view, visit https://review.coreboot.org/20694 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872 Gerrit-Change-Number: 20694 Gerrit-PatchSet: 7 Gerrit-Owner: James Ye <jye836(a)gmail.com> Gerrit-Reviewer: James Ye <jye836(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jul 2017 05:16:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add Cannonlake pci ids for common
by build bot (Jenkins) (Code Review) 30 Jul '17

30 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20823 ) Change subject: soc/intel/common: Add Cannonlake pci ids for common ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58036/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13471/ : SUCCESS -- To view, visit https://review.coreboot.org/20823 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Gerrit-Change-Number: 20823 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jul 2017 00:17:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add Cannonlake pci ids for common
by Lijian Zhao (Code Review) 30 Jul '17

30 Jul '17

Hello Brandon Breitenstein, Subrata Banik, Bora Guvendik, build bot (Jenkins), Hannah Williams, Shaunak Saha, I'd like you to reexamine a change. Please visit https://review.coreboot.org/20823 to look at the new patch set (#2). Change subject: soc/intel/common: Add Cannonlake pci ids for common ...................................................................... soc/intel/common: Add Cannonlake pci ids for common Add Cannonlake pci device ids for all the merged intel common code.As of now only have CNL-U and CNL-Y pci ids. Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 9 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/20823/2 -- To view, visit https://review.coreboot.org/20823 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Gerrit-Change-Number: 20823 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in libgfxinit[master]: gma hsw+: Treat DDI E and PCH DAC disabling separately
by Nico Huber (Code Review) 30 Jul '17

30 Jul '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/20822 ) Change subject: gma hsw+: Treat DDI E and PCH DAC disabling separately ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/20822 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I603ecd29c48af43bc21acaadbedaeae451acbcf3 Gerrit-Change-Number: 20822 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sun, 30 Jul 2017 00:02:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add Cannonlake pci ids for common
by build bot (Jenkins) (Code Review) 30 Jul '17

30 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20823 ) Change subject: soc/intel/common: Add Cannonlake pci ids for common ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58035/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13470/ : SUCCESS -- To view, visit https://review.coreboot.org/20823 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Gerrit-Change-Number: 20823 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jul 2017 00:01:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add Cannonlake pci ids for common
by Lijian Zhao (Code Review) 30 Jul '17

30 Jul '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20823 Change subject: soc/intel/common: Add Cannonlake pci ids for common ...................................................................... soc/intel/common: Add Cannonlake pci ids for common Add Cannonlake pci device ids for all the merged intel common code.As of now only have CNL-U and CNL-Y pci ids. Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/scs/sd.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 9 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/20823/1 diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 6debe88..f4b1e8c 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -179,6 +179,12 @@ PCI_DEVICE_ID_INTEL_APL_I2C5, PCI_DEVICE_ID_INTEL_APL_I2C6, PCI_DEVICE_ID_INTEL_APL_I2C7, + PCI_DEVICE_ID_INTEL_CNL_I2C0, + PCI_DEVICE_ID_INTEL_CNL_I2C1, + PCI_DEVICE_ID_INTEL_CNL_I2C2, + PCI_DEVICE_ID_INTEL_CNL_I2C3, + PCI_DEVICE_ID_INTEL_CNL_I2C4, + PCI_DEVICE_ID_INTEL_CNL_I2C5, PCI_DEVICE_ID_INTEL_GLK_I2C0, PCI_DEVICE_ID_INTEL_GLK_I2C1, PCI_DEVICE_ID_INTEL_GLK_I2C2, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index dfc92fe..19133f0 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -139,6 +139,22 @@ PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23, PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, + PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, 0 }; diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index f027486..d1f964e 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -64,6 +64,9 @@ PCI_DEVICE_ID_INTEL_SPT_U_SATA, PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_SPT_KBL_SATA, + PCI_DEVICE_ID_INTEL_CNL_SATA, + PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_CNL_COMPACT_SATA, 0 }; diff --git a/src/soc/intel/common/block/scs/sd.c b/src/soc/intel/common/block/scs/sd.c index ec5f6e8..d6f4843 100644 --- a/src/soc/intel/common/block/scs/sd.c +++ b/src/soc/intel/common/block/scs/sd.c @@ -65,6 +65,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_APL_SD, + PCI_DEVICE_ID_INTEL_CNL_SD, PCI_DEVICE_ID_INTEL_GLK_SD, PCI_DEVICE_ID_INTEL_SKL_SD, 0 diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index cd066ac..8ee38ee 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -89,6 +89,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CNL_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, 0 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index f2e74cc..206f4a0 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -289,6 +289,8 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_GLK_NB, PCI_DEVICE_ID_INTEL_APL_NB, + PCI_DEVICE_ID_INTEL_CNL_ID_U, + PCI_DEVICE_ID_INTEL_CNL_ID_Y, PCI_DEVICE_ID_INTEL_SKL_ID_U, PCI_DEVICE_ID_INTEL_SKL_ID_Y, PCI_DEVICE_ID_INTEL_SKL_ID_ULX, diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 632fb95..e8f1bc8 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -60,6 +60,9 @@ PCI_DEVICE_ID_INTEL_APL_UART1, PCI_DEVICE_ID_INTEL_APL_UART2, PCI_DEVICE_ID_INTEL_APL_UART3, + PCI_DEVICE_ID_INTEL_CNL_UART0, + PCI_DEVICE_ID_INTEL_CNL_UART1, + PCI_DEVICE_ID_INTEL_CNL_UART2, PCI_DEVICE_ID_INTEL_GLK_UART0, PCI_DEVICE_ID_INTEL_GLK_UART1, PCI_DEVICE_ID_INTEL_GLK_UART2, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index c5d4e00..7b74b21 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -31,6 +31,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_APL_XDCI, + PCI_DEVICE_ID_INTEL_CNL_LP_XDCI, PCI_DEVICE_ID_INTEL_GLK_XDCI, PCI_DEVICE_ID_INTEL_SPT_LP_XDCI, 0 diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 50fe1de..ac7bd58 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -31,6 +31,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_APL_XHCI, + PCI_DEVICE_ID_INTEL_CNL_LP_XHCI, PCI_DEVICE_ID_INTEL_GLK_XHCI, PCI_DEVICE_ID_INTEL_SPT_LP_XHCI, PCI_DEVICE_ID_INTEL_KBP_H_XHCI, -- To view, visit https://review.coreboot.org/20823 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Gerrit-Change-Number: 20823 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in libgfxinit[master]: gma hsw+: Don't use DDI E if DDI A uses all lanes
by Nico Huber (Code Review) 30 Jul '17

30 Jul '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/20821 ) Change subject: gma hsw+: Don't use DDI E if DDI A uses all lanes ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/20821 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I94e9537c9f30d0cbf757b816f38d44e1b43805b3 Gerrit-Change-Number: 20821 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 29 Jul 2017 23:55:23 +0000 Gerrit-HasComments: No

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Change in libgfxinit[master]: gma hsw+: Revise Has_DDI_D flag
by Nico Huber (Code Review) 30 Jul '17

30 Jul '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/20820 ) Change subject: gma hsw+: Revise Has_DDI_D flag ...................................................................... Patch Set 1: Verified+1 -- To view, visit https://review.coreboot.org/20820 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I84c40b6bc01091de8a512e21354243c74643e0f5 Gerrit-Change-Number: 20820 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 29 Jul 2017 23:50:04 +0000 Gerrit-HasComments: No

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Change in libgfxinit[master]: gma hsw+: Treat DDI E and PCH DAC disabling separately
by Nico Huber (Code Review) 30 Jul '17

30 Jul '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/20822 Change subject: gma hsw+: Treat DDI E and PCH DAC disabling separately ...................................................................... gma hsw+: Treat DDI E and PCH DAC disabling separately We only use DDI E for analog VGA outputs through the PCH DAC. DDI E might be configured differently, though, by a previously running dri- ver, so we have to treat the two entities seperately on the All_Off() path. Change-Id: I603ecd29c48af43bc21acaadbedaeae451acbcf3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/haswell_shared/hw-gfx-gma-connectors-ddi.adb M common/haswell_shared/hw-gfx-gma-connectors.adb M common/haswell_shared/hw-gfx-gma-port_detect.adb M common/hw-gfx-gma-config.ads.template 4 files changed, 10 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/22/20822/1 diff --git a/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb b/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb index 4440376..a93f3ec 100644 --- a/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb +++ b/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb @@ -559,7 +559,7 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - if Port = DIGI_E then + if Config.Has_PCH_DAC and then Port = DIGI_E then PCH.VGA.Off; PCH.Transcoder.Off (PCH.FDI_A); -- PCH.VGA.Clock_Off; -- Can't tell what Linux does, if anything. @@ -570,7 +570,9 @@ if Port = DIGI_E then SPLL.Off; - PCH.FDI.Off (PCH.FDI_A, PCH.FDI.Clock_Off); + if Config.Has_PCH_DAC then + PCH.FDI.Off (PCH.FDI_A, PCH.FDI.Clock_Off); + end if; end if; end Off; diff --git a/common/haswell_shared/hw-gfx-gma-connectors.adb b/common/haswell_shared/hw-gfx-gma-connectors.adb index 734b11a..6a8227c 100644 --- a/common/haswell_shared/hw-gfx-gma-connectors.adb +++ b/common/haswell_shared/hw-gfx-gma-connectors.adb @@ -86,9 +86,6 @@ for Port in Digital_Port range DIGI_A .. Config.Last_Digital_Port loop DDI.Off (Port); end loop; - if Config.Is_FDI_Port (Analog) then - DDI.Off (DIGI_E); - end if; end Post_All_Off; end HW.GFX.GMA.Connectors; diff --git a/common/haswell_shared/hw-gfx-gma-port_detect.adb b/common/haswell_shared/hw-gfx-gma-port_detect.adb index 1302cf0..be83bd5 100644 --- a/common/haswell_shared/hw-gfx-gma-port_detect.adb +++ b/common/haswell_shared/hw-gfx-gma-port_detect.adb @@ -124,7 +124,9 @@ Config.Valid_Port (Internal) := Internal_Detected; -- DDI_[BCD] - for Port in Ext_Digital_Port range DIGI_B .. Config.Last_Digital_Port loop + for Port in Ext_Digital_Port range + DIGI_B .. Ext_Digital_Port'Min (DIGI_D, Config.Last_Digital_Port) + loop if Config.Has_Presence_Straps then Registers.Is_Set_Mask (Register => Registers.SFUSE_STRAP, diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 55696c7..5b51941 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -172,7 +172,7 @@ Valid_Port : Valid_Per_Port renames Valid_Port_GPU (CPU); Last_Digital_Port : constant Digital_Port := - (if Has_DDI_D then DIGI_D else DIGI_C); + (if Has_DDI_E then DIGI_E else DIGI_C); ---------------------------------------------------------------------------- @@ -182,11 +182,8 @@ when Ironlake .. Ivybridge => FDI_Per_Port' (Internal => Internal_Display = LVDS, others => True), - when Haswell => FDI_Per_Port' - (Analog => True, - others => False), - when Broadwell => FDI_Per_Port' - (Analog => CPU_Var = Normal, + when Haswell .. Broadwell => FDI_Per_Port' + (Analog => Has_PCH_DAC, others => False), when others => FDI_Per_Port' (others => False)); -- To view, visit https://review.coreboot.org/20822 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I603ecd29c48af43bc21acaadbedaeae451acbcf3 Gerrit-Change-Number: 20822 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit July 2017