July 2017 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: google/gru: Use 1.8V powerdomain for gpio4cd on Scarlet

by build bot (Jenkins) (Code Review)

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20802 ) Change subject: google/gru: Use 1.8V powerdomain for gpio4cd on Scarlet ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58052/ : SUCCESS -- To view, visit https://review.coreboot.org/20802 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc Gerrit-Change-Number: 20802 Gerrit-PatchSet: 3 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 31 Jul 2017 07:31:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/gru: Correct Scarlet pwm regulator minimum value and maximum v...

by Lin Huang (Code Review)

Lin Huang has uploaded this change for review. ( https://review.coreboot.org/20831 Change subject: google/gru: Correct Scarlet pwm regulator minimum value and maximum value ...................................................................... google/gru: Correct Scarlet pwm regulator minimum value and maximum value In Scarlet pwm regulatoror minimum value and maximum value differs from other board variants, Correct it so we can get the right voltage. Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a Signed-off-by: Lin Huang <hl(a)rock-chips.com> --- M src/mainboard/google/gru/pwm_regulator.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/20831/1 diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index 696f09a..729c1fe 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -47,6 +47,12 @@ [PWM_REGULATOR_CENTERLOG] = {7994, 10499} }; +int scarlet_pwm_design_voltage[][2] = { + [PWM_REGULATOR_GPU] = {7996, 10990}, + [PWM_REGULATOR_BIG] = {8000, 12992}, + [PWM_REGULATOR_LIT] = {8021, 11996}, +}; + int pwm_enum_to_pwm_number[] = { [PWM_REGULATOR_GPU] = 0, [PWM_REGULATOR_LIT] = 2, @@ -74,6 +80,9 @@ } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() >= 6) { voltage_min = kevin6_pwm_design_voltage[pwm][0]; voltage_max = kevin6_pwm_design_voltage[pwm][1]; + } else if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) { + voltage_min = scarlet_pwm_design_voltage[pwm][0]; + voltage_max = scarlet_pwm_design_voltage[pwm][1]; } assert(voltage <= voltage_max && voltage >= voltage_min); -- To view, visit https://review.coreboot.org/20831 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a Gerrit-Change-Number: 20831 Gerrit-PatchSet: 1 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com>

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Change in coreboot[master]: soc/intel/apollolake: Skip disabled IGD device

by build bot (Jenkins) (Code Review)

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20830 ) Change subject: soc/intel/apollolake: Skip disabled IGD device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58047/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13481/ : SUCCESS -- To view, visit https://review.coreboot.org/20830 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8 Gerrit-Change-Number: 20830 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 31 Jul 2017 05:30:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Skip disabled IGD device

by build bot (Jenkins) (Code Review)

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20829 ) Change subject: soc/intel/skylake: Skip disabled IGD device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58046/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13480/ : SUCCESS -- To view, visit https://review.coreboot.org/20829 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf Gerrit-Change-Number: 20829 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 31 Jul 2017 05:25:21 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Skip disabled IGD device

by Subrata Banik (Code Review)

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20830 Change subject: soc/intel/apollolake: Skip disabled IGD device ...................................................................... soc/intel/apollolake: Skip disabled IGD device If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/graphics.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/20830/1 diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index c873825..90859d5 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -27,7 +27,13 @@ uintptr_t fsp_soc_get_igd_bar(void) { - return find_resource(SA_DEV_IGD, PCI_BASE_ADDRESS_2)->base; + device_t dev = SA_DEV_IGD; + + /* Check if IGD PCI device is disabled */ + if (!dev->enabled) + return 0; + + return find_resource(dev, PCI_BASE_ADDRESS_2)->base; } static void igd_set_resources(struct device *dev) -- To view, visit https://review.coreboot.org/20830 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8 Gerrit-Change-Number: 20830 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

2 years, 10 months

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Change in coreboot[master]: soc/intel/skylake: Skip disabled IGD device

by Subrata Banik (Code Review)

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20829 Change subject: soc/intel/skylake: Skip disabled IGD device ...................................................................... soc/intel/skylake: Skip disabled IGD device If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/igd.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/20829/1 diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index dbcbd4d..62bcf42 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -36,7 +36,13 @@ uintptr_t fsp_soc_get_igd_bar(void) { - return find_resource(SA_DEV_IGD, PCI_BASE_ADDRESS_2)->base; + device_t dev = SA_DEV_IGD; + + /* Check if IGD PCI device is disabled */ + if (!dev->enabled) + return 0; + + return find_resource(dev, PCI_BASE_ADDRESS_2)->base; } u32 map_oprom_vendev(u32 vendev) -- To view, visit https://review.coreboot.org/20829 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf Gerrit-Change-Number: 20829 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

2 years, 10 months

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Change in coreboot[master]: soc/intel/cannonlake: Sort Kconfig for Cannonlake

by build bot (Jenkins) (Code Review)

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20828 ) Change subject: soc/intel/cannonlake: Sort Kconfig for Cannonlake ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58045/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13479/ : SUCCESS -- To view, visit https://review.coreboot.org/20828 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70 Gerrit-Change-Number: 20828 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jul 2017 23:01:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Sort Kconfig for Cannonlake

by Lijian Zhao (Code Review)

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20828 Change subject: soc/intel/cannonlake: Sort Kconfig for Cannonlake ...................................................................... soc/intel/cannonlake: Sort Kconfig for Cannonlake Look and feel update, sort the sequence in Kconfig. Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/20828/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 1c0f1bf..471fe6c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -8,37 +8,37 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 - select SOC_INTEL_COMMON_BLOCK_TIMER - select HAVE_MONOTONIC_TIMER - select TSC_CONSTANT_RATE - select TSC_MONOTONIC_TIMER - select UDELAY_TSC - select REG_SCRIPT + select ARCH_VERSTAGE_X86_32 select C_ENVIRONMENT_BOOTBLOCK select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE + select HAVE_MONOTONIC_TIMER select INTEL_CAR_NEM_ENHANCED select PLATFORM_USES_FSP2_0 + select REG_SCRIPT select RELOCATABLE_RAMSTAGE select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CPU - select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_LPSS - select SOC_INTEL_COMMON_BLOCK_UART - select SOC_INTEL_COMMON_BLOCK_FAST_SPI - select SOC_INTEL_COMMON_BLOCK_PCR - select SOC_INTEL_COMMON_BLOCK_SMBUS - select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_CSE + select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO + select SOC_INTEL_COMMON_BLOCK_LPSS + select SOC_INTEL_COMMON_BLOCK_PCR + select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_TIMER + select SOC_INTEL_COMMON_BLOCK_UART + select SOC_INTEL_COMMON_RESET select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select UDELAY_TSC config UART_DEBUG bool "Enable UART debug port." -- To view, visit https://review.coreboot.org/20828 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70 Gerrit-Change-Number: 20828 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Add Cannonlake pci ids for common

by build bot (Jenkins) (Code Review)

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20823 ) Change subject: soc/intel/common: Add Cannonlake pci ids for common ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58044/ : SUCCESS -- To view, visit https://review.coreboot.org/20823 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c Gerrit-Change-Number: 20823 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jul 2017 22:50:51 +0000 Gerrit-HasComments: No

2 years, 10 months

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Change in coreboot[master]: libpayload: video: Introduce helpers for font access

by build bot (Jenkins) (Code Review)

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20708 ) Change subject: libpayload: video: Introduce helpers for font access ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58043/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13478/ : SUCCESS -- To view, visit https://review.coreboot.org/20708 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0277984ec01f49dc51bfc8237ef806f13e3547e2 Gerrit-Change-Number: 20708 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Stuge <peter(a)stuge.se> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 30 Jul 2017 13:07:46 +0000 Gerrit-HasComments: No

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coreboot-gerrit July 2017