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Change in coreboot[master]: drvs/lenovo/hybrid_graphics: Switch to new hybrid driver
by Patrick Rudolph (Code Review) 27 Jul '17

27 Jul '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20794 Change subject: drvs/lenovo/hybrid_graphics: Switch to new hybrid driver ...................................................................... drvs/lenovo/hybrid_graphics: Switch to new hybrid driver Get rid of old hybrid graphics driver and use the new one. Disable IGD and PEG in early romstage and remove the PCI based driver. Add GPIO configuration in devicetree. Needs test on all devices. Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/lenovo/Kconfig M src/drivers/lenovo/Makefile.inc D src/drivers/lenovo/hybrid_graphics.c M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/t530/romstage.c 13 files changed, 220 insertions(+), 131 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/20794/1 diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index 38b86da..f20f3b2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,15 +27,3 @@ endchoice endif - -config DRIVERS_LENOVO_HYBRID_GRAPHICS - bool - default n - -config HYBRID_GRAPHICS_GPIO_NUM - depends on DRIVERS_LENOVO_HYBRID_GRAPHICS - int - default 52 - help - Set a default GPIO that sets the panel LVDS signal routing to - integrated or discrete GPU. diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index 66f8594..c50db5b 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1,2 +1 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c -ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c deleted file mode 100644 index 802823a..0000000 --- a/src/drivers/lenovo/hybrid_graphics.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Patrick Rudolph - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <types.h> -#include <string.h> -#include <option.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include <device/pci.h> -#include <console/console.h> -#include <southbridge/intel/common/gpio.h> - -/* Hybrid graphics allows to connect LVDS interface to either iGPU - * or dGPU depending on GPIO level. - * Nvidia is calling this functionality "muxed Optimus". - * Some devices, like T430s, only support "muxless Optimus" where the - * Intel GPU is always connected to the panel. - * As it is only linked on lenovo and only executed if the GPU exists - * we know for sure that the dGPU is there and connected to first PEG slot. - * - * Note: Once native gfx init is done for AMD or Nvida graphic - * cards, merge this code. - */ - -#define HYBRID_GRAPHICS_INTEGRATED 0 -#define HYBRID_GRAPHICS_DISCRETE 1 - -static void hybrid_graphics_disable_peg(struct device *dev) -{ - struct device *peg_dev; - - /* connect LVDS interface to iGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); - printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); - dev->enabled = 0; - - /* Disable PEG10 */ - peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); - if (peg_dev) - peg_dev->enabled = 0; - - printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n"); -} - -/* Called before VGA enable bits are set and only if dGPU - * is present. Enable/disable VGA devices here. */ -static void hybrid_graphics_enable_peg(struct device *dev) -{ - u8 hybrid_graphics_mode; - - hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; - get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); - - if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { - /* connect LVDS interface to dGPU */ - set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); - printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); - dev->enabled = 1; - - /* Disable IGD */ - dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - if (dev && dev->ops->disable) - dev->ops->disable(dev); - dev->enabled = 0; - - printk(BIOS_DEBUG, "Hybrid graphics: Disabled IGD.\n"); - } else - hybrid_graphics_disable_peg(dev); -} - -static struct pci_operations pci_dev_ops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; - -struct device_operations hybrid_graphics_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .scan_bus = 0, - .enable = hybrid_graphics_enable_peg, - .disable = hybrid_graphics_disable_peg, - .ops_pci = &pci_dev_ops_pci, -}; - -static const unsigned short pci_device_ids_nvidia[] = { - 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ - 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ - 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ - 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ - 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ - 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ - 0 }; - -static const struct pci_driver hybrid_peg_nvidia __pci_driver = { - .ops = &hybrid_graphics_ops, - .vendor = PCI_VENDOR_ID_NVIDIA, - .devices = pci_device_ids_nvidia, -}; diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index deb62b7..7d41204 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -162,6 +162,17 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "52" + register "panel_integrated_lvl" = "1" + + register "has_backlight_gpio" = "0" + end end # LPC Controller device pci 1f.2 on subsystemid 0x17aa 0x21ce diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index 94b8d62..f08ca03 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -18,6 +18,37 @@ #include <arch/io.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <device/device.h> +#include <device/pci.h> + +static void hybrid_graphics_init(void) +{ + struct device *dev; + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(dev, DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + + pci_write_config32(dev, DEVEN, reg32); + + /* TODO: Toggle GPU power */ +} void pch_enable_lpc(void) { @@ -65,6 +96,7 @@ void mainboard_early_init(int s3resume) { + hybrid_graphics_init(); } void mainboard_config_superio(void) diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 3224322..b0ed992 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -154,6 +154,17 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "52" + register "panel_integrated_lvl" = "1" + + register "has_backlight_gpio" = "0" + end end # LPC Controller device pci 1f.2 on subsystemid 0x17aa 0x21d2 diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index d7f1c23..207abc6 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -17,10 +17,40 @@ #include <arch/byteorder.h> #include <arch/io.h> -#include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <device/device.h> +#include <device/pci.h> + +static void hybrid_graphics_init(void) +{ + struct device *dev; + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(dev, DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + + pci_write_config32(dev, DEVEN, reg32); + + /* TODO: Toggle GPU power */ +} void pch_enable_lpc(void) { @@ -65,7 +95,9 @@ read_spd(&spd[2], 0x51, id_only); } -void mainboard_early_init(int s3resume) { +void mainboard_early_init(int s3resume) +{ + hybrid_graphics_init(); } void mainboard_config_superio(void) diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 0a121b7..d43c0c9 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -150,6 +150,17 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "52" + register "panel_integrated_lvl" = "1" + + register "has_backlight_gpio" = "0" + end end device pci 1f.2 on # SATA Controller 1 subsystemid 0x17aa 0x21f3 diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c index eb2d29e..c1be93c 100644 --- a/src/mainboard/lenovo/t430/romstage.c +++ b/src/mainboard/lenovo/t430/romstage.c @@ -18,6 +18,37 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/lenovo/pmh7/pmh7.h> +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <device/device.h> +#include <device/pci.h> + +static void hybrid_graphics_init(void) +{ + struct device *dev; + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(dev, DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + + pci_write_config32(dev, DEVEN, reg32); + + /* TODO: Toggle GPU power */ +} void pch_enable_lpc(void) { @@ -57,6 +88,7 @@ void mainboard_early_init(int s3resume) { + hybrid_graphics_init(); } void mainboard_config_superio(void) diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 0065799..11f7b51 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -133,6 +133,17 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "52" + register "panel_integrated_lvl" = "1" + + register "has_backlight_gpio" = "0" + end end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on # SMBUS controller diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index f84bc0d..154423e 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -35,6 +35,36 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> +#include <device/device.h> +#include <device/pci.h> + +static void hybrid_graphics_init(void) +{ + struct device *dev; + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(dev, DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + + pci_write_config32(dev, DEVEN, reg32); + + /* TODO: Toggle GPU power */ +} void pch_enable_lpc(void) { @@ -79,7 +109,9 @@ read_spd (&spd[2], 0x51, id_only); } -void mainboard_early_init(int s3resume) { +void mainboard_early_init(int s3resume) +{ + hybrid_graphics_init(); } void mainboard_config_superio(void) diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 2047a78..1ba060b 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -140,6 +140,17 @@ register "eventd_enable" = "0xff" register "evente_enable" = "0x0d" end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "52" + register "panel_integrated_lvl" = "1" + + register "has_backlight_gpio" = "0" + end end # LPC bridge device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 on diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index c454ec7..d1b7ec1 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -22,6 +22,37 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> +#include <device/device.h> +#include <device/pci.h> + +static void hybrid_graphics_init(void) +{ + struct device *dev; + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(dev, DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + + pci_write_config32(dev, DEVEN, reg32); + + /* TODO: Toggle GPU power */ +} void pch_enable_lpc(void) { @@ -66,7 +97,9 @@ read_spd (&spd[2], 0x51, id_only); } -void mainboard_early_init(int s3resume) { +void mainboard_early_init(int s3resume) +{ + hybrid_graphics_init(); } void mainboard_config_superio(void) -- To view, visit https://review.coreboot.org/20794 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73 Gerrit-Change-Number: 20794 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/lenovo/t400: Switch to new hybrid graphics driver
by Patrick Rudolph (Code Review) 27 Jul '17

27 Jul '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20793 Change subject: mb/lenovo/t400: Switch to new hybrid graphics driver ...................................................................... mb/lenovo/t400: Switch to new hybrid graphics driver Use new hybrid graphics driver to get device state. Move remaining code to romstage.c. Tested on Lenovo T500: * Linux 4.11.4 on Fedora 25 * Integrated (using NGI) * Discrete (using VGA OpROM) * Switchable (using NGI and VGA OpROM), tested with DRI_PRIME No regressions found. Change-Id: Iad2eccaab19c71f11308853ba9326d8186e67c93 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/lenovo/hybrid_graphics.c M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t400/Makefile.inc M src/mainboard/lenovo/t400/devicetree.cb D src/mainboard/lenovo/t400/hybrid_graphics.c M src/mainboard/lenovo/t400/romstage.c 6 files changed, 29 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/20793/1 diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c index 9b46646..802823a 100644 --- a/src/drivers/lenovo/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -112,14 +112,3 @@ .vendor = PCI_VENDOR_ID_NVIDIA, .devices = pci_device_ids_nvidia, }; - -static const unsigned short pci_device_ids_amd[] = { - 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ - 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ - 0 }; - -static const struct pci_driver hybrid_peg_amd __pci_driver = { - .ops = &hybrid_graphics_ops, - .vendor = PCI_VENDOR_ID_ATI, - .devices = pci_device_ids_amd, -}; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index decbab7f..8eb5fc5 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -21,6 +21,7 @@ select INTEL_INT15 select SUPERIO_NSC_PC87382 select SUPERIO_NSC_PC87384 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index 8ac61bb..c2c82b6 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -17,5 +17,4 @@ ramstage-y += dock.c ramstage-y += cstates.c -romstage-y += hybrid_graphics.c ramstage-y += blc.c diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 1adba8b..02a9e72 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -206,6 +206,19 @@ end end + chip drivers/lenovo/hybrid_graphics + device pnp ff.f on end # dummy + + register "detect_gpio" = "21" + + register "has_panel_hybrid_gpio" = "1" + register "panel_hybrid_gpio" = "22" + register "panel_integrated_lvl" = "0" + + register "has_backlight_gpio" = "1" + register "backlight_gpio" = "19" + register "backlight_integrated_lvl" = "0" + end end device pci 1f.2 on # SATA/IDE 1 subsystemid 0x17aa 0x20f8 diff --git a/src/mainboard/lenovo/t400/hybrid_graphics.c b/src/mainboard/lenovo/t400/hybrid_graphics.c deleted file mode 100644 index b313ffa..0000000 --- a/src/mainboard/lenovo/t400/hybrid_graphics.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <stdint.h> -#include <string.h> -#include <southbridge/intel/common/gpio.h> -#include <northbridge/intel/gm45/gm45.h> -#include <console/console.h> -#include <option.h> - -#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 -#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 -#define HYBRID_GRAPHICS_SWITCHABLE 2 - -#define MUX_GPIO 22 -#define BCL_CTL_GPIO 19 -#define GFX_PWR_EN_GPIO 49 - -#define HYBRID_DETECT_GPIO 21 - -void hybrid_graphics_init(sysinfo_t *sysinfo); - -static bool hybrid_graphics_installed(void) -{ - if (get_gpio(HYBRID_DETECT_GPIO)) - return false; - else - return true; -} - -void hybrid_graphics_init(sysinfo_t *sysinfo) -{ - /* Set default mode */ - uint8_t hybrid_graphics_mode = - HYBRID_GRAPHICS_INTEGRATED_ONLY; - - if (!hybrid_graphics_installed()) { - printk(BIOS_DEBUG, "Hybrid graphics not installed.\n"); - /* The display is not connected to a mux or switchable. */ - sysinfo->enable_igd = 1; - sysinfo->enable_peg = 0; - return; - } - - printk(BIOS_DEBUG, "Hybrid graphics available: "); - get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); - - /* Select appropriate hybrid graphics device */ - switch (hybrid_graphics_mode) { - default: - case HYBRID_GRAPHICS_INTEGRATED_ONLY: - printk(BIOS_DEBUG, "Activating Integrated Only.\n"); - set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); - set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); - set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_LOW); - - sysinfo->enable_igd = 1; - sysinfo->enable_peg = 0; - break; - case HYBRID_GRAPHICS_DISCRETE_ONLY: - printk(BIOS_DEBUG, "Activating Discrete Only.\n"); - set_gpio(MUX_GPIO, GPIO_LEVEL_HIGH); - set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_HIGH); - set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); - - sysinfo->enable_igd = 0; - sysinfo->enable_peg = 1; - break; - case HYBRID_GRAPHICS_SWITCHABLE: - printk(BIOS_DEBUG, "Activating Switchable (both GPUs).\n"); - set_gpio(MUX_GPIO, GPIO_LEVEL_LOW); - set_gpio(BCL_CTL_GPIO, GPIO_LEVEL_LOW); - set_gpio(GFX_PWR_EN_GPIO, GPIO_LEVEL_HIGH); - - sysinfo->enable_igd = 1; - sysinfo->enable_peg = 1; - break; - } -} diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 2d35650..5f4ac4b 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -31,6 +31,7 @@ #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> +#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> #include <timestamp.h> #include "dock.h" #include "gpio.h" @@ -38,7 +39,20 @@ #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) -void hybrid_graphics_init(sysinfo_t *sysinfo); +#define GFX_PWR_EN_GPIO 49 + +static void hybrid_graphics_init(sysinfo_t *sysinfo) +{ + bool peg, igd; + + early_hybrid_graphics(&igd, &peg); + + sysinfo->enable_igd = igd; + sysinfo->enable_peg = peg; + + /* Toggle dGPU power */ + set_gpio(GFX_PWR_EN_GPIO, peg ? GPIO_LEVEL_HIGH : GPIO_LEVEL_LOW); +} static void early_lpc_setup(void) { -- To view, visit https://review.coreboot.org/20793 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iad2eccaab19c71f11308853ba9326d8186e67c93 Gerrit-Change-Number: 20793 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: drvs/lenovo/hybrid_graphics: Add new hybrid graphics driver
by Patrick Rudolph (Code Review) 27 Jul '17

27 Jul '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20792 Change subject: drvs/lenovo/hybrid_graphics: Add new hybrid graphics driver ...................................................................... drvs/lenovo/hybrid_graphics: Add new hybrid graphics driver Introduce a chip_driver that uses devicetree instead of Kconfig. The new driver has the following advantages: * No more wasted IGD GFX stolen memory * Can be used by T500 series * Is even run on devices that do not have a dGPU installed * Can disable unused PEG port on devices without dGPU (and save power) * Use devicetree instead of Kconfig options * Support for multiple hybrid GPIO active levels * Support for backlight control GPIO * Support for _ROM on Optimus capable devices The driver is split into romstage part and ramstage part. Every mainboard has to call the driver in romstage to get the requested GPU state. The mainboard code then has to toggle GPU power or disable the IGD or PEG port. The ramstage part does handle the hygrid graphics GPIO, including optional backlight mux GPIO. Every GPIO can have it's own active level, as defined in devicetree. Devices are no longer disabled in ramstage. The existing hybrid graphics driver does the same configuration and should not interfere with this commit until it has been removed. Change-Id: Ie467f9a18b35ab3b8a523dbf51c5575db5b374a5 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/drivers/lenovo/hybrid_graphics/Kconfig A src/drivers/lenovo/hybrid_graphics/Makefile.inc A src/drivers/lenovo/hybrid_graphics/chip.h A src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c A src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h A src/drivers/lenovo/hybrid_graphics/romstage.c 6 files changed, 232 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/20792/1 diff --git a/src/drivers/lenovo/hybrid_graphics/Kconfig b/src/drivers/lenovo/hybrid_graphics/Kconfig new file mode 100644 index 0000000..389dfb9 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/lenovo/hybrid_graphics/Makefile.inc b/src/drivers/lenovo/hybrid_graphics/Makefile.inc new file mode 100644 index 0000000..d9e5079 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics/Makefile.inc @@ -0,0 +1,15 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c +romstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += romstage.c diff --git a/src/drivers/lenovo/hybrid_graphics/chip.h b/src/drivers/lenovo/hybrid_graphics/chip.h new file mode 100644 index 0000000..d5ce74e --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics/chip.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LENOVO_HYBRID_GRAPHICS_CHIP_H_ +#define _LENOVO_HYBRID_GRAPHICS_CHIP_H_ + +#define HYBRID_GRAPHICS_PORT 0xff + +#define HYBRID_GRAPHICS_DEVICE 0xf + +enum hybrid_graphics_req { + HYBRID_GRAPHICS_INTEGRATED = 0, + HYBRID_GRAPHICS_DISCRETE = 1, + HYBRID_GRAPHICS_DUAL = 2 +}; + +enum dgpu_detect_lvl { + DGPU_INSTALLED = 0, + DGPU_NOT_INSTALLED = 1, +}; + +struct drivers_lenovo_hybrid_graphics_config { + unsigned int detect_gpio; + + unsigned int has_panel_hybrid_gpio; + unsigned int panel_hybrid_gpio; + unsigned int panel_integrated_lvl; + + unsigned int has_backlight_gpio; + unsigned int backlight_gpio; + unsigned int backlight_integrated_lvl; +}; + +#endif /* _LENOVO_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c new file mode 100644 index 0000000..ab13747 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <option.h> +#include <device/device.h> +#include <device/pci_def.h> + +#include <southbridge/intel/common/gpio.h> +#include <console/console.h> +#include "chip.h" + +/* + * Switch panel mux or backlight mux to active GPU. + * In case both GPUs are active switch panel mux to integrated. + */ +static void lenovo_hybrid_graphics_enable(struct device *dev) +{ + const struct drivers_lenovo_hybrid_graphics_config *config; + enum hybrid_graphics_req mode = HYBRID_GRAPHICS_INTEGRATED; + + /* Don't confuse anyone else and disable the fake device */ + dev->enabled = 0; + + config = dev->chip_info; + if (!config || (get_gpio(config->detect_gpio) == DGPU_NOT_INSTALLED)) { + printk(BIOS_DEBUG, "Hybrid graphics: Not installed\n"); + return; + } + + get_option(&mode, "hybrid_graphics_mode"); + + if (mode == HYBRID_GRAPHICS_DISCRETE) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Switching panel to discrete GPU.\n"); + + if (config->has_panel_hybrid_gpio) + set_gpio(config->panel_hybrid_gpio, + ~config->panel_integrated_lvl); + + if (config->has_backlight_gpio) + set_gpio(config->backlight_gpio, + ~config->backlight_integrated_lvl); + } else { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Switching panel to integrated GPU.\n"); + + if (config->has_panel_hybrid_gpio) + set_gpio(config->panel_hybrid_gpio, + config->panel_integrated_lvl); + + if (config->has_backlight_gpio) + set_gpio(config->backlight_gpio, + config->backlight_integrated_lvl); + } +} + +struct chip_operations drivers_lenovo_hybrid_graphics_ops = { + CHIP_NAME("Lenovo hybrid graphics driver") + .enable_dev = &lenovo_hybrid_graphics_enable +}; diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h new file mode 100644 index 0000000..b238440 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_ +#define _DRIVERS_LENOVO_HYBRID_GRAPHICS_H_ + +void early_hybrid_graphics(bool *enable_igd, bool *enable_peg); + +#endif /* _DRIVERS_LENOVO_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c new file mode 100644 index 0000000..53eb4a0 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <option.h> +#include <device/device.h> +#include <device/pci_def.h> + +#include <southbridge/intel/common/gpio.h> +#include <console/console.h> +#include "hybrid_graphics.h" +#include "chip.h" + +/* + * Returns the hybrid graphics presence and user's card preferences. + */ +void early_hybrid_graphics(bool *enable_igd, bool *enable_peg) +{ + const struct drivers_lenovo_hybrid_graphics_config *config; + const struct device *dev; + enum hybrid_graphics_req mode = HYBRID_GRAPHICS_INTEGRATED; + + dev = dev_find_slot_pnp(HYBRID_GRAPHICS_PORT, HYBRID_GRAPHICS_DEVICE); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "Hybrid graphics: ERROR\n"); + *enable_igd = true; + *enable_peg = false; + return; + } + + config = dev->chip_info; + if (get_gpio(config->detect_gpio) == DGPU_NOT_INSTALLED) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " No discrete GPU present.\n"); + *enable_igd = true; + *enable_peg = false; + return; + } + + get_option(&mode, "hybrid_graphics_mode"); + + if (mode == HYBRID_GRAPHICS_DISCRETE) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Disabling integrated GPU.\n"); + + *enable_igd = false; + *enable_peg = true; + } else if (mode == HYBRID_GRAPHICS_INTEGRATED) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Disabling discrete GPU.\n"); + + *enable_igd = true; + *enable_peg = false; + } else { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Activating Switchable (both GPUs).\n"); + + *enable_igd = true; + *enable_peg = true; + } +} -- To view, visit https://review.coreboot.org/20792 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie467f9a18b35ab3b8a523dbf51c5575db5b374a5 Gerrit-Change-Number: 20792 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Clarify BAR mask in SPI base
by build bot (Jenkins) (Code Review) 27 Jul '17

27 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20790 ) Change subject: soc/amd/stoneyridge: Clarify BAR mask in SPI base ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/57910/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13355/ : SUCCESS -- To view, visit https://review.coreboot.org/20790 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Gerrit-Change-Number: 20790 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Jul 2017 16:28:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Documentation: Add binary extraction documentation
by build bot (Jenkins) (Code Review) 27 Jul '17

27 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20753 ) Change subject: Documentation: Add binary extraction documentation ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/57909/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13354/ : SUCCESS -- To view, visit https://review.coreboot.org/20753 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia31b01afc66789f95c7d21a0d41b532bc19a6430 Gerrit-Change-Number: 20753 Gerrit-PatchSet: 4 Gerrit-Owner: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Simon Glass <sjg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Jul 2017 16:26:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Convert 48Mhz enable to read/write32
by Marshall Dawson (Code Review) 27 Jul '17

27 Jul '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20791 Change subject: soc/amd/stoneyridge: Convert 48Mhz enable to read/write32 ...................................................................... soc/amd/stoneyridge: Convert 48Mhz enable to read/write32 Use the appropriate read32() and write32() calls. Remove unnecessary cast. Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/early_setup.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/20791/1 diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index ca3447f..f1539ea 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -224,18 +224,17 @@ void hudson_clk_output_48Mhz(void) { - u32 data, *memptr; + u32 ctrl; /* * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so * 48Mhz will be on ball AP13 (FT3b package) */ - memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40); - data = *memptr; + ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40)); /* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */ - data &= (u32)~(1<<2); - *memptr = data; + ctrl &= ~(1<<2); + write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl); } static uintptr_t hudson_spibase(void) -- To view, visit https://review.coreboot.org/20791 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d Gerrit-Change-Number: 20791 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Clarify BAR mask in SPI base
by Marshall Dawson (Code Review) 27 Jul '17

27 Jul '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/20790 Change subject: soc/amd/stoneyridge: Clarify BAR mask in SPI base ...................................................................... soc/amd/stoneyridge: Clarify BAR mask in SPI base The format of the D14F3xA0 SPI Base_Addr register is different than a traditional BAR. Change the function to preserve any enables already in place. Change the AND mask to remove the reserved field and the enables. Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/early_setup.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/20790/1 diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index 68bccc4..ca3447f 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -242,13 +242,16 @@ { /* Make sure the base address is predictable */ device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + u32 base, enables; - u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) - & 0xfffffff0; + base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); + enables = base & 0xf; + base &= ~0x3f; + if (!base) { base = SPI_BASE_ADDRESS; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base - | SPI_ROM_ENABLE); + | enables | SPI_ROM_ENABLE); /* PCI_COMMAND_MEMORY is read-only and enabled. */ } return (uintptr_t)base; -- To view, visit https://review.coreboot.org/20790 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Gerrit-Change-Number: 20790 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: cpu/amd/pi Fix checkpatch warnings and errors
by build bot (Jenkins) (Code Review) 27 Jul '17

27 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20098 ) Change subject: cpu/amd/pi Fix checkpatch warnings and errors ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/57908/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13353/ : SUCCESS -- To view, visit https://review.coreboot.org/20098 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4 Gerrit-Change-Number: 20098 Gerrit-PatchSet: 3 Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ryan Salsamendi <rsalsamendi(a)hotmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Jul 2017 16:16:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/cpu/amd/quadcore Fix checkpatch errors/warnings
by build bot (Jenkins) (Code Review) 27 Jul '17

27 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19987 ) Change subject: src/cpu/amd/quadcore Fix checkpatch errors/warnings ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/57907/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13352/ : SUCCESS -- To view, visit https://review.coreboot.org/19987 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0 Gerrit-Change-Number: 19987 Gerrit-PatchSet: 5 Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Jul 2017 16:07:41 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: src/cpu/amd/quadcore Fix checkpatch errors/warnings
by build bot (Jenkins) (Code Review) 27 Jul '17

27 Jul '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19987 ) Change subject: src/cpu/amd/quadcore Fix checkpatch errors/warnings ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/57906/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13351/ : SUCCESS -- To view, visit https://review.coreboot.org/19987 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0 Gerrit-Change-Number: 19987 Gerrit-PatchSet: 4 Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 27 Jul 2017 15:45:46 +0000 Gerrit-HasComments: No

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coreboot-gerrit July 2017