coreboot-gerrit June 2017

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Change in coreboot[master]: nb/intel/haswell/gma: Set ASLS on S3 resume
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20285 ) Change subject: nb/intel/haswell/gma: Set ASLS on S3 resume ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56314/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11907/ : SUCCESS -- To view, visit https://review.coreboot.org/20285 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1944fcca91ee1a0ad8df5c8b6f402e907de5e78f Gerrit-Change-Number: 20285 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 18:33:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/haswell: set ASLB gnvs to OpRegion ACPI memory address
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20254 ) Change subject: nb/haswell: set ASLB gnvs to OpRegion ACPI memory address ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/56312/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/11906/ : SUCCESS -- To view, visit https://review.coreboot.org/20254 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39 Gerrit-Change-Number: 20254 Gerrit-PatchSet: 3 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 18:25:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable common SMM code for SKL
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19440 ) Change subject: soc/intel/skylake: Enable common SMM code for SKL ...................................................................... Patch Set 16: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56311/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11904/ : SUCCESS -- To view, visit https://review.coreboot.org/19440 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icdbde4cf39703ce10283715d2a28e501de489aae Gerrit-Change-Number: 19440 Gerrit-PatchSet: 16 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 18:24:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] nb/haswell: use GMA common OpRegion
by Matt DeVillier (Code Review) 27 Jun '17

27 Jun '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/20395 Change subject: [WIP] nb/haswell: use GMA common OpRegion ...................................................................... [WIP] nb/haswell: use GMA common OpRegion Add update_igd_opregion() to handle platform-specific mailbox data. Change-Id: Id1d8829d8e8542a165d5eb57725f211c4ae56cf8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/gma.c 2 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/20395/1 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 90f8774..d6cf0d7 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -17,7 +17,7 @@ bool select CPU_INTEL_HASWELL select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE - select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION + select INTEL_GMA_OPREGION select INTEL_DDI select INTEL_GMA_ACPI select RELOCATABLE_RAMSTAGE diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 0dcd82a..ef80f77 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -23,7 +23,7 @@ #include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/i915.h> #include <cpu/intel/haswell/haswell.h> -#include <northbridge/intel/common/gma_opregion.h> +#include <drivers/intel/gma/opregion.h> #include <stdlib.h> #include <string.h> #include <southbridge/intel/lynxpoint/nvs.h> @@ -524,6 +524,39 @@ drivers_intel_gma_displays_ssdt_generate(gfx); } +/* Initialize IGD OpRegion, called from ACPI code */ +static void +update_igd_opregion(igd_opregion_t *opregion) +{ + /* We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + //From Intel OpRegion reference doc + opregion->header.pcon = 279; + + // Initialize Mailbox 1 + opregion->mailbox1.clid = 1; + + /* Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + intel_gma_opregion_register((uintptr_t)opregion); +} + static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, @@ -534,6 +567,7 @@ if (init_igd_opregion(opregion) != CB_SUCCESS) return current; + update_igd_opregion(opregion); current += sizeof(igd_opregion_t); -- To view, visit https://review.coreboot.org/20395 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id1d8829d8e8542a165d5eb57725f211c4ae56cf8 Gerrit-Change-Number: 20395 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: [WIP] drv/intel/gma/opregion: Add common init_idg_opregion()
by Matt DeVillier (Code Review) 27 Jun '17

27 Jun '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/20394 Change subject: [WIP] drv/intel/gma/opregion: Add common init_idg_opregion() ...................................................................... [WIP] drv/intel/gma/opregion: Add common init_idg_opregion() Add a new common method to initialize ACPI OpRegion. Change-Id: I2378043a82bdf785df10a702afef1123662e04d9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc M src/drivers/intel/gma/opregion.c M src/drivers/intel/gma/opregion.h 4 files changed, 171 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/20394/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 1e60a42..c3bb8e0 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -109,3 +109,21 @@ read over the I2C interface of the coupled digital port. endif + +config INTEL_GMA_OPREGION + def_bool n + +config ADD_VBT_DATA_FILE + bool "Add a Video Bios Table (VBT) binary to CBFS" + depends on INTEL_GMA_OPREGION + default y if INTEL_GMA_OPREGION + help + Add a VBT file data file to CBFS. The VBT describes the integrated + GPU and connections, and can be used in leiu of a VBIOS in order to + populate the ACPI OpRegion VBT data. + +config VBT_FILE + string "VBT binary path and filename" + depends on ADD_VBT_DATA_FILE + help + The path and filename of the VBT binary. diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 50494e1..ce81d37 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -19,8 +19,11 @@ ramstage-$(CONFIG_INTEL_INT15) += int15.c endif ramstage-$(CONFIG_INTEL_GMA_ACPI) += acpi.c -ramstage-$(CONFIG_INTEL_GMA_ACPI) += opregion.c +ramstage-$(CONFIG_INTEL_GMA_OPREGION) += opregion.c +cbfs-files-$(CONFIG_ADD_VBT_DATA_FILE) += vbt.bin +vbt.bin-file := $(call strip_quotes,$(CONFIG_VBT_FILE)) +vbt.bin-type := raw ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y) diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c index 5cd04ae..02563d0 100644 --- a/src/drivers/intel/gma/opregion.c +++ b/src/drivers/intel/gma/opregion.c @@ -14,10 +14,15 @@ * GNU General Public License for more details. */ +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <string.h> +#include "intel_bios.h" #include "opregion.h" /* Write ASLS PCI register and enables SWSCI. */ @@ -39,3 +44,145 @@ reg16 |= SMISCISEL; pci_write_config16(igd, SWSCI, reg16); } + +void * __attribute__((weak))get_fake_vbt_signature(void) +{ + return NULL; +} + +static void +generate_vbt(struct vbt_header *const head, const char *const idstr) +{ + u8 *ptr; + + memset(head, 0, sizeof (*head)); + + memset(head->signature, ' ', sizeof (head->signature)); + memcpy(head->signature, idstr, + MIN(strlen(idstr), sizeof (head->signature))); + head->version = 100; + head->header_size = sizeof (*head); + head->bdb_offset = sizeof (*head); + + struct bdb_header *const bdb_head = (struct bdb_header *)(head + 1); + memset(bdb_head, 0, sizeof (*bdb_head)); + memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16); + bdb_head->version = 0xa8; + bdb_head->header_size = sizeof (*bdb_head); + + ptr = (u8 *)(bdb_head + 1); + + ptr[0] = BDB_GENERAL_FEATURES; + ptr[1] = sizeof (struct bdb_general_features); + ptr[2] = sizeof (struct bdb_general_features) >> 8; + ptr += 3; + + struct bdb_general_features *const genfeat = + (struct bdb_general_features *)ptr; + memset(genfeat, 0, sizeof (*genfeat)); + genfeat->panel_fitting = 3; + genfeat->flexaim = 1; + genfeat->download_ext_vbt = 1; + genfeat->enable_ssc = IS_ENABLED(CONFIG_INTEL_GMA_SSC_ALTERNATE_REF); + genfeat->ssc_freq = IS_ENABLED(CONFIG_INTEL_GMA_SSC_ALTERNATE_REF); + genfeat->rsvd10 = 0x4; + genfeat->legacy_monitor_detect = 1; + genfeat->int_crt_support = 1; + genfeat->dp_ssc_enb = 1; + + ptr += sizeof (*genfeat); + + bdb_head->bdb_size = ptr - (u8 *)bdb_head; + head->vbt_size = ptr - (u8 *)head; + head->vbt_checksum = 0; +} + +enum cb_err +init_igd_opregion(igd_opregion_t *opregion) +{ + struct region_device vbt_rdev; + optionrom_vbt_t *vbt = NULL; + optionrom_vbt_t *ext_vbt; + uint32_t vbtsig = 0; + struct cbfsf file_desc; + int need_unmap = 0; + + /* try to locate vbt.bin in CBFS */ + if (cbfs_boot_locate(&file_desc, "vbt.bin", NULL) == CB_SUCCESS) { + cbfs_file_data(&vbt_rdev, &file_desc); + vbt = rdev_mmap_full(&vbt_rdev); + if (vbt) { + /* Validate the vbt file */ + memcpy(&vbtsig, vbt, sizeof(uint32_t)); + if (vbtsig != VBT_SIGNATURE) { + printk(BIOS_ERR, "Invalid signature in VBT data file (vbt.bin)!\n"); + rdev_munmap(&vbt_rdev, vbt); + vbt = NULL; + } + need_unmap = 1; + } else { + printk(BIOS_ERR, "VBT couldn't be read\n"); + } + } else { + printk(BIOS_NOTICE, "Could not locate a VBT file in in CBFS\n"); + } + + /* If no vbt.bin, try to load from VBIOS in CBFS */ + if (!vbt) { + optionrom_header_t *oprom = (optionrom_header_t *) pci_rom_probe(dev_find_slot(0, PCI_DEVFN(0x2,0))); + if (oprom) { + printk(BIOS_DEBUG, "VBIOS found at %p\n", oprom); + vbt = (optionrom_vbt_t *)(oprom + oprom->vbt_offset); + if (read32(vbt->hdr_signature) != VBT_SIGNATURE) { + printk(BIOS_DEBUG, "VBIOS VBT not found!\n"); + vbt = NULL; + } + } else { + printk(BIOS_DEBUG, "VBIOS not found.\n"); + } + } + + /* TODO: 3rd option - generate fake VBT */ + if (!vbt) { + optionrom_vbt_t fake_vbt; + generate_vbt((struct vbt_header *)&fake_vbt, get_fake_vbt_signature()); + vbt = &fake_vbt; + } + + /* Ensure we have something to load into opregion */ + if (!vbt) + return CB_ERR; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(opregion->header.signature)); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, + ARRAY_SIZE(vbt->coreblock_biosbuild)); + /* Extended VBT support */ + if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) { + ext_vbt = cbmem_add(CBMEM_ID_EXT_VBT, vbt->hdr_vbt_size); + + if (ext_vbt == NULL) { + printk(BIOS_ERR, "Unable to add Ext VBT to cbmem!\n"); + rdev_munmap(&vbt_rdev, vbt); + return CB_ERR; + } + + memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); + opregion->mailbox3.rvda = (uintptr_t)ext_vbt; + opregion->mailbox3.rvds = vbt->hdr_vbt_size; + } else { + /* Raw VBT size which can fit in gvd1 */ + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size); + } + + /* 8KiB */ + opregion->header.size = sizeof(igd_opregion_t) / KiB; + opregion->header.version = (IGD_OPREGION_VERSION << 24); + + if (need_unmap) + rdev_munmap(&vbt_rdev, vbt); + + return CB_SUCCESS; +} diff --git a/src/drivers/intel/gma/opregion.h b/src/drivers/intel/gma/opregion.h index c590805..85b54f1 100644 --- a/src/drivers/intel/gma/opregion.h +++ b/src/drivers/intel/gma/opregion.h @@ -246,5 +246,7 @@ } __attribute__((packed)) optionrom_vbt_t; void intel_gma_opregion_register(uintptr_t opregion); +void * __attribute__((weak)) get_fake_vbt_signature(void); +enum cb_err init_igd_opregion(igd_opregion_t *opregion); #endif /* _COMMON_GMA_H_ */ -- To view, visit https://review.coreboot.org/20394 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2378043a82bdf785df10a702afef1123662e04d9 Gerrit-Change-Number: 20394 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/kahlee: Enable TPM
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19848 ) Change subject: google/kahlee: Enable TPM ...................................................................... Patch Set 14: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56310/ : SUCCESS -- To view, visit https://review.coreboot.org/19848 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Gerrit-Change-Number: 19848 Gerrit-PatchSet: 14 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 18:18:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/lint: Add check to make sure 'coreboot' is lowercase
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20032 ) Change subject: util/lint: Add check to make sure 'coreboot' is lowercase ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/56309/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/11903/ : SUCCESS -- To view, visit https://review.coreboot.org/20032 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b52342488dacc56ef6083db5503507af35d41ac Gerrit-Change-Number: 20032 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 17:20:01 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/*/romstage, sb/intel/ibexpeak/lpc: ACPI TRAP cleanup
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20329 ) Change subject: mb/*/romstage,sb/intel/ibexpeak/lpc: ACPI TRAP cleanup ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56305/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11900/ : SUCCESS -- To view, visit https://review.coreboot.org/20329 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83fa97fab153e2709e1ef20e014b91c3410d4c5b Gerrit-Change-Number: 20329 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 17:15:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drv/intel/gma/acpi/common: Remove dead code
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20369 ) Change subject: drv/intel/gma/acpi/common: Remove dead code ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56303/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11898/ : SUCCESS -- To view, visit https://review.coreboot.org/20369 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3867ccad564c9d1da04823afdd82a8dd57d042ff Gerrit-Change-Number: 20369 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 17:13:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/*/Kconfig: Add new symbol ENABLE_SMI_TRAP_SUPPORT
by build bot (Jenkins) (Code Review) 27 Jun '17

27 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20393 ) Change subject: mb/*/Kconfig: Add new symbol ENABLE_SMI_TRAP_SUPPORT ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56306/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/11901/ : SUCCESS -- To view, visit https://review.coreboot.org/20393 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie042824ee2717140dfff7e99157fe2d3fd17e234 Gerrit-Change-Number: 20393 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 27 Jun 2017 17:07:05 +0000 Gerrit-HasComments: No

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coreboot-gerrit June 2017