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coreboot-gerrit
June 2017
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coreboot-gerrit@coreboot.org
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Change in coreboot[master]: superio/winbond/*/header: Include <arch/io.h>
by Arthur Heymans (Code Review)
01 Jun '17
01 Jun '17
Arthur Heymans has uploaded a new change for review. (
https://review.coreboot.org/20004
) Change subject: superio/winbond/*/header: Include <arch/io.h> ...................................................................... superio/winbond/*/header: Include <arch/io.h> Include <arch/io.h> since functions use types defined in there. Change-Id: Iba6bcea4377359c15e3148062458186ee222b8e2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/superio/winbond/w83627dhg/w83627dhg.h M src/superio/winbond/w83627ehg/w83627ehg.h M src/superio/winbond/w83627thg/w83627thg.h M src/superio/winbond/wpcd376i/wpcd376i.h 4 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/20004/1 diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index a527e17..5370437 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -18,6 +18,8 @@ #ifndef SUPERIO_WINBOND_W83627DHG_H #define SUPERIO_WINBOND_W83627DHG_H +#include <arch/io.h> + #define W83627DHG_FDC 0 /* Floppy */ #define W83627DHG_PP 1 /* Parallel port */ #define W83627DHG_SP1 2 /* Com1 */ diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index fe93a62..5b760f2 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -18,6 +18,8 @@ #ifndef SUPERIO_WINBOND_W83627EHG_H #define SUPERIO_WINBOND_W83627EHG_H +#include <arch/io.h> + #define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_PP 1 /* Parallel port */ #define W83627EHG_SP1 2 /* Com1 */ diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index 92fbd27..acea382 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -19,6 +19,8 @@ #ifndef SUPERIO_WINBOND_W83627THG_W83627THG_H #define SUPERIO_WINBOND_W83627THG_W83627THG_H +#include <arch/io.h> + #define W83627THG_FDC 0 /* Floppy */ #define W83627THG_PP 1 /* Parallel port */ #define W83627THG_SP1 2 /* Com1 */ diff --git a/src/superio/winbond/wpcd376i/wpcd376i.h b/src/superio/winbond/wpcd376i/wpcd376i.h index bc202f0..b894e4e 100644 --- a/src/superio/winbond/wpcd376i/wpcd376i.h +++ b/src/superio/winbond/wpcd376i/wpcd376i.h @@ -18,6 +18,8 @@ #ifndef SUPERIO_WINBOND_WPCD376I_WPCD376I_H #define SUPERIO_WINBOND_WPCD376I_WPCD376I_H +#include <arch/io.h> + /* Logical Device Numbers (LDN). */ #define WPCD376I_FDC 0 /* Floppy */ #define WPCD376I_LPT 1 /* Parallel port */ -- To view, visit
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Gerrit-MessageType: newchange Gerrit-Change-Id: Iba6bcea4377359c15e3148062458186ee222b8e2 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
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Change in coreboot[master]: mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selection
by build bot (Jenkins) (Code Review)
01 Jun '17
01 Jun '17
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/20002
) Change subject: mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selection ...................................................................... Patch Set 2: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/54713/
: SUCCESS -- To view, visit
https://review.coreboot.org/20002
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Gerrit-MessageType: comment Gerrit-Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No
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Change in coreboot[master]: nb/intel/x4x/raminit: Limit DDR3 to 400MHz
by build bot (Jenkins) (Code Review)
01 Jun '17
01 Jun '17
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/19919
) Change subject: nb/intel/x4x/raminit: Limit DDR3 to 400MHz ...................................................................... Patch Set 2: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/54711/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/10416/
: SUCCESS -- To view, visit
https://review.coreboot.org/19919
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Gerrit-MessageType: comment Gerrit-Change-Id: I120b22ca8febc5a3644339045218e997d8e8496e Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No
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Change in coreboot[master]: nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings
by build bot (Jenkins) (Code Review)
01 Jun '17
01 Jun '17
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/19917
) Change subject: nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings ...................................................................... Patch Set 2: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/54709/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/10414/
: SUCCESS -- To view, visit
https://review.coreboot.org/19917
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Gerrit-MessageType: comment Gerrit-Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No
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Change in coreboot[master]: nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings
by build bot (Jenkins) (Code Review)
01 Jun '17
01 Jun '17
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/19916
) Change subject: nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings ...................................................................... Patch Set 2: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/54707/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/10412/
: SUCCESS -- To view, visit
https://review.coreboot.org/19916
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Gerrit-MessageType: comment Gerrit-Change-Id: Icf5bb4a8044bbf2f58c8c9a4774329a95bf3b070 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No
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Change in coreboot[master]: [WIP]mb/intel/dg41wv: Add mainboard
by build bot (Jenkins) (Code Review)
01 Jun '17
01 Jun '17
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/20003
) Change subject: [WIP]mb/intel/dg41wv: Add mainboard ...................................................................... Patch Set 1: Verified-1 Build Failed
https://qa.coreboot.org/job/coreboot-gerrit/54712/
: FAILURE
https://qa.coreboot.org/job/coreboot-checkpatch/10417/
: SUCCESS -- To view, visit
https://review.coreboot.org/20003
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Gerrit-MessageType: comment Gerrit-Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No
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Change in coreboot[master]: mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selection
by Aamir Bohra (Code Review)
01 Jun '17
01 Jun '17
Aamir Bohra has posted comments on this change. (
https://review.coreboot.org/20002
) Change subject: mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selection ...................................................................... Patch Set 1: (3 comments)
https://review.coreboot.org/#/c/20002/1//COMMIT_MSG
Commit Message: Line 7: src/mainboard: Remove MONOTONIC_TIMER_MSR selection > mainboard/*/*/Kconfig? Done Line 10: Konfigs,as it only does a reduntant selection of > space after ',' Done Line 11: HAVE_MONOTONIC_TIMER config,already selected under > space Done -- To view, visit
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Gerrit-MessageType: comment Gerrit-Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes
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Change in coreboot[master]: nb/intel/x4x/raminit: Implement read and write DQ DQS training
by build bot (Jenkins) (Code Review)
01 Jun '17
01 Jun '17
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/19879
) Change subject: nb/intel/x4x/raminit: Implement read and write DQ DQS training ...................................................................... Patch Set 5: Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/54708/
: SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/10413/
: SUCCESS -- To view, visit
https://review.coreboot.org/19879
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Gerrit-MessageType: comment Gerrit-Change-Id: I806840445b5e768d079910fb9870a2cee7b9f1ca Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No
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Change in coreboot[master]: soc/intel/skylake: Use Intel timer common code
by build bot (Jenkins) (Code Review)
01 Jun '17
01 Jun '17
build bot (Jenkins) has posted comments on this change. (
https://review.coreboot.org/19912
) Change subject: soc/intel/skylake: Use Intel timer common code ...................................................................... Patch Set 5: Verified-1 Build Failed
https://qa.coreboot.org/job/coreboot-gerrit/54704/
: ABORTED
https://qa.coreboot.org/job/coreboot-checkpatch/10409/
: SUCCESS -- To view, visit
https://review.coreboot.org/19912
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Gerrit-MessageType: comment Gerrit-Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No
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Change in coreboot[master]: soc/intel/common: Add common Intel timer code
by Aamir Bohra (Code Review)
01 Jun '17
01 Jun '17
Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19911
to look at the new patch set (#4). Change subject: soc/intel/common: Add common Intel timer code ...................................................................... soc/intel/common: Add common Intel timer code Add common timer code to get tsc frequency(Mhz). Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/timer/Kconfig A src/soc/intel/common/block/timer/Makefile.inc A src/soc/intel/common/block/timer/timer.c 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/19911/4 -- To view, visit
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Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>
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