coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: amd/gardenia: Init cbmem in romstage
by Marshall Dawson (Code Review) 01 Jun '17

01 Jun '17

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/19752 ) Change subject: amd/gardenia: Init cbmem in romstage ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/19752/2/src/mainboard/amd/gardenia/romstage… File src/mainboard/amd/gardenia/romstage.c: Line 67: cbmem_initialize_empty(); > This should be in the SoC code. Really, this entire sequence is needs to be I agree. This all moves in the "Convert to C_ENVIRONMENT_BOOTBLOCK" patch https://review.coreboot.org/#/c/19755. It felt like 6 vs. 0.5 dozen on which to do first. Doing it this way allowed me to easily verify the other was working as expected. -- To view, visit https://review.coreboot.org/19752 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6ede71ec660678bb5f77693a9095aa0f198e4e26 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK
by Marshall Dawson (Code Review) 01 Jun '17

01 Jun '17

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/19755 ) Change subject: WIP soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/19755/4/src/mainboard/amd/gardenia/bootbloc… File src/mainboard/amd/gardenia/bootblock/OemCustomize.c: Line 128: }; > some of this doesn't belong in the bootblock. So maybe lets split this file Well you wouldn't think so, but they're overrides for AmdInitEarly(). At the moment, I'm not certain why that call would require this info or whether it could be passed to a later call instead. -- To view, visit https://review.coreboot.org/19755 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: google/slippy: populate PEI SPD data for all channels
by Matt DeVillier (Code Review) 01 Jun '17

01 Jun '17

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/19981 ) Change subject: google/slippy: populate PEI SPD data for all channels ...................................................................... Patch Set 1: not directly, no. On BDW, mrc.bin populates the pei_data struct which is used to populate a CBMEM_INFO table and ultimately the SMBIOS table. Os HSW, the mrc.bin doesn't do this, so I've added a patch to populate the data: #19958. Even still, this doesn't eliminate the need for the spd_data struct in the pei_data to be populated for all/both sodimms/channels, which is what this patch does (basically bringing it in line with BDW) -- To view, visit https://review.coreboot.org/19981 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]mb/intel/dg41wv: Add mainboard
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20003 ) Change subject: [WIP]mb/intel/dg41wv: Add mainboard ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54718/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10422/ : SUCCESS -- To view, visit https://review.coreboot.org/20003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use Intel timer common code
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19913 ) Change subject: soc/intel/apollolake: Use Intel timer common code ...................................................................... Patch Set 3: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54716/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10420/ : SUCCESS -- To view, visit https://review.coreboot.org/19913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add common Intel timer code
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19911 ) Change subject: soc/intel/common: Add common Intel timer code ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54714/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10418/ : SUCCESS -- To view, visit https://review.coreboot.org/19911 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: superio/winbond/*/header: Include <arch/io.h>
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20004 ) Change subject: superio/winbond/*/header: Include <arch/io.h> ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54717/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10421/ : SUCCESS -- To view, visit https://review.coreboot.org/20004 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iba6bcea4377359c15e3148062458186ee222b8e2 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]mb/intel/dg41wv: Add mainboard
by Arthur Heymans (Code Review) 01 Jun '17

01 Jun '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20003 to look at the new patch set (#2). Change subject: [WIP]mb/intel/dg41wv: Add mainboard ...................................................................... [WIP]mb/intel/dg41wv: Add mainboard UNTESTED Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/intel/dg41wv/Kconfig A src/mainboard/intel/dg41wv/Kconfig.name A src/mainboard/intel/dg41wv/Makefile.inc A src/mainboard/intel/dg41wv/acpi/ec.asl A src/mainboard/intel/dg41wv/acpi/ich7_pci_irqs.asl A src/mainboard/intel/dg41wv/acpi/platform.asl A src/mainboard/intel/dg41wv/acpi/superio.asl A src/mainboard/intel/dg41wv/acpi/x4x_pci_irqs.asl A src/mainboard/intel/dg41wv/acpi_tables.c A src/mainboard/intel/dg41wv/board_info.txt A src/mainboard/intel/dg41wv/cmos.default A src/mainboard/intel/dg41wv/cmos.layout A src/mainboard/intel/dg41wv/cstates.c A src/mainboard/intel/dg41wv/devicetree.cb A src/mainboard/intel/dg41wv/dsdt.asl A src/mainboard/intel/dg41wv/gpio.c A src/mainboard/intel/dg41wv/hda_verb.c A src/mainboard/intel/dg41wv/romstage.c 18 files changed, 869 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/20003/2 -- To view, visit https://review.coreboot.org/20003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Use Intel timer common code
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19912 ) Change subject: soc/intel/skylake: Use Intel timer common code ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54715/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10419/ : SUCCESS -- To view, visit https://review.coreboot.org/19912 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x: Adapt post JEDEC for DDR3
by build bot (Jenkins) (Code Review) 01 Jun '17

01 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19918 ) Change subject: nb/intel/x4x: Adapt post JEDEC for DDR3 ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54710/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10415/ : SUCCESS -- To view, visit https://review.coreboot.org/19918 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit June 2017