coreboot-gerrit June 2017

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Change in coreboot[master]: rx6110sa: Add a software reset sequence in case of power loss
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20412 ) Change subject: rx6110sa: Add a software reset sequence in case of power loss ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56424/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12015/ : SUCCESS -- To view, visit https://review.coreboot.org/20412 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If64d672e51667523058041bd00e1e50ac047143d Gerrit-Change-Number: 20412 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 09:18:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/siemens/mc_apl1: Set up RTC backup mode to primary cell
by Werner Zeh (Code Review) 29 Jun '17

29 Jun '17

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/20414 Change subject: mb/siemens/mc_apl1: Set up RTC backup mode to primary cell ...................................................................... mb/siemens/mc_apl1: Set up RTC backup mode to primary cell Set RX6110SA RTC backup mode to primary cell. This mode reduces the backup current consumption of the RTC. Change-Id: I7c0c26a0ed5d8f48587acc917f8bb1c5c2b8869a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/20414/1 diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index 55734a2..3979870 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -65,7 +65,10 @@ device pci 16.0 on # - I2C 0 # Enable external RTC chip chip drivers/i2c/rx6110sa - register "cof_selection" = "0" + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" register "set_user_date" = "1" register "user_year" = "04" register "user_month" = "07" -- To view, visit https://review.coreboot.org/20414 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7c0c26a0ed5d8f48587acc917f8bb1c5c2b8869a Gerrit-Change-Number: 20414 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: mb/siemens/mc_bdx1: Set up RTC backup mode to primary cell
by Werner Zeh (Code Review) 29 Jun '17

29 Jun '17

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/20413 Change subject: mb/siemens/mc_bdx1: Set up RTC backup mode to primary cell ...................................................................... mb/siemens/mc_bdx1: Set up RTC backup mode to primary cell The used RTC6110SA has issues to enter backup mode when the power supply decreases too slow when the mainboard is turned off. Switch to backup mode "primary cell" to make sure backup mode will be entered correctly on power-off. In addition set IOCUTEN to minimize the backup current consumption of the RTC. Change-Id: I9733aa9f2981a25f6d42279eff0c4980e5eb5a5a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_bdx1/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/20413/1 diff --git a/src/mainboard/siemens/mc_bdx1/devicetree.cb b/src/mainboard/siemens/mc_bdx1/devicetree.cb index 543786b..8bb582e 100644 --- a/src/mainboard/siemens/mc_bdx1/devicetree.cb +++ b/src/mainboard/siemens/mc_bdx1/devicetree.cb @@ -12,7 +12,10 @@ device pci 1f.3 on # Enable external RTC chip chip drivers/i2c/rx6110sa - register "cof_selection" = "0" + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" register "set_user_date" = "1" register "user_year" = "04" register "user_month" = "07" -- To view, visit https://review.coreboot.org/20413 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9733aa9f2981a25f6d42279eff0c4980e5eb5a5a Gerrit-Change-Number: 20413 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: rx6110sa: Add a software reset sequence in case of power loss
by Werner Zeh (Code Review) 29 Jun '17

29 Jun '17

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/20412 Change subject: rx6110sa: Add a software reset sequence in case of power loss ...................................................................... rx6110sa: Add a software reset sequence in case of power loss According to the datasheet the RTC needs a power rising slope of no more than 100µs/V to ensure a correct power-on reset. If the mainboard that hosts the RTC cannot guarantee this, a software reset sequence is needed in the case where the battery was drained completely. As the rising slope of the power supply depends on so many parameters and is highly mainboard specific, refactor the initialization code to perform a software reset every time a power loss event is recognized by the RTC. Change-Id: If64d672e51667523058041bd00e1e50ac047143d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/rx6110sa/rx6110sa.c M src/drivers/i2c/rx6110sa/rx6110sa.h 2 files changed, 61 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/20412/1 diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 06735a7..761d83d 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -19,6 +19,7 @@ #include <version.h> #include <console/console.h> #include <bcd.h> +#include <timer.h> #include "chip.h" #include "rx6110sa.h" @@ -86,62 +87,84 @@ static void rx6110sa_init(struct device *dev) { struct drivers_i2c_rx6110sa_config *config = dev->chip_info; - uint8_t reg; + uint8_t reg, flags; + struct stopwatch sw; /* Do a dummy read first as requested in the datasheet. */ rx6110sa_read(dev, SECOND_REG); + /* Check power loss status by reading the VLF-bit. */ + flags = rx6110sa_read(dev, FLAG_REGISTER); + if (flags & VLF_BIT) { + /* + * Voltage low detected, perform RX6110 SA reset sequence as + * requested in the datasheet. The meaning of the registers 0x60 + * and above is not documented in the datasheet, they have to be + * used as requested according to Epson. + */ + rx6110sa_write(dev, BATTERY_BACKUP_REG, 0x00); + rx6110sa_write(dev, CTRL_REG, 0x00); + rx6110sa_write(dev, CTRL_REG, TEST_BIT); + rx6110sa_write(dev, 0x60, 0xd3); + rx6110sa_write(dev, 0x66, 0x03); + rx6110sa_write(dev, 0x6b, 0x02); + rx6110sa_write(dev, 0x6b, 0x01); + /* According to the datasheet one have to wait for at least 2 ms + * before the VLF bit can be cleared in the flag register after + * this reset sequence. As the other registers are still + * accessible use the stopwatch to parallel the flow. + */ + stopwatch_init_msecs_expire(&sw, AFTER_RESET_DELAY_MS); + } /* - * Set battery backup mode and power monitor sampling time even if there - * was no power loss to make sure that the right mode is used as it - * directly influences the backup current consumption and therefore the - * backup time. + * Set up important registers even if there was no power loss to make + * sure that the right mode is used as it directly influences the + * backup current consumption and therefore the backup time. These + * settings do not change current date and time and the RTC will not + * be stopped while the registers are set up. */ reg = (config->pmon_sampling & PMON_SAMPL_MASK) | (!!config->bks_off << 2) | (!!config->bks_on << 3) | (!!config->iocut_en << 4); rx6110sa_write(dev, BATTERY_BACKUP_REG, reg); - /* - * Check VLF-bit which indicates the RTC data loss, such as due to a - * supply voltage drop. - */ - reg = rx6110sa_read(dev, FLAG_REGISTER); - if (!(reg & VLF_BIT)) - /* No voltage low detected, everything is well. */ - return; - /* - * Voltage low detected, initialize RX6110 SA again. - * Set first some registers to known state. - */ - rx6110sa_write(dev, RESERVED_BIT_REG, RTC_INIT_VALUE); - rx6110sa_write(dev, DIGITAL_REG, 0x00); - reg = (!!config->enable_1hz_out << 4) | - (!!config->irq_output_pin << 2) | - (config->fout_output_pin & FOUT_OUTPUT_PIN_MASK); - rx6110sa_write(dev, IRQ_CONTROL_REG, reg); /* Clear timer enable bit and set frequency of clock output. */ reg = rx6110sa_read(dev, EXTENSION_REG); - reg &= ~(FSEL_MASK | TE_BIT); - reg |= (config->cof_selection << 6); + reg &= ~(FSEL_MASK); + reg |= ((config->cof_selection << 6) & FSEL_MASK); if (config->timer_preset) { /* Timer needs to be in stop mode prior to programming it. */ - rx6110sa_write(dev, EXTENSION_REG, reg); - reg &= ~TSEL_MASK; + if (reg & TE_BIT) { + reg &= ~TE_BIT; + rx6110sa_write(dev, EXTENSION_REG, reg); + } /* Program the timer preset value. */ rx6110sa_write(dev, TMR_COUNTER_0_REG, config->timer_preset & 0xff); rx6110sa_write(dev, TMR_COUNTER_1_REG, (config->timer_preset >> 8) & 0xff); /* Set Timer Enable bit and the timer clock value. */ + reg &= ~TSEL_MASK; reg |= ((!!config->timer_en << 4) | (config->timer_clk & TSEL_MASK)); } rx6110sa_write(dev, EXTENSION_REG, reg); - - /* Clear voltage low detect bit. */ - reg = rx6110sa_read(dev, FLAG_REGISTER); - reg &= ~VLF_BIT; - rx6110sa_write(dev, FLAG_REGISTER, reg); + rx6110sa_write(dev, CTRL_REG, 0x00); + rx6110sa_write(dev, DIGITAL_REG, 0x00); + rx6110sa_write(dev, RESERVED_BIT_REG, RTC_INIT_VALUE); + reg = (!!config->enable_1hz_out << 4) | + (!!config->irq_output_pin << 2) | + (config->fout_output_pin & FOUT_OUTPUT_PIN_MASK); + rx6110sa_write(dev, IRQ_CONTROL_REG, reg); + /* If there was no power loss event no further steps are needed. */ + if (!(flags & VLF_BIT)) + return; + /* There was a power loss event, clear voltage low detect bit. + * Take the needed delay after a reset sequence into account before the + * VLF-bit can be cleared. + */ + while (!stopwatch_expired(&sw)) + flags &= ~VLF_BIT; + rx6110sa_write(dev, FLAG_REGISTER, flags); /* Before setting the clock stop oscillator. */ rx6110sa_write(dev, CTRL_REG, STOP_BIT); diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.h b/src/drivers/i2c/rx6110sa/rx6110sa.h index ebd75ea..7e71f24 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.h +++ b/src/drivers/i2c/rx6110sa/rx6110sa.h @@ -29,7 +29,7 @@ #define MONTH_REG 0x15 #define YEAR_REG 0x16 #define RESERVED_BIT_REG 0x17 -#define RTC_INIT_VALUE 0x28 +#define RTC_INIT_VALUE 0xA8 #define ALARM_MINUTE_REG 0x18 #define ALARM_HOUR_REG 0x19 #define ALARM_WEEKDAY_REG 0x1A @@ -81,8 +81,10 @@ #define PMON_SAMPL_256_MS 0x03 /* Define on which pin of the RTC the generated square wave will be driven. */ -#define FOUT_IRQ2 0x00 /* IRQ2 pin used for Fout */ -#define FOUT_IRQ1 0x01 /* IRQ1 pin used for Fout */ -#define FOUT_DO_FOUT 0x02 /* DO/FOUT pin used for Fout */ +#define FOUT_IRQ2 0x00 /* IRQ2 pin used for Fout */ +#define FOUT_IRQ1 0x01 /* IRQ1 pin used for Fout */ +#define FOUT_DO_FOUT 0x02 /* DO/FOUT pin used for Fout */ + +#define AFTER_RESET_DELAY_MS 2 /* Delay after reset sequence */ #endif /* _I2C_RX6110SA_H_ */ -- To view, visit https://review.coreboot.org/20412 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If64d672e51667523058041bd00e1e50ac047143d Gerrit-Change-Number: 20412 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: soc/intel/quark/spi.c: Remove unused status assignment
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20411 ) Change subject: soc/intel/quark/spi.c: Remove unused status assignment ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56423/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12014/ : SUCCESS -- To view, visit https://review.coreboot.org/20411 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0a364539c37005cfd637b75c8cc23b84e274294d Gerrit-Change-Number: 20411 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 08:50:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/quark/spi.c: Remove unused status assignment
by Martin Kepplinger (Code Review) 29 Jun '17

29 Jun '17

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/20411 Change subject: soc/intel/quark/spi.c: Remove unused status assignment ...................................................................... soc/intel/quark/spi.c: Remove unused status assignment This removes an unused assignment of the local status variable and thus improves readability. Coverity had found this: *** CID 1376473: Code maintainability issues (UNUSED_VALUE) /src/soc/intel/quark/spi.c: 169 in xfer() 163 } 164 165 /* Use chip select 0 */ 166 ctrlr->address = (data[0] << 16) 167 | (data[1] << 8) 168 | data[2]; CID 1376473: Code maintainability issues (UNUSED_VALUE) Assigning value from "ctrlr->address" to "status" here, but that stored value is overwritten before it can be used. 169 status = ctrlr->address; 170 data += 3; 171 bytesout -= 3; 172 } 173 174 /* Build the control value */ Change-Id: I0a364539c37005cfd637b75c8cc23b84e274294d Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M src/soc/intel/quark/spi.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/20411/1 diff --git a/src/soc/intel/quark/spi.c b/src/soc/intel/quark/spi.c index 1d257a5..68f445f 100644 --- a/src/soc/intel/quark/spi.c +++ b/src/soc/intel/quark/spi.c @@ -166,7 +166,6 @@ ctrlr->address = (data[0] << 16) | (data[1] << 8) | data[2]; - status = ctrlr->address; data += 3; bytesout -= 3; } -- To view, visit https://review.coreboot.org/20411 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0a364539c37005cfd637b75c8cc23b84e274294d Gerrit-Change-Number: 20411 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de>

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Change in coreboot[master]: nb/intel/i945/gma.c: Add whitespace around '<<'
by Arthur Heymans (Code Review) 29 Jun '17

29 Jun '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20410 ) Change subject: nb/intel/i945/gma.c: Add whitespace around '<<' ...................................................................... Patch Set 1: Code-Review+1 For some reason linux does define these macros the short way too... -- To view, visit https://review.coreboot.org/20410 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic01bbae9acaabaade777db52825aa80d25fc5961 Gerrit-Change-Number: 20410 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 07:36:25 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/i945/gma.c: Remove redefined "DISPPLANE_BGRX888"
by Arthur Heymans (Code Review) 29 Jun '17

29 Jun '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20409 ) Change subject: nb/intel/i945/gma.c: Remove redefined "DISPPLANE_BGRX888" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/20409 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4e9414f39a29e4eac7e325672ce6520a5654d3bc Gerrit-Change-Number: 20409 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 07:34:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drv/intel/gma/opregion: Add function to set ASLS register
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20281 ) Change subject: drv/intel/gma/opregion: Add function to set ASLS register ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56422/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12013/ : SUCCESS -- To view, visit https://review.coreboot.org/20281 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4850500ac6d58f80b0eddc81514053c87774405c Gerrit-Change-Number: 20281 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 03:53:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: northbridge/intel: Add whitespace around '<<'
by Philippe Mathieu-Daudé (Code Review) 29 Jun '17

29 Jun '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/20398 ) Change subject: northbridge/intel: Add whitespace around '<<' ...................................................................... Patch Set 5: (7 comments) https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/e7505/raminit… File src/northbridge/intel/e7505/raminit.c: https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/e7505/raminit… PS5, Line 1849: | can you add spaces around | while here? https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/i945/raminit.… PS5, Line 251: | spaces https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/pineview/rami… File src/northbridge/intel/pineview/raminit.c: https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/pineview/rami… PS5, Line 74: #define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx << 1].card_type != 0) || (dimms[(idx << 1) + 1].card_type != 0)) : #define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx << 1].card_type == 0xf) || (dimms[(idx << 1) + 1].card_type == 0xf)) : #define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx << 1].card_type != 0) || (dimms[(idx << 1) + 1].card_type != 0)) break at 80 https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_common.h: https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/sandybridge/r… PS5, Line 148: | spaces https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/x4x/raminit_d… File src/northbridge/intel/x4x/raminit_ddr2.c: https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/x4x/raminit_d… PS5, Line 1620: (r) remove parentheses https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/x4x/x4x.h File src/northbridge/intel/x4x/x4x.h: https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/x4x/x4x.h@184 PS5, Line 184: ((dimms[(ch << 1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch << 1) + 1].ranks + 2)))) break at 80 https://review.coreboot.org/#/c/20398/5/src/northbridge/intel/x4x/x4x.h@189 PS5, Line 189: (r) remove () -- To view, visit https://review.coreboot.org/20398 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Gerrit-Change-Number: 20398 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 03:52:05 +0000 Gerrit-HasComments: Yes

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coreboot-gerrit June 2017