coreboot-gerrit June 2017

coreboot-gerrit@coreboot.org

1 participants
2269 discussions

Change in coreboot[master]: vendorcode/amd/pi: Update AGESA_CFLAGS
by Martin Roth (Code Review) 30 Jun '17

30 Jun '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/20423 Change subject: vendorcode/amd/pi: Update AGESA_CFLAGS ...................................................................... vendorcode/amd/pi: Update AGESA_CFLAGS -Split the existing cflags to a second line to stay under 80 characters -Add -D__LIBAGESA__ to cflags to enable printk in the binarypi agesa vendorcode. Change-Id: I2a64414491130275ba06e5bd76e0b01e450174e8 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/vendorcode/amd/pi/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/20423/1 diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 2e539f8..1f33020 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -74,7 +74,8 @@ AGESA_INC += -I$(src)/commonlib/include AGESA_INC += -I$(VBOOT_SOURCE)/firmware/include -AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing +AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss +AGESA_CFLAGS += -fno-strict-aliasing -D__LIBAGESA__ CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/20423 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2a64414491130275ba06e5bd76e0b01e450174e8 Gerrit-Change-Number: 20423 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: soc/intel/quark: Add I2C debugging
by build bot (Jenkins) (Code Review) 30 Jun '17

30 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20422 ) Change subject: soc/intel/quark: Add I2C debugging ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56442/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12031/ : SUCCESS -- To view, visit https://review.coreboot.org/20422 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia17be8b4213b13fd6c6a367d081414d0f21fbb0f Gerrit-Change-Number: 20422 Gerrit-PatchSet: 1 Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Jun 2017 00:39:28 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/quark: Add I2C debugging
by Lee Leahy (Code Review) 30 Jun '17

30 Jun '17

Lee Leahy has uploaded this change for review. ( https://review.coreboot.org/20422 Change subject: soc/intel/quark: Add I2C debugging ...................................................................... soc/intel/quark: Add I2C debugging Add I2C debugging support: * Add I2C_DEBUG Kconfig value to enable debugging * Display I2C segments before the transfer * Display errors that occur during the transfer * Display the number of bytes transferred for successful transfers TEST=Build and run on Galileo Gen2 Change-Id: Ia17be8b4213b13fd6c6a367d081414d0f21fbb0f Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- M src/soc/intel/quark/Kconfig M src/soc/intel/quark/i2c.c 2 files changed, 83 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/20422/1 diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index bbb1927..d1950a3 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -316,4 +316,14 @@ default n depends on STORAGE_TEST +##### +# I2C debug support +##### + +config I2C_DEBUG + bool "Enable I2C debugging" + default n + help + Display the I2C segments and controller errors + endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/i2c.c b/src/soc/intel/quark/i2c.c index 3988bbe..bc4451b 100644 --- a/src/soc/intel/quark/i2c.c +++ b/src/soc/intel/quark/i2c.c @@ -68,12 +68,21 @@ if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); + if (IS_ENABLED(CONFIG_I2C_DEBUG)) + printk(BIOS_ERR, + "0x%08x: ic_raw_intr_stat, I2C write error!\n", + status); return -1; } /* Check for timeout */ - if (stopwatch_expired(timeout)) + if (stopwatch_expired(timeout)) { + if (IS_ENABLED(CONFIG_I2C_DEBUG)) + printk(BIOS_ERR, + "0x%08x: ic_raw_intr_stat, I2C write timeout!\n", + status); return -1; + } /* Receive any available data */ status = regs->ic_status; @@ -134,12 +143,21 @@ if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); + if (IS_ENABLED(CONFIG_I2C_DEBUG)) + printk(BIOS_ERR, + "0x%08x: ic_raw_intr_stat, I2C read error!\n", + status); return -1; } /* Check for timeout */ - if (stopwatch_expired(timeout)) + if (stopwatch_expired(timeout)) { + if (IS_ENABLED(CONFIG_I2C_DEBUG)) + printk(BIOS_ERR, + "0x%08x: ic_raw_intr_stat, I2C read timeout!\n", + status); return -1; + } /* Receive any available data */ status = regs->ic_status; @@ -175,6 +193,7 @@ uint8_t chip; uint32_t cmd; int data_bytes; + int index; int length; I2C_REGS *regs; uint32_t restart; @@ -185,6 +204,22 @@ int total_bytes; uint8_t *tx_buffer; int tx_bytes; + + if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + for (index = 0; index < seg_count;) { + if (index == 0) + printk(BIOS_ERR, "I2C Start\n"); + printk(BIOS_ERR, "I2C segment[%d]:\n", index); + printk(BIOS_ERR, " 0x%08x: read\n", + segment[index].read); + printk(BIOS_ERR, " 0x%08x: chip\n", + segment[index].chip); + printk(BIOS_ERR, " 0x%p: buf\n", segment[index].buf); + printk(BIOS_ERR, " 0x%08x: len\n", segment[index].len); + printk(BIOS_ERR, "I2C %s\n", + (++index >= seg_count) ? "Stop" : "Restart"); + } + } regs = get_i2c_address(); @@ -228,7 +263,8 @@ bytes_transferred = 0; rx_buffer = NULL; restart = 0; - while (seg_count-- > 0) { + index = 0; + while (index++ < seg_count) { length = segment->len; total_bytes += length; ASSERT(segment->buf != NULL); @@ -236,7 +272,7 @@ ASSERT(segment->chip == chip); /* Determine if this is the last segment of the transaction */ - stop = (seg_count == 0) ? IC_DATA_CMD_STOP : 0; + stop = (index == seg_count) ? IC_DATA_CMD_STOP : 0; /* Fill the FIFO with the necessary command bytes */ if (segment->read) { @@ -246,8 +282,13 @@ length, stop, &timeout); /* Return any detected error */ - if (data_bytes < 0) + if (data_bytes < 0) { + if (IS_ENABLED(CONFIG_I2C_DEBUG)) + printk(BIOS_ERR, + "I2C segment[%d] failed\n", + index); return data_bytes; + } bytes_transferred += data_bytes; } else { /* Write the data into the FIFO */ @@ -257,8 +298,13 @@ length, stop, rx_buffer, &timeout); /* Return any detected error */ - if (data_bytes < 0) + if (data_bytes < 0) { + if (IS_ENABLED(CONFIG_I2C_DEBUG)) + printk(BIOS_ERR, + "I2C segment[%d] failed\n", + index); return data_bytes; + } bytes_transferred += data_bytes; } segment++; @@ -284,12 +330,29 @@ if (status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER | IC_INTR_TX_ABRT | IC_INTR_TX_OVER)) { i2c_disable(regs); + if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + printk(BIOS_ERR, + "0x%08x: ic_raw_intr_stat, I2C read error!\n", + status); + printk(BIOS_ERR, + "I2C segment[%d] failed\n", + seg_count - 1); + } return -1; } /* Check for timeout */ - if (stopwatch_expired(&timeout)) + if (stopwatch_expired(&timeout)) { + if (IS_ENABLED(CONFIG_I2C_DEBUG)) { + printk(BIOS_ERR, + "0x%08x: ic_raw_intr_stat, I2C read timeout!\n", + status); + printk(BIOS_ERR, + "I2C segment[%d] failed\n", + seg_count - 1); + } return -1; + } /* Delay for a while */ udelay(1); @@ -299,5 +362,8 @@ regs->ic_tar = 0; /* Return the number of bytes transferred */ + if (IS_ENABLED(CONFIG_I2C_DEBUG)) + printk(BIOS_ERR, "0x%08x: bytes transferred\n", + bytes_transferred); return bytes_transferred; } -- To view, visit https://review.coreboot.org/20422 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia17be8b4213b13fd6c6a367d081414d0f21fbb0f Gerrit-Change-Number: 20422 Gerrit-PatchSet: 1 Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com>

1 0

Change in coreboot[master]: google/fizz: Enable wake-on-usb attach/detach
by build bot (Jenkins) (Code Review) 30 Jun '17

30 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20421 ) Change subject: google/fizz: Enable wake-on-usb attach/detach ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56441/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12030/ : SUCCESS -- To view, visit https://review.coreboot.org/20421 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I214d6557998bdaf1d327c2a45532461b95d56a96 Gerrit-Change-Number: 20421 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 23:22:54 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: google/fizz: Enable wake-on-usb attach/detach
by Shelley Chen (Code Review) 30 Jun '17

30 Jun '17

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/20421 Change subject: google/fizz: Enable wake-on-usb attach/detach ...................................................................... google/fizz: Enable wake-on-usb attach/detach BUG=b:62095784, b:35775024 BRANCH=None TEST=Run powerd_dbus_suspend from kernel. Plug in usb device and make sure wakes up. Change-Id: I214d6557998bdaf1d327c2a45532461b95d56a96 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/20421/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index d0bddba..d7b6727 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -7,6 +7,10 @@ register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(4) | USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(2) | USB_PORT_WAKE_ENABLE(3) | USB_PORT_WAKE_ENABLE(4) | USB_PORT_WAKE_ENABLE(5) | USB_PORT_WAKE_ENABLE(6)" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE -- To view, visit https://review.coreboot.org/20421 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I214d6557998bdaf1d327c2a45532461b95d56a96 Gerrit-Change-Number: 20421 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

1 0

Change in coreboot[master]: google/fizz: Override PL2 and SysPL2 values
by build bot (Jenkins) (Code Review) 30 Jun '17

30 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20420 ) Change subject: google/fizz: Override PL2 and SysPL2 values ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56440/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12028/ : SUCCESS -- To view, visit https://review.coreboot.org/20420 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b Gerrit-Change-Number: 20420 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 22:22:44 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Set PL2 and PsysPL2 MSRs
by build bot (Jenkins) (Code Review) 30 Jun '17

30 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20418 ) Change subject: soc/intel/skylake: Set PL2 and PsysPL2 MSRs ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56439/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12029/ : SUCCESS -- To view, visit https://review.coreboot.org/20418 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Gerrit-Change-Number: 20418 Gerrit-PatchSet: 3 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 22:17:14 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: google/fizz: Override PL2 and SysPL2 values
by Shelley Chen (Code Review) 30 Jun '17

30 Jun '17

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/20420 Change subject: google/fizz: Override PL2 and SysPL2 values ...................................................................... google/fizz: Override PL2 and SysPL2 values Set PL2 and SysPL2 for Fizz based on cpu id. BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output) Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/devicetree.cb M src/mainboard/google/fizz/mainboard.c 2 files changed, 37 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/20420/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a493de5..d0bddba 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -210,7 +210,6 @@ }" register "speed_shift_enable" = "1" - register "tdp_pl2_override" = "7" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index a925f08..75132bb 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -17,6 +17,8 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> +#include <intelblocks/mp_init.h> +#include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -24,6 +26,41 @@ static const char *oem_id = "GOOGLE"; static const char *oem_table_id = "FIZZ"; +/* + * mainboard_get_pl2 + * + * @return value Pl2 should be set to based on cpu id + * + * NOTE: This is purely based on cpu id, which only work for the + * current build because we have a different cpu id per sku. However, + * on the next build, we'll have distinct board ids per sku. We'll + * need to modify that at this point. + */ +u32 mainboard_get_pl2(void) +{ + struct cpuid_result cpuidr; + + cpuidr = cpuid(1); + printk(BIOS_DEBUG, "CPU(1): 0x%x\n", cpuidr.eax); + if (cpuidr.eax == CPUID_KABYLAKE_Y0) { + /* i7 needs higher pl2 */ + return 44; + } + return 29; +} + +/* + * mainboard_get_psyspl2 + * + * This is 90 Watts across all SKUs for Fizz + * + * @return value PsysPl2 should be set to + */ +u32 mainboard_get_psyspl2(void) +{ + return 90; +} + static void mainboard_init(device_t dev) { mainboard_ec_init(); -- To view, visit https://review.coreboot.org/20420 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b Gerrit-Change-Number: 20420 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

1 0

Change in coreboot[master]: Fizz: Set PL2 and PsysPL2 MSRs
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20418 ) Change subject: Fizz: Set PL2 and PsysPL2 MSRs ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56437/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12026/ : SUCCESS -- To view, visit https://review.coreboot.org/20418 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Gerrit-Change-Number: 20418 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 21:41:17 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: Fizz: Set PL2 and PsysPL2 MSRs
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20418 ) Change subject: Fizz: Set PL2 and PsysPL2 MSRs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56436/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12025/ : SUCCESS -- To view, visit https://review.coreboot.org/20418 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Gerrit-Change-Number: 20418 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 19:55:07 +0000 Gerrit-HasComments: No

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
227
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2017