coreboot-gerrit June 2017

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Change in coreboot[master]: Fizz: Set PL2 and PsysPL2 MSRs
by Shelley Chen (Code Review) 29 Jun '17

29 Jun '17

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/20418 Change subject: Fizz: Set PL2 and PsysPL2 MSRs ...................................................................... Fizz: Set PL2 and PsysPL2 MSRs BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output) Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/devicetree.cb M src/mainboard/google/fizz/mainboard.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/msr.h 5 files changed, 71 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/20418/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index a493de5..d0bddba 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -210,7 +210,6 @@ }" register "speed_shift_enable" = "1" - register "tdp_pl2_override" = "7" register "tcc_offset" = "10" # TCC of 90C # Use default SD card detect GPIO configuration diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index a925f08..4eb12d4 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <device/device.h> #include <ec/ec.h> +#include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -24,6 +25,41 @@ static const char *oem_id = "GOOGLE"; static const char *oem_table_id = "FIZZ"; +/* + * mainboard_get_pl2 + * + * @return value Pl2 should be set to based on cpu id + * + * NOTE: This is purely based on cpu id, which only work for the + * current build because we have a different cpu id per sku. However, + * on the next build, we'll have distinct board ids per sku. We'll + * need to modify that at this point. + */ +u32 mainboard_get_pl2(void) +{ + struct cpuid_result cpuidr; + + cpuidr = cpuid(1); + printk(BIOS_DEBUG, "CPU(1): 0x%x\n", cpuidr.eax); + if (cpuidr.eax == 0x806ea) { + /* i7 needs higher pl2 */ + return 44; + } + return 29; +} + +/* + * mainboard_get_psyspl2 + * + * This is 90 Watts across all SKUs for Fizz + * + * @return value PsysPl2 should be set to + */ +u32 mainboard_get_psyspl2(void) +{ + return 90; +} + static void mainboard_init(device_t dev) { mainboard_ec_init(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index e3be738..825fd15 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -104,6 +104,19 @@ [0x11] = 128, }; +u32 __attribute__((weak)) mainboard_get_pl2(void) +{ + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + + return conf->tdp_pl2_override; +} + +u32 __attribute__((weak)) mainboard_get_psyspl2(void) +{ + return 0; +} + /* * Configure processor power limits if possible * This must be done AFTER set of BIOS_RESET_CPL @@ -115,8 +128,8 @@ unsigned int power_unit; unsigned int tdp, min_power, max_power, max_time, tdp_pl2; u8 power_limit_1_val; - device_t dev = SA_DEV_ROOT; - config_t *conf = dev->chip_info; + u32 pl2_val; + u32 psyspl2_val; if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = 28; @@ -159,10 +172,12 @@ limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; - /* Set short term power limit to 1.25 * TDP */ + /* Set short term power limit to 1.25 TDP if no config given */ limit.hi = 0; - tdp_pl2 = (conf->tdp_pl2_override == 0) ? - (tdp * 125) / 100 : (conf->tdp_pl2_override * power_unit); + pl2_val = mainboard_get_pl2(); + tdp_pl2 = (pl2_val == 0) ? + (tdp * 125) / 100 : (pl2_val * power_unit); + printk(BIOS_DEBUG, "CPU PL2 = %u Watts\n", pl2_val); limit.hi |= (tdp_pl2) & PKG_POWER_LIMIT_MASK; limit.hi |= PKG_POWER_LIMIT_CLAMP; limit.hi |= PKG_POWER_LIMIT_EN; @@ -174,6 +189,18 @@ MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; + /* Set PsysPl2 */ + limit.lo = 0; + limit.hi = 0; + psyspl2_val = mainboard_get_psyspl2(); + if (psyspl2_val) { + printk(BIOS_DEBUG, "CPU PsysPL2 = %u Watts\n", psyspl2_val); + limit.hi |= (psyspl2_val) & PKG_POWER_LIMIT_MASK; + limit.hi |= PKG_POWER_LIMIT_EN; + + wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); + } + /* Set DDR RAPL power limit by copying from MMIO to MSR */ msr.lo = MCHBAR32(MCH_DDR_POWER_LIMIT_LO); msr.hi = MCHBAR32(MCH_DDR_POWER_LIMIT_HI); diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h index 059367a..47d3e63 100644 --- a/src/soc/intel/skylake/include/soc/cpu.h +++ b/src/soc/intel/skylake/include/soc/cpu.h @@ -50,6 +50,8 @@ (IRTL_1024_NS >> 10)) /* Configure power limits for turbo mode */ +u32 mainboard_get_pl2(void); +u32 mainboard_get_psyspl2(void); void set_power_limits(u8 power_limit_1_time); /* CPU identification */ diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index bb4b8e7..ef4027a 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -41,5 +41,6 @@ #define MSR_VR_MISC_CONFIG2 0x636 #define MSR_PP0_POWER_LIMIT 0x638 #define MSR_PP1_POWER_LIMIT 0x640 +#define MSR_PLATFORM_POWER_LIMIT 0x65c #endif -- To view, visit https://review.coreboot.org/20418 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Gerrit-Change-Number: 20418 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: northbridge/intel: Add whitespace around '<<' and '|'
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20398 ) Change subject: northbridge/intel: Add whitespace around '<<' and '|' ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56435/ : SUCCESS -- To view, visit https://review.coreboot.org/20398 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Gerrit-Change-Number: 20398 Gerrit-PatchSet: 8 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 17:00:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: northbridge/intel: Add whitespace around '<<' and '|'
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20398 ) Change subject: northbridge/intel: Add whitespace around '<<' and '|' ...................................................................... Patch Set 7: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/56434/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/12024/ : ABORTED -- To view, visit https://review.coreboot.org/20398 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Gerrit-Change-Number: 20398 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 16:54:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: northbridge/intel: Add whitespace around '<<'
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20398 ) Change subject: northbridge/intel: Add whitespace around '<<' ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56433/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12023/ : SUCCESS -- To view, visit https://review.coreboot.org/20398 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0bf2653c08c4955bf95dcbec2d5a0c891339866b Gerrit-Change-Number: 20398 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 16:46:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common: Add initial support for AMD PSP
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19753 ) Change subject: soc/amd/common: Add initial support for AMD PSP ...................................................................... Patch Set 15: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56432/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12022/ : SUCCESS -- To view, visit https://review.coreboot.org/19753 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87 Gerrit-Change-Number: 19753 Gerrit-PatchSet: 15 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 15:14:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Remove unnecessary P-State and Flex Ratio...
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20050 ) Change subject: soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignment ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56428/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12019/ : SUCCESS -- To view, visit https://review.coreboot.org/20050 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3 Gerrit-Change-Number: 20050 Gerrit-PatchSet: 7 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 29 Jun 2017 12:57:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge/northbridge.c: remove unnecessary null c...
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20415 ) Change subject: soc/amd/stoneyridge/northbridge.c: remove unnecessary null check ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56427/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12018/ : SUCCESS -- To view, visit https://review.coreboot.org/20415 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6a53df8b8d1596ad0eb1d8f0fa200cccf9509cf Gerrit-Change-Number: 20415 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 09:26:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/siemens/mc_apl1: Set up RTC backup mode to primary cell
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20414 ) Change subject: mb/siemens/mc_apl1: Set up RTC backup mode to primary cell ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56426/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12017/ : SUCCESS -- To view, visit https://review.coreboot.org/20414 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7c0c26a0ed5d8f48587acc917f8bb1c5c2b8869a Gerrit-Change-Number: 20414 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 09:23:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge/northbridge.c: remove unnecessary null c...
by Martin Kepplinger (Code Review) 29 Jun '17

29 Jun '17

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/20415 Change subject: soc/amd/stoneyridge/northbridge.c: remove unnecessary null check ...................................................................... soc/amd/stoneyridge/northbridge.c: remove unnecessary null check Checking for NULL here doesn't help here. We *rely* on cdb_dev to exist directly before this check. Coverity had found this: *** CID 1376664: Null pointer dereferences (REVERSE_INULL) /src/soc/amd/stoneyridge/northbridge.c: 666 in cpu_bus_scan() 660 * this silicon. It is an SOC and can't have >= 16 APICs, but 661 * we will start numbering at 0x10. We also know there is only 662 * on physical node (module in AMD speak). 663 */ 664 665 lapicid_start = 0x10; /* Get this from devicetree? see comment above. */ CID 1376664: Null pointer dereferences (REVERSE_INULL) Null-checking "cdb_dev" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 666 enable_node = cdb_dev && cdb_dev->enabled; 667 cpu_bus = dev->link_list; 668 669 for (j = 0; j <= siblings; j++ ) { 670 apic_id = lapicid_start + j; 671 printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x, apicid=0x%x\n", Change-Id: Ic6a53df8b8d1596ad0eb1d8f0fa200cccf9509cf Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/20415/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 009c6df..fac966f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -676,7 +676,7 @@ */ lapicid_start = 0x10; /* Get this from devicetree? see comment above. */ - enable_node = cdb_dev && cdb_dev->enabled; + enable_node = cdb_dev->enabled; cpu_bus = dev->link_list; for (j = 0 ; j <= siblings ; j++) { -- To view, visit https://review.coreboot.org/20415 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic6a53df8b8d1596ad0eb1d8f0fa200cccf9509cf Gerrit-Change-Number: 20415 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de>

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Change in coreboot[master]: mb/siemens/mc_bdx1: Set up RTC backup mode to primary cell
by build bot (Jenkins) (Code Review) 29 Jun '17

29 Jun '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20413 ) Change subject: mb/siemens/mc_bdx1: Set up RTC backup mode to primary cell ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/56425/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/12016/ : SUCCESS -- To view, visit https://review.coreboot.org/20413 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9733aa9f2981a25f6d42279eff0c4980e5eb5a5a Gerrit-Change-Number: 20413 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2017 09:19:55 +0000 Gerrit-HasComments: No

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coreboot-gerrit June 2017