coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/arm/armv7: Correct checkpatch errors
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19996 ) Change subject: arch/arm/armv7: Correct checkpatch errors ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/54637/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/10349/ : SUCCESS -- To view, visit https://review.coreboot.org/19996 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I69d50030b07b1919555feca44967472922176a81 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: payloads/external/tianocore: Update to build uefi corebootpa...
by Martin Roth (Code Review) 31 May '17

31 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/15057 ) Change subject: payloads/external/tianocore: Update to build uefi corebootpayload ...................................................................... Patch Set 21: Rebased on top of the current tree to restart work. -- To view, visit https://review.coreboot.org/15057 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9719ca5c39fccb856dfe096d449760a937d51fd1 Gerrit-PatchSet: 21 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maurice Ma Gerrit-Reviewer: Maurice Ma <mauricexma(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Pablo Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Prabal Saha <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: payloads/external/tianocore: Update to build uefi corebootpa...
by Martin Roth (Code Review) 31 May '17

31 May '17

Hello Lee Leahy, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/15057 to look at the new patch set (#21). Change subject: payloads/external/tianocore: Update to build uefi corebootpayload ...................................................................... payloads/external/tianocore: Update to build uefi corebootpayload Update the existing tianocore payload (which didn't do any more than adding an elf payload with a specific name) to fetch and build the UEFI corebootPayloadPackage Only compiles with GCC 4.8, therefore the host compiler is used. Currently working if patches are merged into the upstream edk2 repository. Missing: Intel GOP and GOP FB support Change-Id: I9719ca5c39fccb856dfe096d449760a937d51fd1 Signed-off-by: Martin Roth <martinroth(a)google.com> Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M .gitignore M payloads/Makefile.inc M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Kconfig.name A payloads/external/tianocore/Makefile 6 files changed, 166 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/15057/21 -- To view, visit https://review.coreboot.org/15057 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9719ca5c39fccb856dfe096d449760a937d51fd1 Gerrit-PatchSet: 21 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maurice Ma Gerrit-Reviewer: Maurice Ma <mauricexma(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Pablo Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Prabal Saha <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/arm/armv7: Correct checkpatch errors
by Logan Carlson (Code Review) 31 May '17

31 May '17

Logan Carlson has uploaded a new change for review. ( https://review.coreboot.org/19996 ) Change subject: arch/arm/armv7: Correct checkpatch errors ...................................................................... arch/arm/armv7: Correct checkpatch errors - Correct whitespace issues with files under arch/arm/armv7. - Fix comments and remove unnecessary line continuations in mmu.c Change-Id: I69d50030b07b1919555feca44967472922176a81 Signed-off-by: Logan Carlson <logancarlson(a)google.com> --- M src/arch/arm/armv7/cache.c M src/arch/arm/armv7/mmu.c M src/arch/arm/armv7/thread.c 3 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19996/1 diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index eea514b..ef3ad01 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -84,7 +84,7 @@ dsb(); while ((void *)line < addr + len) { - switch(op) { + switch (op) { case OP_DCCIMVAC: dccimvac(line); break; diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 4123bb4..20cb12f 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -43,14 +43,14 @@ /* See B3.6.2 of ARMv7 Architecture Reference Manual */ /* TODO: Utilize the contiguous hint flag */ #define ATTR_BLOCK (\ - 0ULL << 54 | /* XN. 0:Not restricted */ \ - 0ULL << 53 | /* PXN. 0:Not restricted */ \ - 1 << 10 | /* AF. 1:Accessed. This is to prevent access \ - * fault when accessed for the first time */ \ - 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \ - 0 << 5 | /* NS. 0:Output address is in Secure space */ \ - 0 << 1 | /* block/table. 0:block entry */ \ - 1 << 0 /* validity. 1:valid */ \ + 0ULL << 54 | /* XN. 0:Not restricted */ + 0ULL << 53 | /* PXN. 0:Not restricted */ + 1 << 10 | /* AF. 1:Accessed. This is to prevent access + * fault when accessed for the first time */ + 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ + 0 << 5 | /* NS. 0:Output address is in Secure space */ + 0 << 1 | /* block/table. 0:block entry */ + 1 << 0 /* validity. 1:valid */ ) #define ATTR_PAGE (ATTR_BLOCK | 1 << 1) #define ATTR_NEXTLEVEL (0x3) @@ -280,12 +280,12 @@ table[0] = ATTR_UNUSED; if (CONFIG_ARM_LPAE) { - pte_t *const pgd_buff = (pte_t*)(_ttb + 16*KiB); + pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB); pte_t *pmd = ttb_buff; int i; printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", - ttb_buff); + ttb_buff); ASSERT((read_mmfr0() & 0xf) >= 5); /* @@ -308,7 +308,7 @@ */ for (i = 0; i < 4; i++) { pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | - ATTR_NEXTLEVEL; + ATTR_NEXTLEVEL; pmd += BLOCK_SIZE / PAGE_SIZE; } diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c index a3b1d0c..3b8d1af 100644 --- a/src/arch/arm/armv7/thread.c +++ b/src/arch/arm/armv7/thread.c @@ -39,7 +39,7 @@ } void arch_prepare_thread(struct thread *t, - void asmlinkage (*thread_entry)(void *), void *arg) + void asmlinkage(*thread_entry)(void *), void *arg) { uintptr_t stack = t->stack_current; int i; -- To view, visit https://review.coreboot.org/19996 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I69d50030b07b1919555feca44967472922176a81 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com>

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Change in coreboot[master]: mainboard/google/poppy: Power down camera rails when suspending
by Furquan Shaikh (Code Review) 31 May '17

31 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19953 ) Change subject: mainboard/google/poppy: Power down camera rails when suspending ...................................................................... mainboard/google/poppy: Power down camera rails when suspending BUG=b:62147763 Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19953 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/poppy/smihandler.c M src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h 2 files changed, 15 insertions(+), 0 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c index 88aa905..30b009d 100644 --- a/src/mainboard/google/poppy/smihandler.c +++ b/src/mainboard/google/poppy/smihandler.c @@ -15,8 +15,11 @@ #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> +#include <gpio.h> +#include <soc/gpio.h> #include <soc/smm.h> +#include <variant/gpio.h> #include <variant/ec.h> void mainboard_smi_espi_handler(void) @@ -24,10 +27,18 @@ chromeec_smi_process_events(); } +static void mainboard_gpio_smi_sleep(void) +{ + /* Hold camera device in reset and then power it down. */ + gpio_set(EN_CAM_PMIC_RST_L, 0); + gpio_set(EN_PP3300_DX_CAM, 0); +} + void mainboard_smi_sleep(u8 slp_typ) { chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); + mainboard_gpio_smi_sleep(); } int mainboard_smi_apmc(u8 apmc) diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h index 628483b..4c9ade3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/gpio.h @@ -37,4 +37,8 @@ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI +/* Power rail control signals */ +#define EN_PP3300_DX_CAM GPP_C11 +#define EN_CAM_PMIC_RST_L GPP_C10 + #endif /* BASEBOARD_GPIO_H */ -- To view, visit https://review.coreboot.org/19953 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Iba88fed972b847448e01fcfca8c7129d950244c2 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x/early_usb: Use register name
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19954 ) Change subject: sb/intel/bd82x6x/early_usb: Use register name ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54636/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10348/ : SUCCESS -- To view, visit https://review.coreboot.org/19954 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/slippy: add board-specific USB port info
by Martin Roth (Code Review) 31 May '17

31 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19967 ) Change subject: google/slippy: add board-specific USB port info ...................................................................... google/slippy: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each slippy variant has slightly different USB port config; data for falco and leon to be added once available Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19967 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/slippy/acpi/mainboard.asl A src/mainboard/google/slippy/variants/falco/include/variant/acpi/usb.asl A src/mainboard/google/slippy/variants/leon/include/variant/acpi/usb.asl A src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl A src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl 5 files changed, 249 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/slippy/acpi/mainboard.asl b/src/mainboard/google/slippy/acpi/mainboard.asl index 7605e9e..f12a440 100644 --- a/src/mainboard/google/slippy/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/acpi/mainboard.asl @@ -23,3 +23,6 @@ } #include <variant/acpi/mainboard.asl> + +/* USB port entries */ +#include <variant/acpi/usb.asl> diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl new file mode 100644 index 0000000..9227680 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT1) +{ + // WWAN M.2 Slot + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Left USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // Right USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl new file mode 100644 index 0000000..1799640 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT1) +{ + // Left Front USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Left Rear USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP2) +{ + // Rear USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} -- To view, visit https://review.coreboot.org/19967 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/beltino: add board-specific USB port info
by Martin Roth (Code Review) 31 May '17

31 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19966 ) Change subject: google/beltino: add board-specific USB port info ...................................................................... google/beltino: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. All beltino variants use the exact same USB port layout. Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19966 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/beltino/acpi/mainboard.asl A src/mainboard/google/beltino/acpi/usb.asl 2 files changed, 147 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index 03dc5e0..e6f931e 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -67,3 +67,6 @@ } } } + +/* USB port entries */ +#include "acpi/usb.asl" diff --git a/src/mainboard/google/beltino/acpi/usb.asl b/src/mainboard/google/beltino/acpi/usb.asl new file mode 100644 index 0000000..59c9654 --- /dev/null +++ b/src/mainboard/google/beltino/acpi/usb.asl @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // USB 2.0 Port 1 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // USB 2.0 Port 2 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // USB 2.0 Port 3 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT6) +{ + // USB 2.0 Port 4 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // USB 3.0 Port 1 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP2) +{ + // USB 3.0 Port 2 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP3) +{ + // USB 3.0 Port 3 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP4) +{ + // USB 3.0 Port 4 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} -- To view, visit https://review.coreboot.org/19966 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/lynxpoint: add missing USB port defs
by Martin Roth (Code Review) 31 May '17

31 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19965 ) Change subject: sb/lynxpoint: add missing USB port defs ...................................................................... sb/lynxpoint: add missing USB port defs Add device/address stubs for XHCI USB ports 7, 10-13. Stub data will be supplemented by board-specific info added in subsequent commits. Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19965 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/lynxpoint/acpi/usb.asl 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 85e4390..ee88303 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -49,7 +49,6 @@ { Name (_ADR, 0x00000000) - // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 Device (PRT3) { Name (_ADR, 3) } // USB Port 2 @@ -409,12 +408,16 @@ Return (PCKG) } - // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 Device (PRT3) { Name (_ADR, 3) } // USB Port 2 Device (PRT4) { Name (_ADR, 4) } // USB Port 3 Device (PRT5) { Name (_ADR, 5) } // USB Port 4 Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + Device (PRT7) { Name (_ADR, 7) } // USB Port 6 + Device (SSP1) { Name (_ADR, 10) } // USB Port 10 + Device (SSP2) { Name (_ADR, 11) } // USB Port 11 + Device (SSP3) { Name (_ADR, 12) } // USB Port 12 + Device (SSP4) { Name (_ADR, 13) } // USB Port 13 } } -- To view, visit https://review.coreboot.org/19965 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/lynxpoint: add ACPI method to generate USB port info
by Martin Roth (Code Review) 31 May '17

31 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19964 ) Change subject: sb/lynxpoint: add ACPI method to generate USB port info ...................................................................... sb/lynxpoint: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19964 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/southbridge/intel/lynxpoint/acpi/usb.asl 1 file changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index b02cbfe..85e4390 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -393,6 +393,22 @@ { Name (_ADR, 0x00000000) + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) { + Name (PCKG, Package (0x01) { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + Return (PCKG) + } + // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 -- To view, visit https://review.coreboot.org/19964 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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