coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/include/device: Add System Agent (SA) device ids
by Furquan Shaikh (Code Review) 31 May '17

31 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19794 ) Change subject: src/include/device: Add System Agent (SA) device ids ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19794/2/src/include/device/pci_ids.h File src/include/device/pci_ids.h: PS2, Line 2820: INTEL? -- To view, visit https://review.coreboot.org/19794 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iddc9f8187d1ff4a51bf3bf42a266b79007c42f3b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/apollolake: Use Intel timer common code
by Aamir Bohra (Code Review) 31 May '17

31 May '17

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19913 ) Change subject: soc/intel/apollolake: Use Intel timer common code ...................................................................... soc/intel/apollolake: Use Intel timer common code Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc D src/soc/intel/apollolake/tsc_freq.c 3 files changed, 1 insertion(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/19913/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 8312611..21b9132 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -63,6 +63,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 33bc7cf..a2768e7 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -18,7 +18,6 @@ bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c -bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S @@ -32,7 +31,6 @@ romstage-y += memmap.c romstage-y += meminit.c romstage-y += mmap_boot.c -romstage-y += tsc_freq.c romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c @@ -42,7 +40,6 @@ smm-y += gpio.c smm-y += smihandler.c smm-y += spi.c -smm-y += tsc_freq.c smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c @@ -65,7 +62,6 @@ ramstage-y += nhlt.c ramstage-y += northbridge.c ramstage-y += spi.c -ramstage-y += tsc_freq.c ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += reset.c @@ -79,7 +75,6 @@ postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c -postcar-y += tsc_freq.c postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S @@ -89,7 +84,6 @@ verstage-y += memmap.c verstage-y += mmap_boot.c verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c -verstage-y += tsc_freq.c verstage-y += pmutil.c verstage-y += reset.c verstage-y += spi.c diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c deleted file mode 100644 index db456bf..0000000 --- a/src/soc/intel/apollolake/tsc_freq.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/intel/speedstep.h> -#include <cpu/intel/turbo.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include <soc/cpu.h> -#include <console/console.h> -#include <delay.h> -#include "chip.h" - -unsigned long tsc_freq_mhz(void) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); -} \ No newline at end of file -- To view, visit https://review.coreboot.org/19913 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I7b415711d01ddc0d998eba62de2c2139045efa80 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Use Intel timer common code
by Aamir Bohra (Code Review) 31 May '17

31 May '17

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19912 ) Change subject: soc/intel/skylake: Use Intel timer common code ...................................................................... soc/intel/skylake: Use Intel timer common code Use timer code from soc/intel/common. This code removes monotonic timer refrence w.r.t MSR 24Mhz counter(0x637) and use tsc timer. Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/monotonic_timer.c D src/soc/intel/skylake/tsc_freq.c 4 files changed, 3 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/19912/4 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index c36a4a7..affb81d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -63,6 +63,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SATA select SOC_INTEL_COMMON_BLOCK_SMBUS + select SOC_INTEL_COMMON_BLOCK_TIMER select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_NHLT @@ -73,6 +74,7 @@ select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC select ACPI_NHLT @@ -160,7 +162,7 @@ default 0x400000 config MONOTONIC_TIMER_MSR - def_bool y + def_bool n select HAVE_MONOTONIC_TIMER help Provide a monotonic timer using the 24MHz MSR counter. diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 1ea5287..29a89d3 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -18,33 +18,27 @@ bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c bootblock-y += gpio.c bootblock-y += gspi.c -bootblock-y += monotonic_timer.c bootblock-y += pch.c bootblock-y += pmutil.c bootblock-y += spi.c -bootblock-y += tsc_freq.c verstage-y += gspi.c -verstage-y += monotonic_timer.c verstage-y += pch.c verstage-$(CONFIG_UART_DEBUG) += uart_debug.c verstage-y += pmutil.c verstage-y += i2c.c verstage-y += spi.c -verstage-y += tsc_freq.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c romstage-y += memmap.c -romstage-y += monotonic_timer.c romstage-y += me.c romstage-y += pch.c romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += spi.c -romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c @@ -62,7 +56,6 @@ ramstage-y += lpc.c ramstage-y += me.c ramstage-y += memmap.c -ramstage-y += monotonic_timer.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c ramstage-y += pch.c ramstage-y += pei_data.c @@ -74,23 +67,18 @@ ramstage-y += smi.c ramstage-y += spi.c ramstage-y += systemagent.c -ramstage-y += tsc_freq.c ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-y += vr_config.c smm-y += gpio.c -smm-y += monotonic_timer.c smm-y += pch.c smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c -smm-y += tsc_freq.c smm-$(CONFIG_UART_DEBUG) += uart_debug.c postcar-y += memmap.c -postcar-y += monotonic_timer.c -postcar-y += tsc_freq.c postcar-$(CONFIG_UART_DEBUG) += uart_debug.c # cpu_microcode_bins += ??? diff --git a/src/soc/intel/skylake/monotonic_timer.c b/src/soc/intel/skylake/monotonic_timer.c deleted file mode 100644 index 7e33223..0000000 --- a/src/soc/intel/skylake/monotonic_timer.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <timer.h> -#include <soc/msr.h> - -static inline uint32_t read_counter_msr(void) -{ - /* - * Even though the MSR is 64-bit it is assumed that the hardware - * is polled frequently enough to only use the lower 32-bits. - */ - msr_t counter_msr; - - counter_msr = rdmsr(MSR_COUNTER_24_MHZ); - - return counter_msr.lo; -} - -void timer_monotonic_get(struct mono_time *mt) -{ - /* Always increases. Don't normalize to 0 between stages. */ - mono_time_set_usecs(mt, read_counter_msr() / 24); -} diff --git a/src/soc/intel/skylake/tsc_freq.c b/src/soc/intel/skylake/tsc_freq.c deleted file mode 100644 index 7654e83..0000000 --- a/src/soc/intel/skylake/tsc_freq.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include <intelblocks/cpu.h> -#include <soc/msr.h> - -unsigned long tsc_freq_mhz(void) -{ - msr_t platform_info; - - platform_info = rdmsr(MSR_PLATFORM_INFO); - return CPU_BCLK * ((platform_info.lo >> 8) & 0xff); -} -- To view, visit https://review.coreboot.org/19912 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Add common Intel timer code
by Aamir Bohra (Code Review) 31 May '17

31 May '17

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19911 ) Change subject: soc/intel/common: Add common Intel timer code ...................................................................... soc/intel/common: Add common Intel timer code Add common timer code to get tsc frequency(Mhz). Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/timer/Kconfig A src/soc/intel/common/block/timer/Makefile.inc A src/soc/intel/common/block/timer/timer.c 3 files changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/19911/2 diff --git a/src/soc/intel/common/block/timer/Kconfig b/src/soc/intel/common/block/timer/Kconfig new file mode 100644 index 0000000..a415045 --- /dev/null +++ b/src/soc/intel/common/block/timer/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_TIMER + bool + help + Intel Processor common TIMER support diff --git a/src/soc/intel/common/block/timer/Makefile.inc b/src/soc/intel/common/block/timer/Makefile.inc new file mode 100644 index 0000000..b562c50 --- /dev/null +++ b/src/soc/intel/common/block/timer/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c +postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER) += timer.c diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c new file mode 100644 index 0000000..c93aebd --- /dev/null +++ b/src/soc/intel/common/block/timer/timer.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <intelblocks/msr.h> + +/* CPU bus clock is fixed at 100MHz */ +#define CPU_BCLK 100 + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + return (CPU_BCLK * ((msr.lo >> 8) & 0xff)); +} -- To view, visit https://review.coreboot.org/19911 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd4b24735c74c636348fc32afbcc267e384cb610 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Use common gpio for apollolake[WIP]
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19949 ) Change subject: soc/intel/apollolake: Use common gpio for apollolake[WIP] ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54640/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10352/ : SUCCESS -- To view, visit https://review.coreboot.org/19949 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 16: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54639/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10351/ : SUCCESS -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 16 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use common gpio for apollolake[WIP]
by Hannah Williams (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19949 to look at the new patch set (#4). Change subject: soc/intel/apollolake: Use common gpio for apollolake[WIP] ...................................................................... soc/intel/apollolake: Use common gpio for apollolake[WIP] Will remove WIP after testing this patch Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc R src/soc/intel/apollolake/acpi/gpio_apl.asl M src/soc/intel/apollolake/acpi/gpiolib.asl M src/soc/intel/apollolake/acpi/southbridge.asl M src/soc/intel/apollolake/chip.h D src/soc/intel/apollolake/gpio.c A src/soc/intel/apollolake/gpio_apl.c M src/soc/intel/apollolake/include/soc/gpio.h R src/soc/intel/apollolake/include/soc/gpio_apl.h 10 files changed, 135 insertions(+), 683 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19949/4 -- To view, visit https://review.coreboot.org/19949 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19759 to look at the new patch set (#16). Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... soc/intel/common/block/gpio: Port gpio code from Apollolake to common Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- A src/soc/intel/common/block/gpio/Kconfig A src/soc/intel/common/block/gpio/Makefile.inc A src/soc/intel/common/block/gpio/gpio.c A src/soc/intel/common/block/include/intelblocks/gpio.h A src/soc/intel/common/block/include/intelblocks/gpio_defs.h 5 files changed, 819 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/19759/16 -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 16 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 31 May '17

31 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/#/c/19759/14/src/soc/intel/common/block/gpio/gp… File src/soc/intel/common/block/gpio/gpio.c: PS14, Line 132: : config_offset = pad_config_offset(comm, cfg->pad); : pad_conf0 = pcr_read32(comm->port, config_offset); : pad_conf1 = pcr_read32(comm->port, config_offset + GPIO_DWx_SIZE(1)); : if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) : printk(BIOS_DEBUG, : "gpio_padcfg [0x%02x, %d] DW0 [0x%08x : 0x%08x] " : "DW1 [0x%08x : 0x%08x]\n", : comm->port, : (cfg->pad - comm->first_pad), : pad_conf0,/* old value */ : cfg->pad_config0, /* new value */ : pad_conf1,/* old value */ : cfg->pad_config1); /* new value */ : : pad_conf0 &= ~PAD_DW0_MASK; : pcr_write32(comm->port, config_offset, pad_conf0 | : (cfg->pad_config0 & PAD_DW0_MASK)); : pad_conf1 &= ~PAD_DW1_MASK; : pcr_write32(comm->port, config_offset + GPIO_DWx_SIZE(1), : pad_conf1 | (cfg->pad_config1 & PAD_DW1_MASK)); Shall I change this logic to only configure what comes in from the gpio table and remove PAD_DW0_MASK and PAD_DW1_MASK? Basically it would be to move to existing APL code -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 14 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: payloads/external/tianocore: Update to build uefi corebootpa...
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/15057 ) Change subject: payloads/external/tianocore: Update to build uefi corebootpayload ...................................................................... Patch Set 21: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54638/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10350/ : SUCCESS -- To view, visit https://review.coreboot.org/15057 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9719ca5c39fccb856dfe096d449760a937d51fd1 Gerrit-PatchSet: 21 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maurice Ma Gerrit-Reviewer: Maurice Ma <mauricexma(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Pablo Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Prabal Saha <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017